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|
---------- Begin Simulation Statistics ----------
sim_seconds 2.326119 # Number of seconds simulated
sim_ticks 2326118592000 # Number of ticks simulated
final_tick 2326118592000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 546207 # Simulator instruction rate (inst/s)
host_op_rate 740969 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 919614125 # Simulator tick rate (ticks/s)
host_mem_usage 332488 # Number of bytes of host memory used
host_seconds 2529.45 # Real time elapsed on the host
sim_insts 1381604339 # Number of instructions simulated
sim_ops 1874244941 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 113472 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 30232512 # Number of bytes read from this memory
system.physmem.bytes_read::total 30345984 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 113472 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 113472 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 4230336 # Number of bytes written to this memory
system.physmem.bytes_written::total 4230336 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 1773 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 472383 # Number of read requests responded to by this memory
system.physmem.num_reads::total 474156 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 66099 # Number of write requests responded to by this memory
system.physmem.num_writes::total 66099 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 48782 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 12996978 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 13045760 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 48782 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 48782 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1818624 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1818624 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1818624 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 48782 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 12996978 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 14864384 # Total bandwidth to/from this memory (bytes/s)
system.membus.throughput 14864384 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 408063 # Transaction distribution
system.membus.trans_dist::ReadResp 408063 # Transaction distribution
system.membus.trans_dist::Writeback 66099 # Transaction distribution
system.membus.trans_dist::ReadExReq 66093 # Transaction distribution
system.membus.trans_dist::ReadExResp 66093 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1014411 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1014411 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34576320 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 34576320 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 34576320 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 1069047000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 4267404000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 1411 # Number of system calls
system.cpu.numCycles 4652237184 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 1381604339 # Number of instructions committed
system.cpu.committedOps 1874244941 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1653698868 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 52289415 # Number of float alu accesses
system.cpu.num_func_calls 80372855 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 230619738 # number of instructions that are conditional controls
system.cpu.num_int_insts 1653698868 # number of integer instructions
system.cpu.num_fp_insts 52289415 # number of float instructions
system.cpu.num_int_register_reads 10644316447 # number of times the integer registers were read
system.cpu.num_int_register_writes 1874331393 # number of times the integer registers were written
system.cpu.num_fp_register_reads 60540850 # number of times the floating registers were read
system.cpu.num_fp_register_writes 46777010 # number of times the floating registers were written
system.cpu.num_mem_refs 908382479 # number of memory refs
system.cpu.num_load_insts 631387181 # Number of load instructions
system.cpu.num_store_insts 276995298 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 4652237184 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.Branches 298259106 # Number of branches fetched
system.cpu.icache.tags.replacements 18364 # number of replacements
system.cpu.icache.tags.tagsinuse 1392.317060 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 1390251699 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 19803 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 70204.095289 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 1392.317060 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.679842 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.679842 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1439 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1339 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.702637 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 2780562807 # Number of tag accesses
system.cpu.icache.tags.data_accesses 2780562807 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 1390251699 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1390251699 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1390251699 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 1390251699 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 1390251699 # number of overall hits
system.cpu.icache.overall_hits::total 1390251699 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 19803 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 19803 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 19803 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 19803 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 19803 # number of overall misses
system.cpu.icache.overall_misses::total 19803 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 331911000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 331911000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 331911000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 331911000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 331911000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 331911000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 1390271502 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 1390271502 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 1390271502 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 1390271502 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 1390271502 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 1390271502 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000014 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000014 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000014 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000014 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000014 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000014 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16760.642327 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 16760.642327 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 16760.642327 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 16760.642327 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 16760.642327 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 16760.642327 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 19803 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 19803 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 19803 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 19803 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 19803 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 19803 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 292305000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 292305000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 292305000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 292305000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 292305000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 292305000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000014 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000014 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000014 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000014 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000014 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000014 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14760.642327 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14760.642327 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14760.642327 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 14760.642327 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14760.642327 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 14760.642327 # average overall mshr miss latency
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system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1387 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31024 # Occupied blocks per task id
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22680.810036 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22680.810036 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49141.055235 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49141.055235 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23936.489545 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 23936.489545 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23936.489545 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 23936.489545 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.throughput 45389617 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 1480676 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 1480676 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 96257 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 72780 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 72780 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 39606 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3163563 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 3203169 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1267392 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104314240 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total 105581632 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus 105581632 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 921113500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 29704500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 2300479500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
---------- End Simulation Statistics ----------
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