path: root/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.043459                       # Number of seconds simulated
sim_ticks                                 43458818000                       # Number of ticks simulated
final_tick                                43458818000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 114678                       # Simulator instruction rate (inst/s)
host_op_rate                                   114678                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               56415550                       # Simulator tick rate (ticks/s)
host_mem_usage                                 273516                       # Number of bytes of host memory used
host_seconds                                   770.33                       # Real time elapsed on the host
sim_insts                                    88340673                       # Number of instructions simulated
sim_ops                                      88340673                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst            454592                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          10138368                       # Number of bytes read from this memory
system.physmem.bytes_read::total             10592960                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       454592                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          454592                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      7295808                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7295808                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst               7103                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             158412                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                165515                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          113997                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               113997                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst             10460294                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data            233286787                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total               243747080                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst        10460294                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total           10460294                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks         167878657                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total              167878657                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks         167878657                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst            10460294                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data           233286787                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              411625737                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        165515                       # Number of read requests accepted
system.physmem.writeReqs                       113997                       # Number of write requests accepted
system.physmem.readBursts                      165515                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     113997                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 10592576                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                       384                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   7294400                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  10592960                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                7295808                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                        6                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               10379                       # Per bank write bursts
system.physmem.perBankRdBursts::1               10437                       # Per bank write bursts
system.physmem.perBankRdBursts::2               10256                       # Per bank write bursts
system.physmem.perBankRdBursts::3               10015                       # Per bank write bursts
system.physmem.perBankRdBursts::4               10350                       # Per bank write bursts
system.physmem.perBankRdBursts::5               10362                       # Per bank write bursts
system.physmem.perBankRdBursts::6                9796                       # Per bank write bursts
system.physmem.perBankRdBursts::7               10273                       # Per bank write bursts
system.physmem.perBankRdBursts::8               10509                       # Per bank write bursts
system.physmem.perBankRdBursts::9               10590                       # Per bank write bursts
system.physmem.perBankRdBursts::10              10477                       # Per bank write bursts
system.physmem.perBankRdBursts::11              10188                       # Per bank write bursts
system.physmem.perBankRdBursts::12              10236                       # Per bank write bursts
system.physmem.perBankRdBursts::13              10580                       # Per bank write bursts
system.physmem.perBankRdBursts::14              10468                       # Per bank write bursts
system.physmem.perBankRdBursts::15              10593                       # Per bank write bursts
system.physmem.perBankWrBursts::0                7081                       # Per bank write bursts
system.physmem.perBankWrBursts::1                7259                       # Per bank write bursts
system.physmem.perBankWrBursts::2                7255                       # Per bank write bursts
system.physmem.perBankWrBursts::3                6998                       # Per bank write bursts
system.physmem.perBankWrBursts::4                7125                       # Per bank write bursts
system.physmem.perBankWrBursts::5                7170                       # Per bank write bursts
system.physmem.perBankWrBursts::6                6769                       # Per bank write bursts
system.physmem.perBankWrBursts::7                7092                       # Per bank write bursts
system.physmem.perBankWrBursts::8                7216                       # Per bank write bursts
system.physmem.perBankWrBursts::9                6938                       # Per bank write bursts
system.physmem.perBankWrBursts::10               7083                       # Per bank write bursts
system.physmem.perBankWrBursts::11               6989                       # Per bank write bursts
system.physmem.perBankWrBursts::12               6963                       # Per bank write bursts
system.physmem.perBankWrBursts::13               7284                       # Per bank write bursts
system.physmem.perBankWrBursts::14               7281                       # Per bank write bursts
system.physmem.perBankWrBursts::15               7472                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                     43458797000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  165515                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 113997                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                     69517                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     66164                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     19662                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                     10165                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                      573                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                      585                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                      866                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     1934                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     2737                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     4571                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     5772                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     6159                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     6456                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     6714                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     7156                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     7301                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     7672                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     8033                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     8104                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     8481                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     8313                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     8308                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     5342                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                     3822                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                     2427                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      910                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      567                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      333                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      152                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      100                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                       82                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                       69                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                       58                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                       54                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                       48                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                       47                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                       44                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                       38                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                       37                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                       33                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                       29                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                       28                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                       27                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        41807                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      385.014950                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     230.118388                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     358.708548                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          12628     30.21%     30.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255         8632     20.65%     50.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         4415     10.56%     61.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         2749      6.58%     67.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2263      5.41%     73.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1680      4.02%     77.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1442      3.45%     80.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1629      3.90%     84.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         6369     15.23%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          41807                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          6909                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        23.954842                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      351.043824                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023           6907     99.97%     99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047            1      0.01%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::28672-29695            1      0.01%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            6909                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          6909                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        16.496599                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       16.404036                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        2.150839                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16               6289     91.03%     91.03% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17                 13      0.19%     91.21% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18                 61      0.88%     92.10% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19                166      2.40%     94.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20                127      1.84%     96.34% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21                 73      1.06%     97.39% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22                 63      0.91%     98.31% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23                 29      0.42%     98.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24                 18      0.26%     98.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::25                 12      0.17%     99.16% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26                  7      0.10%     99.26% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::27                  3      0.04%     99.31% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28                  3      0.04%     99.35% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::29                  1      0.01%     99.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::30                  2      0.03%     99.39% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::31                  3      0.04%     99.44% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32                  2      0.03%     99.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::34                  3      0.04%     99.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::35                  2      0.03%     99.54% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::37                  3      0.04%     99.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::38                  2      0.03%     99.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::39                 19      0.28%     99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40                  5      0.07%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::42                  2      0.03%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::43                  1      0.01%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            6909                       # Writes before turning the bus around for reads
system.physmem.totQLat                     5306478250                       # Total ticks spent queuing
system.physmem.totMemAccLat                7800537000                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    827545000                       # Total ticks spent in databus transfers
system.physmem.totBankLat                  1666513750                       # Total ticks spent accessing banks
system.physmem.avgQLat                       32061.57                       # Average queueing delay per DRAM burst
system.physmem.avgBankLat                    10069.02                       # Average bank access latency per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  47130.59                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                         243.74                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                         167.85                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                      243.75                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                      167.88                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           3.22                       # Data bus utilization in percentage
system.physmem.busUtilRead                       1.90                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      1.31                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.45                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        26.84                       # Average write queue length when enqueuing
system.physmem.readRowHits                     144461                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     82889                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   87.28                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  72.71                       # Row buffer hit rate for writes
system.physmem.avgGap                       155480.97                       # Average gap between requests
system.physmem.pageHitRate                      81.34                       # Row buffer hit rate, read and write combined
system.physmem.prechargeAllPercent              10.25                       # Percentage of time for which DRAM has all the banks in precharge state
system.membus.throughput                    411625737                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq               34625                       # Transaction distribution
system.membus.trans_dist::ReadResp              34625                       # Transaction distribution
system.membus.trans_dist::Writeback            113997                       # Transaction distribution
system.membus.trans_dist::ReadExReq            130890                       # Transaction distribution
system.membus.trans_dist::ReadExResp           130890                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       445027                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 445027                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     17888768                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total            17888768                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus               17888768                       # Total data (bytes)
system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy          1219845000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               2.8                       # Layer utilization (%)
system.membus.respLayer1.occupancy         1520840750                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              3.5                       # Layer utilization (%)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.branchPred.lookups                18742760                       # Number of BP lookups
system.cpu.branchPred.condPredicted          12318400                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect           4775680                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             15507492                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                 4664025                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             30.075947                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 1660965                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect               1030                       # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits                           0                       # ITB hits
system.cpu.dtb.fetch_misses                         0                       # ITB misses
system.cpu.dtb.fetch_acv                            0                       # ITB acv
system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
system.cpu.dtb.read_hits                     20277780                       # DTB read hits
system.cpu.dtb.read_misses                      90148                       # DTB read misses
system.cpu.dtb.read_acv                             0                       # DTB read access violations
system.cpu.dtb.read_accesses                 20367928                       # DTB read accesses
system.cpu.dtb.write_hits                    14729056                       # DTB write hits
system.cpu.dtb.write_misses                      7252                       # DTB write misses
system.cpu.dtb.write_acv                            0                       # DTB write access violations
system.cpu.dtb.write_accesses                14736308                       # DTB write accesses
system.cpu.dtb.data_hits                     35006836                       # DTB hits
system.cpu.dtb.data_misses                      97400                       # DTB misses
system.cpu.dtb.data_acv                             0                       # DTB access violations
system.cpu.dtb.data_accesses                 35104236                       # DTB accesses
system.cpu.itb.fetch_hits                    12367757                       # ITB hits
system.cpu.itb.fetch_misses                     11021                       # ITB misses
system.cpu.itb.fetch_acv                            0                       # ITB acv
system.cpu.itb.fetch_accesses                12378778                       # ITB accesses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.read_acv                             0                       # DTB read access violations
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.write_acv                            0                       # DTB write access violations
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.data_hits                            0                       # DTB hits
system.cpu.itb.data_misses                          0                       # DTB misses
system.cpu.itb.data_acv                             0                       # DTB access violations
system.cpu.itb.data_accesses                        0                       # DTB accesses
system.cpu.workload.num_syscalls                 4583                       # Number of system calls
system.cpu.numCycles                         86917637                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.branch_predictor.predictedTaken      8074236                       # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken     10668524                       # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads     74162131                       # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites     52319250                       # Number of Writes to Int. Register File
system.cpu.regfile_manager.intRegFileAccesses    126481381                       # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads        66044                       # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites       227630                       # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses       293674                       # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards       14174243                       # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens                   35060070                       # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect      4449011                       # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect       216169                       # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted        4665180                       # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted           9107422                       # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct     33.872902                       # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions         44777932                       # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies             41107                       # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides                    0                       # Number of Divide Operations Executed
system.cpu.contextSwitches                          1                       # Number of context switches
system.cpu.threadCycles                      77191042                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled                          229429                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                        17341864                       # Number of cycles cpu's stages were not processed
system.cpu.runCycles                         69575773                       # Number of cycles cpu stages are processed.
system.cpu.activity                         80.047934                       # Percentage of cycles cpu is active
system.cpu.comLoads                          20276638                       # Number of Load instructions committed
system.cpu.comStores                         14613377                       # Number of Store instructions committed
system.cpu.comBranches                       13754477                       # Number of Branches instructions committed
system.cpu.comNops                            8748916                       # Number of Nop instructions committed
system.cpu.comNonSpec                            4583                       # Number of Non-Speculative instructions committed
system.cpu.comInts                           30791227                       # Number of Integer instructions committed
system.cpu.comFloats                           151453                       # Number of Floating Point instructions committed
system.cpu.committedInsts                    88340673                       # Number of Instructions committed (Per-Thread)
system.cpu.committedOps                      88340673                       # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total              88340673                       # Number of Instructions committed (Total)
system.cpu.cpi                               0.983891                       # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi                                nan                       # CPI: Total SMT-CPI
system.cpu.cpi_total                         0.983891                       # CPI: Total CPI of All Threads
system.cpu.ipc                               1.016372                       # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc                                nan                       # IPC: Total SMT-IPC
system.cpu.ipc_total                         1.016372                       # IPC: Total IPC of All Threads
system.cpu.stage0.idleCycles                 34262012                       # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles                  52655625                       # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization               60.581059                       # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles                 44462439                       # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles                  42455198                       # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization               48.845320                       # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles                 43887105                       # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles                  43030532                       # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization               49.507250                       # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles                 64797015                       # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles                  22120622                       # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization               25.450096                       # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles                 40875399                       # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles                  46042238                       # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization               52.972262                       # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.tags.replacements             84371                       # number of replacements
system.cpu.icache.tags.tagsinuse          1905.831723                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs            12250503                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs             86417                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs            141.760337                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst  1905.831723                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.930582                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.930582                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024         2046                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           62                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          104                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3         1090                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4          790                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.999023                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses          24821911                       # Number of tag accesses
system.cpu.icache.tags.data_accesses         24821911                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst     12250503                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        12250503                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      12250503                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         12250503                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     12250503                       # number of overall hits
system.cpu.icache.overall_hits::total        12250503                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst       117244                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total        117244                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst       117244                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total         117244                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst       117244                       # number of overall misses
system.cpu.icache.overall_misses::total        117244                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst   1999895234                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total   1999895234                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst   1999895234                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total   1999895234                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst   1999895234                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total   1999895234                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     12367747                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     12367747                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     12367747                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     12367747                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     12367747                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     12367747                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.009480                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.009480                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.009480                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.009480                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.009480                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.009480                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17057.548651                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 17057.548651                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 17057.548651                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 17057.548651                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 17057.548651                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 17057.548651                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs          343                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets          192                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                15                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               4                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    22.866667                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets           48                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst        30827                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total        30827                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst        30827                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total        30827                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst        30827                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total        30827                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst        86417                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total        86417                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst        86417                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total        86417                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst        86417                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total        86417                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   1419611513                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total   1419611513                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst   1419611513                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total   1419611513                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst   1419611513                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total   1419611513                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.006987                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.006987                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.006987                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.006987                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.006987                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.006987                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16427.456554                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16427.456554                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16427.456554                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 16427.456554                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16427.456554                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 16427.456554                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.throughput               676121104                       # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq         146995                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp        146995                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback       168352                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       143769                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       143769                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       172834                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       577046                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total            749880                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      5530688                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     23852736                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total       29383424                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus          29383424                       # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy      397910000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.9                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy     130829487                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.3                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy     323146469                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.7                       # Layer utilization (%)
system.cpu.l2cache.tags.replacements           131591                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        30877.243576                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs             151434                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           163651                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             0.925347                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 27092.654478                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  2007.905024                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data  1776.684074                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.826802                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.061276                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.054220                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.942299                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        32060                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0          145                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1         1156                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2        17173                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3        13478                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4          108                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.978394                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses          3980348                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses         3980348                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst        79314                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data        33056                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total         112370                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks       168352                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total       168352                       # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data        12879                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total        12879                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst        79314                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data        45935                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total          125249                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst        79314                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data        45935                       # number of overall hits
system.cpu.l2cache.overall_hits::total         125249                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst         7103                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data        27522                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total        34625                       # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       130890                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       130890                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst         7103                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       158412                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        165515                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         7103                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       158412                       # number of overall misses
system.cpu.l2cache.overall_misses::total       165515                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    537407000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data   1972226500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   2509633500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  12899781250                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  12899781250                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    537407000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  14872007750                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  15409414750                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    537407000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  14872007750                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  15409414750                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst        86417                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data        60578                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total       146995                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks       168352                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total       168352                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       143769                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       143769                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst        86417                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data       204347                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total       290764                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst        86417                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data       204347                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total       290764                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.082194                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.454323                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.235552                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.910419                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.910419                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.082194                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.775211                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.569242                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.082194                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.775211                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.569242                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75659.158102                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71659.999273                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 72480.389892                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 98554.368172                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 98554.368172                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75659.158102                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93881.825556                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 93099.808174                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75659.158102                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93881.825556                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 93099.808174                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks       113997                       # number of writebacks
system.cpu.l2cache.writebacks::total           113997                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         7103                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        27522                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total        34625                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       130890                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       130890                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         7103                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       158412                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       165515                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         7103                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       158412                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       165515                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    448296500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1624855000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   2073151500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  11301062250                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  11301062250                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    448296500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  12925917250                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  13374213750                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    448296500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  12925917250                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  13374213750                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.082194                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.454323                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.235552                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.910419                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.910419                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.082194                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.775211                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.569242                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.082194                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.775211                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.569242                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63113.684359                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59038.405639                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59874.411552                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86340.150126                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86340.150126                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63113.684359                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 81596.831364                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 80803.635622                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63113.684359                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 81596.831364                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 80803.635622                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements            200251                       # number of replacements
system.cpu.dcache.tags.tagsinuse          4076.081511                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            33755026                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs            204347                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs            165.184838                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle         302612000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data  4076.081511                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.995137                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.995137                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           66                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          922                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2         3108                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses          69984377                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses         69984377                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data     20180293                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        20180293                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     13574733                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       13574733                       # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data      33755026                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         33755026                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     33755026                       # number of overall hits
system.cpu.dcache.overall_hits::total        33755026                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data        96345                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total         96345                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      1038644                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      1038644                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data      1134989                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        1134989                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      1134989                       # number of overall misses
system.cpu.dcache.overall_misses::total       1134989                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data   4945314984                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total   4945314984                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  82211352380                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  82211352380                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  87156667364                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  87156667364                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  87156667364                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  87156667364                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     20276638                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     20276638                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     14613377                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     14613377                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     34890015                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     34890015                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     34890015                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     34890015                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.004752                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.004752                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.071075                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.071075                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.032530                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.032530                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.032530                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.032530                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51329.233318                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 51329.233318                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 79152.580076                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 79152.580076                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 76790.759526                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 76790.759526                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 76790.759526                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 76790.759526                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs      5467849                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets           77                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs            116872                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               1                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    46.784936                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets           77                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       168352                       # number of writebacks
system.cpu.dcache.writebacks::total            168352                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data        35578                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total        35578                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data       895064                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total       895064                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data       930642                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total       930642                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data       930642                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total       930642                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data        60767                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total        60767                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       143580                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       143580                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data       204347                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total       204347                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data       204347                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total       204347                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   2366861266                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total   2366861266                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  13170287765                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  13170287765                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  15537149031                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  15537149031                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  15537149031                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  15537149031                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002997                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002997                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.009825                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.009825                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.005857                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.005857                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.005857                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.005857                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 38949.779749                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 38949.779749                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 91727.871326                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 91727.871326                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76033.164328                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 76033.164328                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76033.164328                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 76033.164328                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------