blob: 22fcb32bda1a014afd84620b1b78d8faa1999cd3 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
|
---------- Begin Simulation Statistics ----------
sim_seconds 0.046914 # Number of seconds simulated
sim_ticks 46914279500 # Number of ticks simulated
final_tick 46914279500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 145791 # Simulator instruction rate (inst/s)
host_op_rate 145791 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 77424105 # Simulator tick rate (ticks/s)
host_mem_usage 218104 # Number of bytes of host memory used
host_seconds 605.94 # Real time elapsed on the host
sim_insts 88340673 # Number of instructions simulated
sim_ops 88340673 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 11164096 # Number of bytes read from this memory
system.physmem.bytes_inst_read 599296 # Number of instructions bytes read from this memory
system.physmem.bytes_written 7712960 # Number of bytes written to this memory
system.physmem.num_reads 174439 # Number of read requests responded to by this memory
system.physmem.num_writes 120515 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
system.physmem.bw_read 237967973 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 12774277 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write 164405381 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total 402373354 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 20277222 # DTB read hits
system.cpu.dtb.read_misses 90148 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 20367370 # DTB read accesses
system.cpu.dtb.write_hits 14736811 # DTB write hits
system.cpu.dtb.write_misses 7252 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 14744063 # DTB write accesses
system.cpu.dtb.data_hits 35014033 # DTB hits
system.cpu.dtb.data_misses 97400 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 35111433 # DTB accesses
system.cpu.itb.fetch_hits 12380499 # ITB hits
system.cpu.itb.fetch_misses 10576 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 12391075 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4583 # Number of system calls
system.cpu.numCycles 93828560 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.contextSwitches 1 # Number of context switches
system.cpu.threadCycles 77431415 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled 305691 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 24228941 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 69599619 # Number of cycles cpu stages are processed.
system.cpu.activity 74.177435 # Percentage of cycles cpu is active
system.cpu.comLoads 20276638 # Number of Load instructions committed
system.cpu.comStores 14613377 # Number of Store instructions committed
system.cpu.comBranches 13754477 # Number of Branches instructions committed
system.cpu.comNops 8748916 # Number of Nop instructions committed
system.cpu.comNonSpec 4583 # Number of Non-Speculative instructions committed
system.cpu.comInts 30791227 # Number of Integer instructions committed
system.cpu.comFloats 151453 # Number of Floating Point instructions committed
system.cpu.committedInsts 88340673 # Number of Instructions committed (Per-Thread)
system.cpu.committedOps 88340673 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 88340673 # Number of Instructions committed (Total)
system.cpu.cpi 1.062122 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi no_value # CPI: Total SMT-CPI
system.cpu.cpi_total 1.062122 # CPI: Total CPI of All Threads
system.cpu.ipc 0.941512 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc no_value # IPC: Total SMT-IPC
system.cpu.ipc_total 0.941512 # IPC: Total IPC of All Threads
system.cpu.branch_predictor.lookups 18761151 # Number of BP lookups
system.cpu.branch_predictor.condPredicted 12342012 # Number of conditional branches predicted
system.cpu.branch_predictor.condIncorrect 4785453 # Number of conditional branches incorrect
system.cpu.branch_predictor.BTBLookups 15763185 # Number of BTB lookups
system.cpu.branch_predictor.BTBHits 4708455 # Number of BTB hits
system.cpu.branch_predictor.usedRAS 1660959 # Number of times the RAS was used to get a target.
system.cpu.branch_predictor.RASInCorrect 1029 # Number of incorrect RAS predictions.
system.cpu.branch_predictor.BTBHitPct 29.869947 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 8112975 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 10648176 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 74148043 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 52319250 # Number of Writes to Int. Register File
system.cpu.regfile_manager.intRegFileAccesses 126467293 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 65874 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 227630 # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses 293504 # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards 14179622 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 35053135 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 4496417 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 178536 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted 4674953 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted 9097544 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct 33.944121 # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions 44764178 # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies 41107 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.stage0.idleCycles 41142190 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 52686370 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 56.151741 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 51376338 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 42452222 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 45.244456 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 50789796 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 43038764 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 45.869577 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 71702339 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 22126221 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 23.581542 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 47784207 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 46044353 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 49.072855 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 83610 # number of replacements
system.cpu.icache.tagsinuse 1886.858130 # Cycle average of tags in use
system.cpu.icache.total_refs 12263478 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 85656 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 143.171266 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 1886.858130 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.921317 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.921317 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 12263478 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 12263478 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 12263478 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 12263478 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 12263478 # number of overall hits
system.cpu.icache.overall_hits::total 12263478 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 116984 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 116984 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 116984 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 116984 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 116984 # number of overall misses
system.cpu.icache.overall_misses::total 116984 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 2068004000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 2068004000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 2068004000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 2068004000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 2068004000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 2068004000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 12380462 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 12380462 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 12380462 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 12380462 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 12380462 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 12380462 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.009449 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.009449 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.009449 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17677.665322 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 17677.665322 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 17677.665322 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 1596000 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 172 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 9279.069767 # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 31328 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 31328 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 31328 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 31328 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 31328 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 31328 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 85656 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 85656 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 85656 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 85656 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 85656 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 85656 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1345401500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 1345401500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1345401500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 1345401500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1345401500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 1345401500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006919 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006919 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006919 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15707.031615 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15707.031615 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15707.031615 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 200251 # number of replacements
system.cpu.dcache.tagsinuse 4073.105766 # Cycle average of tags in use
system.cpu.dcache.total_refs 34126014 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 204347 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 167.000318 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 486265000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4073.105766 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.994411 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.994411 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 20180445 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 20180445 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 13945569 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 13945569 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 34126014 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 34126014 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 34126014 # number of overall hits
system.cpu.dcache.overall_hits::total 34126014 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 96193 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 96193 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 667808 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 667808 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 764001 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 764001 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 764001 # number of overall misses
system.cpu.dcache.overall_misses::total 764001 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 4158649000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 4158649000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 35332073000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 35332073000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 39490722000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 39490722000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 39490722000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 39490722000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 34890015 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 34890015 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 34890015 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004744 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045698 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.021897 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.021897 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 43232.345389 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52907.531806 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 51689.359045 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 51689.359045 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 6330522500 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 124112 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 51006.530392 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 161216 # number of writebacks
system.cpu.dcache.writebacks::total 161216 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35426 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 35426 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 524228 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 524228 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 559654 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 559654 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 559654 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 559654 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60767 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 60767 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143580 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 143580 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 204347 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 204347 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 204347 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 204347 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2088724500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2088724500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7254420000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 7254420000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9343144500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 9343144500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9343144500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 9343144500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34372.677605 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50525.282073 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45721.955791 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45721.955791 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 148060 # number of replacements
system.cpu.l2cache.tagsinuse 18663.556927 # Cycle average of tags in use
system.cpu.l2cache.total_refs 131331 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 173405 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.757366 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 15657.764606 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 1362.413436 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 1643.378886 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.477837 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.041578 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.050152 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.569567 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 76292 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 27002 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 103294 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 161216 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 161216 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 12270 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 12270 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 76292 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 39272 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 115564 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 76292 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 39272 # number of overall hits
system.cpu.l2cache.overall_hits::total 115564 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 9364 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 33575 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 42939 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 131500 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 131500 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 9364 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 165075 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 174439 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 9364 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 165075 # number of overall misses
system.cpu.l2cache.overall_misses::total 174439 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 489614500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1752692000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 2242306500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6854385000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 6854385000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 489614500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 8607077000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 9096691500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 489614500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 8607077000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 9096691500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 85656 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 60577 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 146233 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 161216 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 161216 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 143770 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 143770 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 85656 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 204347 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 290003 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 85656 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 204347 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 290003 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.109321 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.554253 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.914655 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.109321 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.807817 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.109321 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.807817 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52286.896625 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52202.293373 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52124.600760 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52286.896625 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52140.402847 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52286.896625 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52140.402847 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 120515 # number of writebacks
system.cpu.l2cache.writebacks::total 120515 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 9364 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 33575 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 42939 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 131500 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 131500 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 9364 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 165075 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 174439 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 9364 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 165075 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 174439 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 375279000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1343349500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1718628500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5262711000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5262711000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 375279000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6606060500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 6981339500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 375279000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6606060500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 6981339500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.109321 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.554253 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.914655 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.109321 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.807817 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.109321 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.807817 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40076.783426 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40010.409531 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40020.615970 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40076.783426 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40018.540058 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40076.783426 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40018.540058 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
|
