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|
---------- Begin Simulation Statistics ----------
sim_seconds 0.042726 # Number of seconds simulated
sim_ticks 42725646500 # Number of ticks simulated
final_tick 42725646500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 44211 # Simulator instruction rate (inst/s)
host_op_rate 44211 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 21382391 # Simulator tick rate (ticks/s)
host_mem_usage 280712 # Number of bytes of host memory used
host_seconds 1998.17 # Real time elapsed on the host
sim_insts 88340673 # Number of instructions simulated
sim_ops 88340673 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 454528 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 10138368 # Number of bytes read from this memory
system.physmem.bytes_read::total 10592896 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 454528 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 454528 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 7295808 # Number of bytes written to this memory
system.physmem.bytes_written::total 7295808 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 7102 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 158412 # Number of read requests responded to by this memory
system.physmem.num_reads::total 165514 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 113997 # Number of write requests responded to by this memory
system.physmem.num_writes::total 113997 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 10638294 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 237289985 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 247928279 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 10638294 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 10638294 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 170759452 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 170759452 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 170759452 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 10638294 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 237289985 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 418687731 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 165514 # Total number of read requests seen
system.physmem.writeReqs 113997 # Total number of write requests seen
system.physmem.cpureqs 279511 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 10592896 # Total number of bytes read from memory
system.physmem.bytesWritten 7295808 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 10592896 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 7295808 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 10572 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 10465 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 10270 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 10169 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 10534 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 10768 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 10384 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 10283 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 10421 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 10442 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 10202 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 9934 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 10515 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 10344 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 10131 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 10080 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 7377 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 7241 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 6946 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 6832 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 7241 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 7386 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 7023 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 7006 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 7262 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 7155 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 7040 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 6934 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 7274 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 7250 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 7038 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 6992 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
system.physmem.totGap 42725626000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 165514 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 113997 # Categorize write packet sizes
system.physmem.rdQLenPdf::0 62488 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 76381 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 18709 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 7928 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 2107 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 3879 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 4869 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 4907 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 4940 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 4955 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 4957 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 4957 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 4957 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 4956 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 4956 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 4956 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 4956 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 4956 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 4956 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 4956 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 4956 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 4956 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 4956 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 4956 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 4956 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 4956 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 4956 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 2850 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 1078 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 88 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 50 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 17 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 2 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.totQLat 7078163250 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 9669555750 # Sum of mem lat for all requests
system.physmem.totBusLat 827570000 # Total cycles spent in databus access
system.physmem.totBankLat 1763822500 # Total cycles spent in bank access
system.physmem.avgQLat 42764.74 # Average queueing delay per request
system.physmem.avgBankLat 10656.64 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
system.physmem.avgMemAccLat 58421.38 # Average memory access latency
system.physmem.avgRdBW 247.93 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 170.76 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 247.93 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 170.76 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 3.27 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.23 # Average read queue length over time
system.physmem.avgWrQLen 10.41 # Average write queue length over time
system.physmem.readRowHits 148885 # Number of row buffer hits during reads
system.physmem.writeRowHits 71702 # Number of row buffer hits during writes
system.physmem.readRowHitRate 89.95 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 62.90 # Row buffer hit rate for writes
system.physmem.avgGap 152858.48 # Average gap between requests
system.cpu.branchPred.lookups 18741806 # Number of BP lookups
system.cpu.branchPred.condPredicted 12317440 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 4774691 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 15571063 # Number of BTB lookups
system.cpu.branchPred.BTBHits 4663219 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 29.947981 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 1660960 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 1030 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 20277542 # DTB read hits
system.cpu.dtb.read_misses 90148 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 20367690 # DTB read accesses
system.cpu.dtb.write_hits 14728781 # DTB write hits
system.cpu.dtb.write_misses 7252 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 14736033 # DTB write accesses
system.cpu.dtb.data_hits 35006323 # DTB hits
system.cpu.dtb.data_misses 97400 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 35103723 # DTB accesses
system.cpu.itb.fetch_hits 12368482 # ITB hits
system.cpu.itb.fetch_misses 10998 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 12379480 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4583 # Number of system calls
system.cpu.numCycles 85451294 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.branch_predictor.predictedTaken 8073687 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 10668119 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 74170009 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 52319250 # Number of Writes to Int. Register File
system.cpu.regfile_manager.intRegFileAccesses 126489259 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 66071 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 227630 # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses 293701 # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards 14164942 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 35060353 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 4447581 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 216610 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted 4664191 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted 9108383 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct 33.865790 # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions 44777788 # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies 41107 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches
system.cpu.threadCycles 77182336 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled 229187 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 15880194 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 69571100 # Number of cycles cpu stages are processed.
system.cpu.activity 81.416087 # Percentage of cycles cpu is active
system.cpu.comLoads 20276638 # Number of Load instructions committed
system.cpu.comStores 14613377 # Number of Store instructions committed
system.cpu.comBranches 13754477 # Number of Branches instructions committed
system.cpu.comNops 8748916 # Number of Nop instructions committed
system.cpu.comNonSpec 4583 # Number of Non-Speculative instructions committed
system.cpu.comInts 30791227 # Number of Integer instructions committed
system.cpu.comFloats 151453 # Number of Floating Point instructions committed
system.cpu.committedInsts 88340673 # Number of Instructions committed (Per-Thread)
system.cpu.committedOps 88340673 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 88340673 # Number of Instructions committed (Total)
system.cpu.cpi 0.967293 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
system.cpu.cpi_total 0.967293 # CPI: Total CPI of All Threads
system.cpu.ipc 1.033813 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
system.cpu.ipc_total 1.033813 # IPC: Total IPC of All Threads
system.cpu.stage0.idleCycles 32800214 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 52651080 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 61.615310 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 42999576 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 42451718 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 49.679433 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 42421796 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 43029498 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 50.355584 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 63338785 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 22112509 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 25.877325 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 39402182 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 46049112 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 53.889309 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 84283 # number of replacements
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system.cpu.icache.total_refs 12251335 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 86329 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 141.914478 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 1908.281182 # Average occupied blocks per requestor
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system.cpu.icache.occ_percent::total 0.931778 # Average percentage of cache occupancy
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system.cpu.icache.ReadReq_hits::total 12251335 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 12251335 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 12251335 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 12251335 # number of overall hits
system.cpu.icache.overall_hits::total 12251335 # number of overall hits
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system.cpu.icache.ReadReq_misses::total 117137 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 117137 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 117137 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 117137 # number of overall misses
system.cpu.icache.overall_misses::total 117137 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 1898913500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 1898913500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 1898913500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 1898913500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 1898913500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 1898913500 # number of overall miss cycles
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system.cpu.icache.ReadReq_accesses::total 12368472 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 12368472 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 12368472 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 12368472 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 12368472 # number of overall (read+write) accesses
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system.cpu.icache.ReadReq_miss_rate::total 0.009471 # miss rate for ReadReq accesses
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system.cpu.icache.demand_miss_rate::total 0.009471 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.009471 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.009471 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16211.047748 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 16211.047748 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 16211.047748 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 16211.047748 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 16211.047748 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 16211.047748 # average overall miss latency
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system.cpu.icache.blocked::no_mshrs 16 # number of cycles access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets 7 # average number of cycles each access was blocked
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system.cpu.icache.demand_mshr_hits::total 30808 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 30808 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 30808 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 86329 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 86329 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 86329 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 86329 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 86329 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 86329 # number of overall MSHR misses
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system.cpu.icache.ReadReq_mshr_miss_latency::total 1336106500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1336106500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 1336106500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1336106500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 1336106500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006980 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006980 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006980 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.006980 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006980 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.006980 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15476.913899 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15476.913899 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15476.913899 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 15476.913899 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15476.913899 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 15476.913899 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 131591 # number of replacements
system.cpu.l2cache.tagsinuse 30966.087647 # Cycle average of tags in use
system.cpu.l2cache.total_refs 151345 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 163649 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.924815 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 27282.334509 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 2017.545117 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 1666.208021 # Average occupied blocks per requestor
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system.cpu.l2cache.ReadReq_hits::total 112282 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 168351 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 168351 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 12879 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 12879 # number of ReadExReq hits
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system.cpu.l2cache.Writeback_accesses::writebacks 168351 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 168351 # number of Writeback accesses(hits+misses)
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system.cpu.l2cache.writebacks::writebacks 113997 # number of writebacks
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system.cpu.dcache.WriteReq_miss_latency::cpu.data 76774000000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 76774000000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 80643387500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 80643387500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 80643387500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 80643387500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 34890015 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 34890015 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 34890015 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004754 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.004754 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071083 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.071083 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.032536 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.032536 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.032536 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.032536 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40139.707255 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 40139.707255 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73908.778388 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 73908.778388 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 71041.115168 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 71041.115168 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 71041.115168 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 71041.115168 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 5035459 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 519 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 116380 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 43.267391 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 519 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 168351 # number of writebacks
system.cpu.dcache.writebacks::total 168351 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35632 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 35632 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895187 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 895187 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 930819 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 930819 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 930819 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 930819 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60766 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 60766 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143580 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 143580 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 204346 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 204346 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 204346 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 204346 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1910017000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 1910017000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12290144000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 12290144000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14200161000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 14200161000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14200161000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 14200161000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009825 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31432.330580 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31432.330580 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 85597.882713 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 85597.882713 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 69490.770556 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 69490.770556 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 69490.770556 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 69490.770556 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
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