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|
---------- Begin Simulation Statistics ----------
sim_seconds 0.058331 # Number of seconds simulated
sim_ticks 58330740000 # Number of ticks simulated
final_tick 58330740000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 186275 # Simulator instruction rate (inst/s)
host_op_rate 186275 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 122860334 # Simulator tick rate (ticks/s)
host_mem_usage 249156 # Number of bytes of host memory used
host_seconds 474.77 # Real time elapsed on the host
sim_insts 88438073 # Number of instructions simulated
sim_ops 88438073 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 10662976 # Number of bytes read from this memory
system.physmem.bytes_read::total 10662976 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 515264 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 515264 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 7299200 # Number of bytes written to this memory
system.physmem.bytes_written::total 7299200 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 166609 # Number of read requests responded to by this memory
system.physmem.num_reads::total 166609 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 114050 # Number of write requests responded to by this memory
system.physmem.num_writes::total 114050 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 182802001 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 182802001 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 8833490 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 8833490 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 125134706 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 125134706 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 125134706 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 182802001 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 307936707 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 166609 # Number of read requests accepted
system.physmem.writeReqs 114050 # Number of write requests accepted
system.physmem.readBursts 166609 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 114050 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 10662464 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 512 # Total number of bytes read from write queue
system.physmem.bytesWritten 7297728 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 10662976 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 7299200 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 8 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 10471 # Per bank write bursts
system.physmem.perBankRdBursts::1 10513 # Per bank write bursts
system.physmem.perBankRdBursts::2 10311 # Per bank write bursts
system.physmem.perBankRdBursts::3 10091 # Per bank write bursts
system.physmem.perBankRdBursts::4 10430 # Per bank write bursts
system.physmem.perBankRdBursts::5 10425 # Per bank write bursts
system.physmem.perBankRdBursts::6 9845 # Per bank write bursts
system.physmem.perBankRdBursts::7 10301 # Per bank write bursts
system.physmem.perBankRdBursts::8 10592 # Per bank write bursts
system.physmem.perBankRdBursts::9 10642 # Per bank write bursts
system.physmem.perBankRdBursts::10 10594 # Per bank write bursts
system.physmem.perBankRdBursts::11 10255 # Per bank write bursts
system.physmem.perBankRdBursts::12 10302 # Per bank write bursts
system.physmem.perBankRdBursts::13 10654 # Per bank write bursts
system.physmem.perBankRdBursts::14 10528 # Per bank write bursts
system.physmem.perBankRdBursts::15 10647 # Per bank write bursts
system.physmem.perBankWrBursts::0 7087 # Per bank write bursts
system.physmem.perBankWrBursts::1 7261 # Per bank write bursts
system.physmem.perBankWrBursts::2 7256 # Per bank write bursts
system.physmem.perBankWrBursts::3 6999 # Per bank write bursts
system.physmem.perBankWrBursts::4 7126 # Per bank write bursts
system.physmem.perBankWrBursts::5 7177 # Per bank write bursts
system.physmem.perBankWrBursts::6 6771 # Per bank write bursts
system.physmem.perBankWrBursts::7 7089 # Per bank write bursts
system.physmem.perBankWrBursts::8 7224 # Per bank write bursts
system.physmem.perBankWrBursts::9 6941 # Per bank write bursts
system.physmem.perBankWrBursts::10 7095 # Per bank write bursts
system.physmem.perBankWrBursts::11 6991 # Per bank write bursts
system.physmem.perBankWrBursts::12 6965 # Per bank write bursts
system.physmem.perBankWrBursts::13 7289 # Per bank write bursts
system.physmem.perBankWrBursts::14 7284 # Per bank write bursts
system.physmem.perBankWrBursts::15 7472 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 58330713500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 166609 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 114050 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 164962 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 1611 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 28 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 736 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 758 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 6203 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 6988 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 7033 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 7035 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 7030 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 7041 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 7036 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 7062 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 7079 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 7087 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 7241 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 7129 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 7115 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 7354 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 7080 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 7023 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 5 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 54540 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 329.285515 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 195.168705 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 332.681094 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 19405 35.58% 35.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 11848 21.72% 57.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 5629 10.32% 67.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 3624 6.64% 74.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 2728 5.00% 79.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 2044 3.75% 83.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 1598 2.93% 85.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 1491 2.73% 88.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 6173 11.32% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 54540 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 7020 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 23.731339 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 347.912038 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023 7019 99.99% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::28672-29695 1 0.01% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 7020 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 7020 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 16.243162 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 16.227940 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 0.737137 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16 6260 89.17% 89.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17 15 0.21% 89.39% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18 596 8.49% 97.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19 118 1.68% 99.56% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20 21 0.30% 99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21 7 0.10% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22 1 0.01% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26 1 0.01% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::27 1 0.01% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 7020 # Writes before turning the bus around for reads
system.physmem.totQLat 1961331500 # Total ticks spent queuing
system.physmem.totMemAccLat 5085100250 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 833005000 # Total ticks spent in databus transfers
system.physmem.avgQLat 11772.63 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 30522.63 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 182.79 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 125.11 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 182.80 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 125.13 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 2.41 # Data bus utilization in percentage
system.physmem.busUtilRead 1.43 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.98 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing
system.physmem.avgWrQLen 23.77 # Average write queue length when enqueuing
system.physmem.readRowHits 144790 # Number of row buffer hits during reads
system.physmem.writeRowHits 81289 # Number of row buffer hits during writes
system.physmem.readRowHitRate 86.91 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 71.27 # Row buffer hit rate for writes
system.physmem.avgGap 207834.82 # Average gap between requests
system.physmem.pageHitRate 80.56 # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE 31870385750 # Time in different power states
system.physmem.memoryStateTime::REF 1947660000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem.memoryStateTime::ACT 24509026750 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
system.membus.throughput 307936707 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 35729 # Transaction distribution
system.membus.trans_dist::ReadResp 35729 # Transaction distribution
system.membus.trans_dist::Writeback 114050 # Transaction distribution
system.membus.trans_dist::ReadExReq 130880 # Transaction distribution
system.membus.trans_dist::ReadExResp 130880 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 447268 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 447268 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17962176 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 17962176 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 17962176 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 1302300000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 2.2 # Layer utilization (%)
system.membus.respLayer1.occupancy 1600619750 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 2.7 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.branchPred.lookups 14594378 # Number of BP lookups
system.cpu.branchPred.condPredicted 9449120 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 378858 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 10404778 # Number of BTB lookups
system.cpu.branchPred.BTBHits 6369492 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 61.216991 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 1700724 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 73182 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 20554057 # DTB read hits
system.cpu.dtb.read_misses 96859 # DTB read misses
system.cpu.dtb.read_acv 9 # DTB read access violations
system.cpu.dtb.read_accesses 20650916 # DTB read accesses
system.cpu.dtb.write_hits 14665861 # DTB write hits
system.cpu.dtb.write_misses 9387 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 14675248 # DTB write accesses
system.cpu.dtb.data_hits 35219918 # DTB hits
system.cpu.dtb.data_misses 106246 # DTB misses
system.cpu.dtb.data_acv 9 # DTB access violations
system.cpu.dtb.data_accesses 35326164 # DTB accesses
system.cpu.itb.fetch_hits 25539378 # ITB hits
system.cpu.itb.fetch_misses 5182 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 25544560 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4583 # Number of system calls
system.cpu.numCycles 116661480 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 88438073 # Number of instructions committed
system.cpu.committedOps 88438073 # Number of ops (including micro ops) committed
system.cpu.discardedOps 1184669 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 1.319132 # CPI: cycles per instruction
system.cpu.ipc 0.758074 # IPC: instructions per cycle
system.cpu.tickCycles 90786920 # Number of cycles that the object actually ticked
system.cpu.idleCycles 25874560 # Total number of cycles that the object has spent stopped
system.cpu.icache.tags.replacements 152636 # number of replacements
system.cpu.icache.tags.tagsinuse 1933.709390 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 25384693 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 154684 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 164.106779 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 41485931250 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 1933.709390 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.944194 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.944194 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 155 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 1042 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 799 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 51233440 # Number of tag accesses
system.cpu.icache.tags.data_accesses 51233440 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 25384693 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 25384693 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 25384693 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 25384693 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 25384693 # number of overall hits
system.cpu.icache.overall_hits::total 25384693 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 154685 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 154685 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 154685 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 154685 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 154685 # number of overall misses
system.cpu.icache.overall_misses::total 154685 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 2511936746 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 2511936746 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 2511936746 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 2511936746 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 2511936746 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 2511936746 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 25539378 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 25539378 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 25539378 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 25539378 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 25539378 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 25539378 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.006057 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.006057 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.006057 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.006057 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.006057 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.006057 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16239.045454 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 16239.045454 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 16239.045454 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 16239.045454 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 16239.045454 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 16239.045454 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 154685 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 154685 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 154685 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 154685 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 154685 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 154685 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2199492254 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 2199492254 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2199492254 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 2199492254 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2199492254 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 2199492254 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006057 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006057 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006057 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.006057 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006057 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.006057 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14219.169629 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14219.169629 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14219.169629 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 14219.169629 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14219.169629 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 14219.169629 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.throughput 579413736 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 215991 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 215990 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 168535 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 143563 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 143563 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 309369 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 578273 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 887642 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9899776 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23897856 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total 33797632 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus 33797632 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 432579500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 233564246 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.4 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 343185250 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%)
system.cpu.l2cache.tags.replacements 132686 # number of replacements
system.cpu.l2cache.tags.tagsinuse 30472.865320 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 219503 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 164761 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 1.332251 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 26247.009665 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 4225.855654 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.800995 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.128963 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.929958 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32075 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1028 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 11972 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 18837 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 113 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978851 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 4533036 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 4533036 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst 180261 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 180261 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 168535 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 168535 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.inst 12683 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 12683 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 192944 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 192944 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 192944 # number of overall hits
system.cpu.l2cache.overall_hits::total 192944 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 35730 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 35730 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.inst 130880 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 130880 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 166610 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 166610 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 166610 # number of overall misses
system.cpu.l2cache.overall_misses::total 166610 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 2607479500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 2607479500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 9666800250 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 9666800250 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 12274279750 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 12274279750 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 12274279750 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 12274279750 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 215991 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 215991 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 168535 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 168535 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.inst 143563 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 143563 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 359554 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 359554 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 359554 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 359554 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.165424 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.165424 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.911656 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.911656 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.463380 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.463380 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.463380 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.463380 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72977.315981 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 72977.315981 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 73860.026360 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73860.026360 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73670.726547 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 73670.726547 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73670.726547 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 73670.726547 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 114050 # number of writebacks
system.cpu.l2cache.writebacks::total 114050 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 35730 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 35730 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 130880 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 130880 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 166610 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 166610 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 166610 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 166610 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 2154391500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2154391500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 7982023250 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7982023250 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10136414750 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 10136414750 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10136414750 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 10136414750 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.165424 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.165424 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.911656 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911656 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.463380 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.463380 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.463380 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.463380 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60296.431570 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60296.431570 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 60987.341458 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60987.341458 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60839.173819 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60839.173819 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60839.173819 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60839.173819 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements 200773 # number of replacements
system.cpu.dcache.tags.tagsinuse 4071.422788 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 34597432 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 204869 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 168.875877 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 644670250 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.inst 4071.422788 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.inst 0.994000 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.994000 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 752 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 3292 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 70138775 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 70138775 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.inst 20264167 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 20264167 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.inst 14333265 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 14333265 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.inst 34597432 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 34597432 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.inst 34597432 # number of overall hits
system.cpu.dcache.overall_hits::total 34597432 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.inst 89409 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 89409 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.inst 280112 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 280112 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.inst 369521 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 369521 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.inst 369521 # number of overall misses
system.cpu.dcache.overall_misses::total 369521 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.inst 4415904250 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 4415904250 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.inst 20008402750 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 20008402750 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.inst 24424307000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 24424307000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.inst 24424307000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 24424307000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.inst 20353576 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 20353576 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.inst 14613377 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.inst 34966953 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 34966953 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.inst 34966953 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 34966953 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.004393 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.004393 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.019168 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.019168 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.inst 0.010568 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.010568 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.inst 0.010568 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.010568 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 49389.929985 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 49389.929985 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 71430.009246 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 71430.009246 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66097.209631 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 66097.209631 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66097.209631 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 66097.209631 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 168535 # number of writebacks
system.cpu.dcache.writebacks::total 168535 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 28102 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 28102 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 136550 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 136550 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.inst 164652 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 164652 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.inst 164652 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 164652 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 61307 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 61307 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 143562 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 143562 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.inst 204869 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 204869 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.inst 204869 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 204869 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 2427134250 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2427134250 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 9937233500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 9937233500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 12364367750 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 12364367750 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 12364367750 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 12364367750 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.003012 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003012 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.009824 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009824 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.005859 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.005859 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.005859 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.005859 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 39589.838844 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39589.838844 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 69219.107424 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69219.107424 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 60352.555780 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 60352.555780 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 60352.555780 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 60352.555780 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
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