blob: 58628a22b586cee5db6a7958722dddafd50622c8 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
|
---------- Begin Simulation Statistics ----------
sim_seconds 0.060094 # Number of seconds simulated
sim_ticks 60093931000 # Number of ticks simulated
final_tick 60093931000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 276952 # Simulator instruction rate (inst/s)
host_op_rate 276952 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 188189933 # Simulator tick rate (ticks/s)
host_mem_usage 264524 # Number of bytes of host memory used
host_seconds 319.33 # Real time elapsed on the host
sim_insts 88438073 # Number of instructions simulated
sim_ops 88438073 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 60093931000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 438272 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 10168832 # Number of bytes read from this memory
system.physmem.bytes_read::total 10607104 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 438272 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 438272 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 7376000 # Number of bytes written to this memory
system.physmem.bytes_written::total 7376000 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 6848 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 158888 # Number of read requests responded to by this memory
system.physmem.num_reads::total 165736 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 115250 # Number of write requests responded to by this memory
system.physmem.num_writes::total 115250 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 7293116 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 169215623 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 176508739 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7293116 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7293116 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 122741180 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 122741180 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 122741180 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7293116 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 169215623 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 299249919 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 165736 # Number of read requests accepted
system.physmem.writeReqs 115250 # Number of write requests accepted
system.physmem.readBursts 165736 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 115250 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 10606464 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 640 # Total number of bytes read from write queue
system.physmem.bytesWritten 7374720 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 10607104 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 7376000 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 10 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 10345 # Per bank write bursts
system.physmem.perBankRdBursts::1 10388 # Per bank write bursts
system.physmem.perBankRdBursts::2 10224 # Per bank write bursts
system.physmem.perBankRdBursts::3 10067 # Per bank write bursts
system.physmem.perBankRdBursts::4 10353 # Per bank write bursts
system.physmem.perBankRdBursts::5 10360 # Per bank write bursts
system.physmem.perBankRdBursts::6 9794 # Per bank write bursts
system.physmem.perBankRdBursts::7 10229 # Per bank write bursts
system.physmem.perBankRdBursts::8 10568 # Per bank write bursts
system.physmem.perBankRdBursts::9 10626 # Per bank write bursts
system.physmem.perBankRdBursts::10 10567 # Per bank write bursts
system.physmem.perBankRdBursts::11 10241 # Per bank write bursts
system.physmem.perBankRdBursts::12 10307 # Per bank write bursts
system.physmem.perBankRdBursts::13 10590 # Per bank write bursts
system.physmem.perBankRdBursts::14 10494 # Per bank write bursts
system.physmem.perBankRdBursts::15 10573 # Per bank write bursts
system.physmem.perBankWrBursts::0 7166 # Per bank write bursts
system.physmem.perBankWrBursts::1 7280 # Per bank write bursts
system.physmem.perBankWrBursts::2 7303 # Per bank write bursts
system.physmem.perBankWrBursts::3 7011 # Per bank write bursts
system.physmem.perBankWrBursts::4 7144 # Per bank write bursts
system.physmem.perBankWrBursts::5 7304 # Per bank write bursts
system.physmem.perBankWrBursts::6 6890 # Per bank write bursts
system.physmem.perBankWrBursts::7 7170 # Per bank write bursts
system.physmem.perBankWrBursts::8 7244 # Per bank write bursts
system.physmem.perBankWrBursts::9 7072 # Per bank write bursts
system.physmem.perBankWrBursts::10 7215 # Per bank write bursts
system.physmem.perBankWrBursts::11 7126 # Per bank write bursts
system.physmem.perBankWrBursts::12 7072 # Per bank write bursts
system.physmem.perBankWrBursts::13 7397 # Per bank write bursts
system.physmem.perBankWrBursts::14 7353 # Per bank write bursts
system.physmem.perBankWrBursts::15 7483 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 60093907500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 165736 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 115250 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 164444 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 1265 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 17 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 491 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 503 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 6946 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 7138 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 7140 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 7142 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 7143 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 7151 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 7145 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 7154 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 7174 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 7162 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 7183 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 7195 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 7151 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 7140 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 7139 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 7135 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 3 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 47112 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 381.637629 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 228.425229 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 356.616158 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 14360 30.48% 30.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 9586 20.35% 50.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 5012 10.64% 61.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 3327 7.06% 68.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 2470 5.24% 73.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1960 4.16% 77.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 1618 3.43% 81.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 1472 3.12% 84.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 7307 15.51% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 47112 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 7135 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 23.226489 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::gmean 17.911576 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 310.890099 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023 7133 99.97% 99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::25600-26623 1 0.01% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 7135 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 7135 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 16.149965 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 16.141117 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 0.557028 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16 6628 92.89% 92.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17 11 0.15% 93.05% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18 441 6.18% 99.23% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19 47 0.66% 99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20 7 0.10% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24 1 0.01% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 7135 # Writes before turning the bus around for reads
system.physmem.totQLat 1892978500 # Total ticks spent queuing
system.physmem.totMemAccLat 5000341000 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 828630000 # Total ticks spent in databus transfers
system.physmem.avgQLat 11422.34 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 30172.34 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 176.50 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 122.72 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 176.51 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 122.74 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 2.34 # Data bus utilization in percentage
system.physmem.busUtilRead 1.38 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.96 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
system.physmem.avgWrQLen 23.81 # Average write queue length when enqueuing
system.physmem.readRowHits 144145 # Number of row buffer hits during reads
system.physmem.writeRowHits 89685 # Number of row buffer hits during writes
system.physmem.readRowHitRate 86.98 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 77.82 # Row buffer hit rate for writes
system.physmem.avgGap 213867.98 # Average gap between requests
system.physmem.pageHitRate 83.22 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 171128160 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 93373500 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 637486200 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 370921680 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 3924557520 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 12045269070 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 25486025250 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 42728761380 # Total energy per rank (pJ)
system.physmem_0.averagePower 711.117850 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 42256937250 # Time in different power states
system.physmem_0.memoryStateTime::REF 2006420000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 15823407750 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 184781520 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 100823250 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 654677400 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 375431760 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 3924557520 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 12738285900 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 24878115750 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 42856673100 # Total energy per rank (pJ)
system.physmem_1.averagePower 713.246634 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 41240527500 # Time in different power states
system.physmem_1.memoryStateTime::REF 2006420000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 16840206000 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.pwrStateResidencyTicks::UNDEFINED 60093931000 # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups 14696108 # Number of BP lookups
system.cpu.branchPred.condPredicted 9501028 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 386035 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 10214286 # Number of BTB lookups
system.cpu.branchPred.BTBHits 6368013 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 62.344181 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 1712199 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 84611 # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups 37560 # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits 31792 # Number of indirect target hits.
system.cpu.branchPred.indirectMisses 5768 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 7597 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 20579333 # DTB read hits
system.cpu.dtb.read_misses 95423 # DTB read misses
system.cpu.dtb.read_acv 10 # DTB read access violations
system.cpu.dtb.read_accesses 20674756 # DTB read accesses
system.cpu.dtb.write_hits 14666035 # DTB write hits
system.cpu.dtb.write_misses 8840 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 14674875 # DTB write accesses
system.cpu.dtb.data_hits 35245368 # DTB hits
system.cpu.dtb.data_misses 104263 # DTB misses
system.cpu.dtb.data_acv 10 # DTB access violations
system.cpu.dtb.data_accesses 35349631 # DTB accesses
system.cpu.itb.fetch_hits 25649355 # ITB hits
system.cpu.itb.fetch_misses 5175 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 25654530 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4583 # Number of system calls
system.cpu.pwrStateResidencyTicks::ON 60093931000 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 120187862 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 88438073 # Number of instructions committed
system.cpu.committedOps 88438073 # Number of ops (including micro ops) committed
system.cpu.discardedOps 1085816 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 1.359006 # CPI: cycles per instruction
system.cpu.ipc 0.735832 # IPC: instructions per cycle
system.cpu.op_class_0::No_OpClass 8748916 9.89% 9.89% # Class of committed instruction
system.cpu.op_class_0::IntAlu 44394799 50.20% 60.09% # Class of committed instruction
system.cpu.op_class_0::IntMult 41101 0.05% 60.14% # Class of committed instruction
system.cpu.op_class_0::IntDiv 0 0.00% 60.14% # Class of committed instruction
system.cpu.op_class_0::FloatAdd 114304 0.13% 60.27% # Class of committed instruction
system.cpu.op_class_0::FloatCmp 84 0.00% 60.27% # Class of committed instruction
system.cpu.op_class_0::FloatCvt 113640 0.13% 60.40% # Class of committed instruction
system.cpu.op_class_0::FloatMult 50 0.00% 60.40% # Class of committed instruction
system.cpu.op_class_0::FloatDiv 37764 0.04% 60.44% # Class of committed instruction
system.cpu.op_class_0::FloatSqrt 0 0.00% 60.44% # Class of committed instruction
system.cpu.op_class_0::SimdAdd 0 0.00% 60.44% # Class of committed instruction
system.cpu.op_class_0::SimdAddAcc 0 0.00% 60.44% # Class of committed instruction
system.cpu.op_class_0::SimdAlu 0 0.00% 60.44% # Class of committed instruction
system.cpu.op_class_0::SimdCmp 0 0.00% 60.44% # Class of committed instruction
system.cpu.op_class_0::SimdCvt 0 0.00% 60.44% # Class of committed instruction
system.cpu.op_class_0::SimdMisc 0 0.00% 60.44% # Class of committed instruction
system.cpu.op_class_0::SimdMult 0 0.00% 60.44% # Class of committed instruction
system.cpu.op_class_0::SimdMultAcc 0 0.00% 60.44% # Class of committed instruction
system.cpu.op_class_0::SimdShift 0 0.00% 60.44% # Class of committed instruction
system.cpu.op_class_0::SimdShiftAcc 0 0.00% 60.44% # Class of committed instruction
system.cpu.op_class_0::SimdSqrt 0 0.00% 60.44% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAdd 0 0.00% 60.44% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAlu 0 0.00% 60.44% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCmp 0 0.00% 60.44% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCvt 0 0.00% 60.44% # Class of committed instruction
system.cpu.op_class_0::SimdFloatDiv 0 0.00% 60.44% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMisc 0 0.00% 60.44% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMult 0 0.00% 60.44% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 60.44% # Class of committed instruction
system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 60.44% # Class of committed instruction
system.cpu.op_class_0::MemRead 20366786 23.03% 83.47% # Class of committed instruction
system.cpu.op_class_0::MemWrite 14620629 16.53% 100.00% # Class of committed instruction
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::total 88438073 # Class of committed instruction
system.cpu.tickCycles 91997493 # Number of cycles that the object actually ticked
system.cpu.idleCycles 28190369 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 60093931000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 200806 # number of replacements
system.cpu.dcache.tags.tagsinuse 4070.595144 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 34648172 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 204902 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 169.096309 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 696470500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 4070.595144 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.993798 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.993798 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 646 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 3399 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 70184522 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 70184522 # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 60093931000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 20314904 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 20314904 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 14333268 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 14333268 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 34648172 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 34648172 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 34648172 # number of overall hits
system.cpu.dcache.overall_hits::total 34648172 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 61529 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 61529 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 280109 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 280109 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 341638 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 341638 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 341638 # number of overall misses
system.cpu.dcache.overall_misses::total 341638 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 2787384000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 2787384000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 21745232000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 21745232000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 24532616000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 24532616000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 24532616000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 24532616000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 20376433 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 20376433 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 34989810 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 34989810 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 34989810 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 34989810 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003020 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.003020 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.019168 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.019168 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.009764 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.009764 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.009764 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.009764 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 45301.955176 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 45301.955176 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77631.322092 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 77631.322092 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 71808.803470 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 71808.803470 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 71808.803470 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 71808.803470 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks 168116 # number of writebacks
system.cpu.dcache.writebacks::total 168116 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 194 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 194 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 136542 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 136542 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 136736 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 136736 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 136736 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 136736 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61335 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 61335 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143567 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 143567 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 204902 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 204902 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 204902 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 204902 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2722762000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2722762000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10994246500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 10994246500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13717008500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 13717008500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13717008500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 13717008500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003010 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003010 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009824 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009824 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005856 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.005856 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005856 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.005856 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 44391.652401 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 44391.652401 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76579.203438 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76579.203438 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66944.239197 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 66944.239197 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66944.239197 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 66944.239197 # average overall mshr miss latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 60093931000 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 153916 # number of replacements
system.cpu.icache.tags.tagsinuse 1931.382130 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 25493390 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 155964 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 163.456887 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 42683279500 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 1931.382130 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.943058 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.943058 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 163 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 1033 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 801 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 51454674 # Number of tag accesses
system.cpu.icache.tags.data_accesses 51454674 # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 60093931000 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 25493390 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 25493390 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 25493390 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 25493390 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 25493390 # number of overall hits
system.cpu.icache.overall_hits::total 25493390 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 155965 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 155965 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 155965 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 155965 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 155965 # number of overall misses
system.cpu.icache.overall_misses::total 155965 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 2518921000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 2518921000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 2518921000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 2518921000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 2518921000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 2518921000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 25649355 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 25649355 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 25649355 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 25649355 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 25649355 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 25649355 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.006081 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.006081 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.006081 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.006081 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.006081 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.006081 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16150.553009 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 16150.553009 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 16150.553009 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 16150.553009 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 16150.553009 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 16150.553009 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks 153916 # number of writebacks
system.cpu.icache.writebacks::total 153916 # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 155965 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 155965 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 155965 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 155965 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 155965 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 155965 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2362957000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 2362957000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2362957000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 2362957000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2362957000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 2362957000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006081 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006081 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006081 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.006081 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006081 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.006081 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15150.559420 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15150.559420 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15150.559420 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 15150.559420 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15150.559420 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 15150.559420 # average overall mshr miss latency
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 60093931000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 135276 # number of replacements
system.cpu.l2cache.tags.tagsinuse 31728.322423 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 547427 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 168044 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 3.257641 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 13928082000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 716.089195 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1994.899360 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 29017.333867 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.021853 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.060879 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.885539 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.968272 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 147 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 968 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9499 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 22051 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 103 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 5892756 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 5892756 # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 60093931000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 168116 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 168116 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 153916 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 153916 # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 12659 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 12659 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 149116 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 149116 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 33355 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 33355 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst 149116 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 46014 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 195130 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 149116 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 46014 # number of overall hits
system.cpu.l2cache.overall_hits::total 195130 # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 130908 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 130908 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 6849 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 6849 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 27980 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 27980 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 6849 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 158888 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 165737 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 6849 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 158888 # number of overall misses
system.cpu.l2cache.overall_misses::total 165737 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10645913500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 10645913500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 563137000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 563137000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2280269500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 2280269500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 563137000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 12926183000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 13489320000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 563137000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 12926183000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 13489320000 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 168116 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 168116 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 153916 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 153916 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 143567 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 143567 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 155965 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 155965 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 61335 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 61335 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 155965 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 204902 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 360867 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 155965 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 204902 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 360867 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911825 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.911825 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.043914 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.043914 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.456183 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.456183 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.043914 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.775434 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.459274 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.043914 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.775434 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.459274 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81323.628044 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81323.628044 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82221.784202 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82221.784202 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81496.408149 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81496.408149 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82221.784202 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81354.054428 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 81389.912934 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82221.784202 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81354.054428 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 81389.912934 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.writebacks::writebacks 115251 # number of writebacks
system.cpu.l2cache.writebacks::total 115251 # number of writebacks
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 117 # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total 117 # number of CleanEvict MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130908 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 130908 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 6849 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 6849 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 27980 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 27980 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 6849 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 158888 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 165737 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 6849 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 158888 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 165737 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9336833500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9336833500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 494657000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 494657000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2000469500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2000469500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 494657000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11337303000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 11831960000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 494657000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11337303000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 11831960000 # number of overall MSHR miss cycles
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911825 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911825 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.043914 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.043914 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.456183 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.456183 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.043914 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775434 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.459274 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.043914 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775434 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.459274 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71323.628044 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71323.628044 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72223.244269 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72223.244269 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71496.408149 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71496.408149 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72223.244269 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71354.054428 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71389.973271 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72223.244269 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71354.054428 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71389.973271 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 715589 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 354722 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 4259 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 4259 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 60093931000 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 217299 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 283367 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 153916 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 52715 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 143567 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 143567 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 155965 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 61335 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 465845 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 610610 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 1076455 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19832320 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23873152 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 43705472 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 135276 # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic 7376064 # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples 496143 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.008584 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.092253 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 491884 99.14% 99.14% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 4259 0.86% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 496143 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 679826500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 233946499 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.4 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 307357491 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%)
system.membus.snoop_filter.tot_requests 296869 # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests 131133 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 60093931000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 34828 # Transaction distribution
system.membus.trans_dist::WritebackDirty 115250 # Transaction distribution
system.membus.trans_dist::CleanEvict 15883 # Transaction distribution
system.membus.trans_dist::ReadExReq 130908 # Transaction distribution
system.membus.trans_dist::ReadExResp 130908 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 34828 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 462605 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 462605 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17983104 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 17983104 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples 165736 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 165736 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 165736 # Request fanout histogram
system.membus.reqLayer0.occupancy 829286500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 1.4 # Layer utilization (%)
system.membus.respLayer1.occupancy 875094750 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 1.5 # Layer utilization (%)
---------- End Simulation Statistics ----------
|