blob: dfd14c5766a09308da80b8b21366b16609f8bf3b (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
|
---------- Begin Simulation Statistics ----------
sim_seconds 0.059580 # Number of seconds simulated
sim_ticks 59579614000 # Number of ticks simulated
final_tick 59579614000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 321432 # Simulator instruction rate (inst/s)
host_op_rate 321432 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 216544599 # Simulator tick rate (ticks/s)
host_mem_usage 304972 # Number of bytes of host memory used
host_seconds 275.14 # Real time elapsed on the host
sim_insts 88438073 # Number of instructions simulated
sim_ops 88438073 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 500672 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 10147648 # Number of bytes read from this memory
system.physmem.bytes_read::total 10648320 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 500672 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 500672 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 7320576 # Number of bytes written to this memory
system.physmem.bytes_written::total 7320576 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 7823 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 158557 # Number of read requests responded to by this memory
system.physmem.num_reads::total 166380 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 114384 # Number of write requests responded to by this memory
system.physmem.num_writes::total 114384 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 8403411 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 170320808 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 178724219 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 8403411 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 8403411 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 122870484 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 122870484 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 122870484 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 8403411 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 170320808 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 301594703 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 166380 # Number of read requests accepted
system.physmem.writeReqs 114384 # Number of write requests accepted
system.physmem.readBursts 166380 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 114384 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 10648064 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 256 # Total number of bytes read from write queue
system.physmem.bytesWritten 7319040 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 10648320 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 7320576 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 4 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 10451 # Per bank write bursts
system.physmem.perBankRdBursts::1 10506 # Per bank write bursts
system.physmem.perBankRdBursts::2 10284 # Per bank write bursts
system.physmem.perBankRdBursts::3 10088 # Per bank write bursts
system.physmem.perBankRdBursts::4 10415 # Per bank write bursts
system.physmem.perBankRdBursts::5 10418 # Per bank write bursts
system.physmem.perBankRdBursts::6 9828 # Per bank write bursts
system.physmem.perBankRdBursts::7 10277 # Per bank write bursts
system.physmem.perBankRdBursts::8 10580 # Per bank write bursts
system.physmem.perBankRdBursts::9 10645 # Per bank write bursts
system.physmem.perBankRdBursts::10 10557 # Per bank write bursts
system.physmem.perBankRdBursts::11 10259 # Per bank write bursts
system.physmem.perBankRdBursts::12 10298 # Per bank write bursts
system.physmem.perBankRdBursts::13 10623 # Per bank write bursts
system.physmem.perBankRdBursts::14 10516 # Per bank write bursts
system.physmem.perBankRdBursts::15 10631 # Per bank write bursts
system.physmem.perBankWrBursts::0 7162 # Per bank write bursts
system.physmem.perBankWrBursts::1 7274 # Per bank write bursts
system.physmem.perBankWrBursts::2 7295 # Per bank write bursts
system.physmem.perBankWrBursts::3 6999 # Per bank write bursts
system.physmem.perBankWrBursts::4 7127 # Per bank write bursts
system.physmem.perBankWrBursts::5 7182 # Per bank write bursts
system.physmem.perBankWrBursts::6 6834 # Per bank write bursts
system.physmem.perBankWrBursts::7 7095 # Per bank write bursts
system.physmem.perBankWrBursts::8 7222 # Per bank write bursts
system.physmem.perBankWrBursts::9 6994 # Per bank write bursts
system.physmem.perBankWrBursts::10 7111 # Per bank write bursts
system.physmem.perBankWrBursts::11 6991 # Per bank write bursts
system.physmem.perBankWrBursts::12 6990 # Per bank write bursts
system.physmem.perBankWrBursts::13 7296 # Per bank write bursts
system.physmem.perBankWrBursts::14 7306 # Per bank write bursts
system.physmem.perBankWrBursts::15 7482 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 59579590000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 166380 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 114384 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 164758 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 1592 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 26 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 735 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 762 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 6133 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 6992 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 7036 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 7064 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 7059 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 7063 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 7067 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 7065 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 7144 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 7119 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 7223 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 7229 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 7151 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 7372 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 7099 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 7043 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 12 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 54737 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 328.220838 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 195.100573 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 330.685535 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 19472 35.57% 35.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 11861 21.67% 57.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 5645 10.31% 67.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 3680 6.72% 74.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 2860 5.22% 79.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 2018 3.69% 83.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 1694 3.09% 86.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 1489 2.72% 89.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 6018 10.99% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 54737 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 7040 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 23.631676 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 336.376134 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023 7037 99.96% 99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047 2 0.03% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::27648-28671 1 0.01% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 7040 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 7040 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 16.244318 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 16.229045 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 0.737232 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16 6278 89.18% 89.18% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17 16 0.23% 89.40% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18 578 8.21% 97.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19 145 2.06% 99.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20 15 0.21% 99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21 3 0.04% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22 1 0.01% 99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23 2 0.03% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24 1 0.01% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26 1 0.01% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 7040 # Writes before turning the bus around for reads
system.physmem.totQLat 2004219750 # Total ticks spent queuing
system.physmem.totMemAccLat 5123769750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 831880000 # Total ticks spent in databus transfers
system.physmem.avgQLat 12046.33 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 30796.33 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 178.72 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 122.84 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 178.72 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 122.87 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 2.36 # Data bus utilization in percentage
system.physmem.busUtilRead 1.40 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.96 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing
system.physmem.avgWrQLen 24.12 # Average write queue length when enqueuing
system.physmem.readRowHits 144447 # Number of row buffer hits during reads
system.physmem.writeRowHits 81540 # Number of row buffer hits during writes
system.physmem.readRowHitRate 86.82 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 71.29 # Row buffer hit rate for writes
system.physmem.avgGap 212205.23 # Average gap between requests
system.physmem.pageHitRate 80.49 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 199372320 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 108784500 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 641464200 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 368938800 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 3890992560 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 12501731340 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 24777284250 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 42488567970 # Total energy per rank (pJ)
system.physmem_0.averagePower 713.220229 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 41071172000 # Time in different power states
system.physmem_0.memoryStateTime::REF 1989260000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 16512675000 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 214189920 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 116869500 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 655792800 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 371790000 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 3890992560 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 13114227690 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 24240006750 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 42603869220 # Total energy per rank (pJ)
system.physmem_1.averagePower 715.155695 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 40171909250 # Time in different power states
system.physmem_1.memoryStateTime::REF 1989260000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 17411703250 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.branchPred.lookups 14668515 # Number of BP lookups
system.cpu.branchPred.condPredicted 9490335 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 391198 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 9984003 # Number of BTB lookups
system.cpu.branchPred.BTBHits 6387554 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 63.977885 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 1708558 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 85259 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 20570256 # DTB read hits
system.cpu.dtb.read_misses 97321 # DTB read misses
system.cpu.dtb.read_acv 10 # DTB read access violations
system.cpu.dtb.read_accesses 20667577 # DTB read accesses
system.cpu.dtb.write_hits 14665734 # DTB write hits
system.cpu.dtb.write_misses 9406 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 14675140 # DTB write accesses
system.cpu.dtb.data_hits 35235990 # DTB hits
system.cpu.dtb.data_misses 106727 # DTB misses
system.cpu.dtb.data_acv 10 # DTB access violations
system.cpu.dtb.data_accesses 35342717 # DTB accesses
system.cpu.itb.fetch_hits 25623202 # ITB hits
system.cpu.itb.fetch_misses 5252 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 25628454 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4583 # Number of system calls
system.cpu.numCycles 119159228 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 88438073 # Number of instructions committed
system.cpu.committedOps 88438073 # Number of ops (including micro ops) committed
system.cpu.discardedOps 1111760 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 1.347375 # CPI: cycles per instruction
system.cpu.ipc 0.742184 # IPC: instructions per cycle
system.cpu.tickCycles 91522395 # Number of cycles that the object actually ticked
system.cpu.idleCycles 27636833 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements 200775 # number of replacements
system.cpu.dcache.tags.tagsinuse 4070.716592 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 34616548 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 204871 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 168.967536 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 688117500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 4070.716592 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.993827 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.993827 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 687 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 3359 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 70177059 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 70177059 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 20283298 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 20283298 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 14333250 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 14333250 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 34616548 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 34616548 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 34616548 # number of overall hits
system.cpu.dcache.overall_hits::total 34616548 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 89419 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 89419 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 280127 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 280127 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 369546 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 369546 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 369546 # number of overall misses
system.cpu.dcache.overall_misses::total 369546 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 4766015000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 4766015000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 21725113500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 21725113500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 26491128500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 26491128500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 26491128500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 26491128500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 20372717 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 20372717 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 34986094 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 34986094 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 34986094 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 34986094 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004389 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.004389 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.019169 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.019169 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.010563 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.010563 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.010563 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.010563 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53299.802055 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 53299.802055 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77554.514559 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 77554.514559 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 71685.604769 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 71685.604769 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 71685.604769 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 71685.604769 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 168451 # number of writebacks
system.cpu.dcache.writebacks::total 168451 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 28112 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 28112 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 136563 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 136563 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 164675 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 164675 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 164675 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 164675 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61307 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 61307 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143564 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 143564 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 204871 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 204871 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 204871 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 204871 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2678080000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2678080000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10985374000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 10985374000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13663454000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 13663454000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13663454000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 13663454000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003009 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003009 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009824 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009824 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005856 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.005856 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005856 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.005856 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 43683.103071 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 43683.103071 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76519.001978 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76519.001978 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66692.962889 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 66692.962889 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66692.962889 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 66692.962889 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 153439 # number of replacements
system.cpu.icache.tags.tagsinuse 1932.585595 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 25467714 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 155487 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 163.793205 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 42332946500 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 1932.585595 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.943645 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.943645 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 157 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 1043 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 798 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 51401891 # Number of tag accesses
system.cpu.icache.tags.data_accesses 51401891 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 25467714 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 25467714 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 25467714 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 25467714 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 25467714 # number of overall hits
system.cpu.icache.overall_hits::total 25467714 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 155488 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 155488 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 155488 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 155488 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 155488 # number of overall misses
system.cpu.icache.overall_misses::total 155488 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 2558679500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 2558679500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 2558679500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 2558679500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 2558679500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 2558679500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 25623202 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 25623202 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 25623202 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 25623202 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 25623202 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 25623202 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.006068 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.006068 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.006068 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.006068 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.006068 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.006068 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16455.800448 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 16455.800448 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 16455.800448 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 16455.800448 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 16455.800448 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 16455.800448 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 155488 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 155488 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 155488 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 155488 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 155488 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 155488 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2403192500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 2403192500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2403192500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 2403192500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2403192500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 2403192500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006068 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006068 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006068 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.006068 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006068 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.006068 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15455.806879 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15455.806879 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15455.806879 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 15455.806879 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15455.806879 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 15455.806879 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 132455 # number of replacements
system.cpu.l2cache.tags.tagsinuse 30425.611503 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 404125 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 164531 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 2.456224 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 25960.344438 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2481.956505 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 1983.310560 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.792247 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.075743 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.060526 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.928516 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32076 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 937 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 11867 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 19026 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 126 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978882 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 6024680 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 6024680 # Number of data accesses
system.cpu.l2cache.Writeback_hits::writebacks 168451 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 168451 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 12683 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 12683 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 147664 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 147664 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 33631 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 33631 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst 147664 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 46314 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 193978 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 147664 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 46314 # number of overall hits
system.cpu.l2cache.overall_hits::total 193978 # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 130882 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 130882 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 7824 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 7824 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 27675 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 27675 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 7824 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 158557 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 166381 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 7824 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 158557 # number of overall misses
system.cpu.l2cache.overall_misses::total 166381 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10636812500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 10636812500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 619419000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 619419000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2232532000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 2232532000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 619419000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 12869344500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 13488763500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 619419000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 12869344500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 13488763500 # number of overall miss cycles
system.cpu.l2cache.Writeback_accesses::writebacks 168451 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 168451 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 143565 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 143565 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 155488 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 155488 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 61306 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 61306 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 155488 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 204871 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 360359 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 155488 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 204871 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 360359 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911657 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.911657 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.050319 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.050319 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.451424 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.451424 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.050319 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.773936 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.461709 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.050319 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.773936 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.461709 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81270.247246 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81270.247246 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79169.095092 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79169.095092 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80669.629630 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80669.629630 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79169.095092 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81165.413700 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 81071.537615 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79169.095092 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81165.413700 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 81071.537615 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 114384 # number of writebacks
system.cpu.l2cache.writebacks::total 114384 # number of writebacks
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 2093 # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total 2093 # number of CleanEvict MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130882 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 130882 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 7824 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 7824 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 27675 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 27675 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 7824 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 158557 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 166381 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 7824 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 158557 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 166381 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9327992500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9327992500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 541189000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 541189000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1955782000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1955782000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 541189000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11283774500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 11824963500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 541189000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11283774500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 11824963500 # number of overall MSHR miss cycles
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911657 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911657 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.050319 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.050319 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.451424 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.451424 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.050319 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.773936 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.461709 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.050319 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.773936 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.461709 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71270.247246 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71270.247246 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69170.373211 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69170.373211 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70669.629630 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70669.629630 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69170.373211 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71165.413700 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71071.597718 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69170.373211 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71165.413700 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71071.597718 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadResp 216793 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 282835 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 203834 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 143565 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 143565 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 155488 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 61306 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 464414 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 610517 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 1074931 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9951168 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23892608 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 33843776 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 132455 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 847028 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 1.156376 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.363212 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 714573 84.36% 84.36% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 132455 15.64% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 847028 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 525737500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 233232496 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.4 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 307309993 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%)
system.membus.trans_dist::ReadResp 35498 # Transaction distribution
system.membus.trans_dist::Writeback 114384 # Transaction distribution
system.membus.trans_dist::CleanEvict 16134 # Transaction distribution
system.membus.trans_dist::ReadExReq 130882 # Transaction distribution
system.membus.trans_dist::ReadExResp 130882 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 35498 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 463278 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 463278 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17968896 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 17968896 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 296898 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 296898 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 296898 # Request fanout histogram
system.membus.reqLayer0.occupancy 824886500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 1.4 # Layer utilization (%)
system.membus.respLayer1.occupancy 878487500 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 1.5 # Layer utilization (%)
---------- End Simulation Statistics ----------
|