blob: 7baadddcc548efe8ccae94655e8e223a39f80711 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
|
---------- Begin Simulation Statistics ----------
sim_seconds 0.021620 # Number of seconds simulated
sim_ticks 21619648000 # Number of ticks simulated
final_tick 21619648000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 236725 # Simulator instruction rate (inst/s)
host_op_rate 236725 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 64301983 # Simulator tick rate (ticks/s)
host_mem_usage 228176 # Number of bytes of host memory used
host_seconds 336.22 # Real time elapsed on the host
sim_insts 79591756 # Number of instructions simulated
sim_ops 79591756 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 559360 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 10295744 # Number of bytes read from this memory
system.physmem.bytes_read::total 10855104 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 559360 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 559360 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 7426560 # Number of bytes written to this memory
system.physmem.bytes_written::total 7426560 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 8740 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 160871 # Number of read requests responded to by this memory
system.physmem.num_reads::total 169611 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 116040 # Number of write requests responded to by this memory
system.physmem.num_writes::total 116040 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 25872762 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 476221630 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 502094391 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 25872762 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 25872762 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 343509756 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 343509756 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 343509756 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 25872762 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 476221630 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 845604147 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 22479620 # DTB read hits
system.cpu.dtb.read_misses 218266 # DTB read misses
system.cpu.dtb.read_acv 51 # DTB read access violations
system.cpu.dtb.read_accesses 22697886 # DTB read accesses
system.cpu.dtb.write_hits 15794697 # DTB write hits
system.cpu.dtb.write_misses 42457 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 15837154 # DTB write accesses
system.cpu.dtb.data_hits 38274317 # DTB hits
system.cpu.dtb.data_misses 260723 # DTB misses
system.cpu.dtb.data_acv 51 # DTB access violations
system.cpu.dtb.data_accesses 38535040 # DTB accesses
system.cpu.itb.fetch_hits 14126097 # ITB hits
system.cpu.itb.fetch_misses 39352 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 14165449 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4583 # Number of system calls
system.cpu.numCycles 43239299 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 16709943 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 10781072 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 476192 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 12038225 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 7471491 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 1995310 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 44665 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 15444845 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 106679218 # Number of instructions fetch has processed
system.cpu.fetch.Branches 16709943 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 9466801 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 19799027 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 2146422 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 5702055 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 8316 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 320776 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 14126097 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 222277 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 42829816 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.490770 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.154588 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 23030789 53.77% 53.77% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 1545838 3.61% 57.38% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 1407824 3.29% 60.67% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 1518177 3.54% 64.21% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 4200095 9.81% 74.02% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 1866083 4.36% 78.38% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 683567 1.60% 79.97% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 1088540 2.54% 82.51% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 7488903 17.49% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 42829816 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.386453 # Number of branch fetches per cycle
system.cpu.fetch.rate 2.467182 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 16586159 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 5216387 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 18831807 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 747368 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 1448095 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 3802176 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 109343 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 104798684 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 306113 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 1448095 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 17060162 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 2943499 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 82970 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 19071081 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 2224009 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 103374463 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 294 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 47714 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 2072135 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 62309566 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 124647358 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 124190382 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 456976 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 9762685 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 5585 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 5583 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 4545963 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 23367723 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 16390642 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 1133008 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 393146 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 91432081 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 5446 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 89033358 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 121532 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 11257440 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 4905922 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 863 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 42829816 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 2.078770 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 2.113525 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 14329925 33.46% 33.46% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 7119620 16.62% 50.08% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 5526453 12.90% 62.98% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 4793299 11.19% 74.18% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 4689695 10.95% 85.13% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 2671983 6.24% 91.36% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 1950910 4.56% 95.92% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 1326668 3.10% 99.02% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 421263 0.98% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 42829816 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 128939 6.83% 6.83% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 6.83% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 6.83% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.83% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.83% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.83% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 6.83% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.83% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.83% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.83% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.83% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.83% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.83% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.83% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.83% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 6.83% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.83% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 6.83% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.83% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.83% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.83% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.83% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.83% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.83% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.83% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.83% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.83% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.83% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.83% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 795203 42.12% 48.94% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 964007 51.06% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 49729867 55.86% 55.86% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 43817 0.05% 55.90% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.90% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 121200 0.14% 56.04% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 87 0.00% 56.04% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 122187 0.14% 56.18% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 56 0.00% 56.18% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 38946 0.04% 56.22% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.22% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.22% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.22% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.22% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.22% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.22% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.22% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.22% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.22% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.22% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.22% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.22% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.22% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.22% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.22% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.22% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.22% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.22% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.22% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.22% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.22% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 22972171 25.80% 82.02% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 16005027 17.98% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 89033358 # Type of FU issued
system.cpu.iq.rate 2.059084 # Inst issue rate
system.cpu.iq.fu_busy_cnt 1888149 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.021207 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 222297193 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 102291434 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 86992301 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 609020 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 419648 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 296730 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 90616918 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 304589 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 1450786 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 3091085 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 5211 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 17173 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 1777265 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 2461 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 40 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 1448095 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 1762662 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 92194 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 100976081 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 242299 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 23367723 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 16390642 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 5446 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 53221 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 430 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 17173 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 250537 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 173902 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 424439 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 88065648 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 22701440 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 967710 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 9538554 # number of nop insts executed
system.cpu.iew.exec_refs 38538948 # number of memory reference insts executed
system.cpu.iew.exec_branches 15139399 # Number of branches executed
system.cpu.iew.exec_stores 15837508 # Number of stores executed
system.cpu.iew.exec_rate 2.036704 # Inst execution rate
system.cpu.iew.wb_sent 87702246 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 87289031 # cumulative count of insts written-back
system.cpu.iew.wb_producers 33442850 # num instructions producing a value
system.cpu.iew.wb_consumers 43872911 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 2.018743 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.762266 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts 9533571 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 369490 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 41381721 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 2.134775 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.804212 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 18296264 44.21% 44.21% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 7146737 17.27% 61.48% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 3523583 8.51% 70.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 2099457 5.07% 75.07% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 2039541 4.93% 80.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 1177840 2.85% 82.85% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 1135730 2.74% 85.59% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 713898 1.73% 87.32% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 5248671 12.68% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 41381721 # Number of insts commited each cycle
system.cpu.commit.committedInsts 88340672 # Number of instructions committed
system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 34890015 # Number of memory references committed
system.cpu.commit.loads 20276638 # Number of loads committed
system.cpu.commit.membars 0 # Number of memory barriers committed
system.cpu.commit.branches 13754477 # Number of branches committed
system.cpu.commit.fp_insts 267754 # Number of committed floating point instructions.
system.cpu.commit.int_insts 77942044 # Number of committed integer instructions.
system.cpu.commit.function_calls 1661057 # Number of function calls committed.
system.cpu.commit.bw_lim_events 5248671 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 132689951 # The number of ROB reads
system.cpu.rob.rob_writes 197200056 # The number of ROB writes
system.cpu.timesIdled 24548 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 409483 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 79591756 # Number of Instructions Simulated
system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated
system.cpu.cpi 0.543264 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.543264 # CPI: Total CPI of All Threads
system.cpu.ipc 1.840727 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.840727 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 116607964 # number of integer regfile reads
system.cpu.int_regfile_writes 57862089 # number of integer regfile writes
system.cpu.fp_regfile_reads 251339 # number of floating regfile reads
system.cpu.fp_regfile_writes 241385 # number of floating regfile writes
system.cpu.misc_regfile_reads 38087 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
system.cpu.icache.replacements 92930 # number of replacements
system.cpu.icache.tagsinuse 1930.212243 # Cycle average of tags in use
system.cpu.icache.total_refs 14026666 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 94978 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 147.683316 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 18067713000 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 1930.212243 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.942486 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.942486 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 14026666 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 14026666 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 14026666 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 14026666 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 14026666 # number of overall hits
system.cpu.icache.overall_hits::total 14026666 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 99431 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 99431 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 99431 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 99431 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 99431 # number of overall misses
system.cpu.icache.overall_misses::total 99431 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 1030437000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 1030437000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 1030437000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 1030437000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 1030437000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 1030437000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 14126097 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 14126097 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 14126097 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 14126097 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 14126097 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 14126097 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007039 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.007039 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.007039 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.007039 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.007039 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.007039 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10363.337390 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 10363.337390 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 10363.337390 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 10363.337390 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 10363.337390 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 10363.337390 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4452 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 4452 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 4452 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 4452 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 4452 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 4452 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 94979 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 94979 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 94979 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 94979 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 94979 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 94979 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 637690000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 637690000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 637690000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 637690000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 637690000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 637690000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006724 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006724 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006724 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.006724 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006724 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.006724 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 6714.010465 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 6714.010465 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 6714.010465 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 6714.010465 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 6714.010465 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 6714.010465 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 201568 # number of replacements
system.cpu.dcache.tagsinuse 4075.950137 # Cycle average of tags in use
system.cpu.dcache.total_refs 34352337 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 205664 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 167.031357 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 168155000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4075.950137 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.995105 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.995105 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 20774825 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 20774825 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 13577434 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 13577434 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 78 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 78 # number of LoadLockedReq hits
system.cpu.dcache.demand_hits::cpu.data 34352259 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 34352259 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 34352259 # number of overall hits
system.cpu.dcache.overall_hits::total 34352259 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 251443 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 251443 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1035943 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 1035943 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 1287386 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 1287386 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 1287386 # number of overall misses
system.cpu.dcache.overall_misses::total 1287386 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 8531732000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 8531732000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 45960422000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 45960422000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 54492154000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 54492154000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 54492154000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 54492154000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 21026268 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 21026268 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 78 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 78 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 35639645 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 35639645 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 35639645 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 35639645 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011959 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.011959 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.070890 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.070890 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.036122 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.036122 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.036122 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.036122 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33931.077819 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 33931.077819 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44365.782673 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 44365.782673 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 42327.750962 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 42327.750962 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 42327.750962 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 42327.750962 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 103000 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 17 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 6058.823529 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 166337 # number of writebacks
system.cpu.dcache.writebacks::total 166337 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 189183 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 189183 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 892539 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 892539 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 1081722 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 1081722 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 1081722 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 1081722 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62260 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 62260 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143404 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 143404 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 205664 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 205664 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 205664 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 205664 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1244458000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 1244458000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5521780000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5521780000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6766238000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 6766238000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6766238000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 6766238000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002961 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002961 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009813 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009813 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005771 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.005771 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005771 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.005771 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19988.082236 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19988.082236 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38505.062620 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38505.062620 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 32899.476817 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 32899.476817 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32899.476817 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 32899.476817 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 137209 # number of replacements
system.cpu.l2cache.tagsinuse 29108.919988 # Cycle average of tags in use
system.cpu.l2cache.total_refs 155222 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 168087 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.923462 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 25319.531401 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 1909.557763 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 1879.830824 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.772691 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.058275 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.057368 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.888334 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 86239 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 32344 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 118583 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 166337 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 166337 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 12449 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 12449 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 86239 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 44793 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 131032 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 86239 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 44793 # number of overall hits
system.cpu.l2cache.overall_hits::total 131032 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 8740 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 29910 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 38650 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 130961 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 130961 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 8740 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 160871 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 169611 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 8740 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 160871 # number of overall misses
system.cpu.l2cache.overall_misses::total 169611 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 308686000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1033182500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 1341868500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5027402000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 5027402000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 308686000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 6060584500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 6369270500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 308686000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 6060584500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 6369270500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 94979 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 62254 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 157233 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 166337 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 166337 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 143410 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 143410 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 94979 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 205664 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 300643 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 94979 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 205664 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 300643 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.092020 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.480451 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.245814 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.913193 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.913193 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.092020 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.782203 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.564161 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.092020 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.782203 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.564161 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35318.764302 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34543.045804 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 34718.460543 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 38388.543154 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 38388.543154 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35318.764302 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 37673.567641 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 37552.225386 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35318.764302 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 37673.567641 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 37552.225386 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 34000 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 12 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 2833.333333 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 116040 # number of writebacks
system.cpu.l2cache.writebacks::total 116040 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 8740 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 29910 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 38650 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130961 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 130961 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 8740 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 160871 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 169611 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 8740 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 160871 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 169611 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 281019000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 942134500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1223153500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4629566000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4629566000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 281019000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5571700500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 5852719500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 281019000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5571700500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 5852719500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.092020 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.480451 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.245814 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.913193 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.913193 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.092020 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.782203 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.564161 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.092020 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.782203 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.564161 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32153.203661 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31498.980274 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31646.921087 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35350.722734 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35350.722734 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32153.203661 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34634.586097 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34506.721262 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32153.203661 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34634.586097 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34506.721262 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
|