path: root/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.022297                       # Number of seconds simulated
sim_ticks                                 22296591500                       # Number of ticks simulated
final_tick                                22296591500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 221726                       # Simulator instruction rate (inst/s)
host_op_rate                                   221726                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               62113736                       # Simulator tick rate (ticks/s)
host_mem_usage                                 308500                       # Number of bytes of host memory used
host_seconds                                   358.96                       # Real time elapsed on the host
sim_insts                                    79591756                       # Number of instructions simulated
sim_ops                                      79591756                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst            409984                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          10153216                       # Number of bytes read from this memory
system.physmem.bytes_read::total             10563200                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       409984                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          409984                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      7322432                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7322432                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst               6406                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             158644                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                165050                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          114413                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               114413                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst             18387743                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data            455370768                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total               473758511                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst        18387743                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total           18387743                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks         328410376                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total              328410376                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks         328410376                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst            18387743                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data           455370768                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              802168888                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        165050                       # Number of read requests accepted
system.physmem.writeReqs                       114413                       # Number of write requests accepted
system.physmem.readBursts                      165050                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     114413                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 10562816                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                       384                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   7320896                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  10563200                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                7322432                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                        6                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs          14730                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               10292                       # Per bank write bursts
system.physmem.perBankRdBursts::1               10329                       # Per bank write bursts
system.physmem.perBankRdBursts::2               10209                       # Per bank write bursts
system.physmem.perBankRdBursts::3               10020                       # Per bank write bursts
system.physmem.perBankRdBursts::4               10344                       # Per bank write bursts
system.physmem.perBankRdBursts::5               10314                       # Per bank write bursts
system.physmem.perBankRdBursts::6                9779                       # Per bank write bursts
system.physmem.perBankRdBursts::7               10195                       # Per bank write bursts
system.physmem.perBankRdBursts::8               10531                       # Per bank write bursts
system.physmem.perBankRdBursts::9               10599                       # Per bank write bursts
system.physmem.perBankRdBursts::10              10453                       # Per bank write bursts
system.physmem.perBankRdBursts::11              10204                       # Per bank write bursts
system.physmem.perBankRdBursts::12              10247                       # Per bank write bursts
system.physmem.perBankRdBursts::13              10532                       # Per bank write bursts
system.physmem.perBankRdBursts::14              10447                       # Per bank write bursts
system.physmem.perBankRdBursts::15              10549                       # Per bank write bursts
system.physmem.perBankWrBursts::0                7163                       # Per bank write bursts
system.physmem.perBankWrBursts::1                7267                       # Per bank write bursts
system.physmem.perBankWrBursts::2                7294                       # Per bank write bursts
system.physmem.perBankWrBursts::3                7000                       # Per bank write bursts
system.physmem.perBankWrBursts::4                7127                       # Per bank write bursts
system.physmem.perBankWrBursts::5                7180                       # Per bank write bursts
system.physmem.perBankWrBursts::6                6836                       # Per bank write bursts
system.physmem.perBankWrBursts::7                7102                       # Per bank write bursts
system.physmem.perBankWrBursts::8                7221                       # Per bank write bursts
system.physmem.perBankWrBursts::9                7001                       # Per bank write bursts
system.physmem.perBankWrBursts::10               7100                       # Per bank write bursts
system.physmem.perBankWrBursts::11               7020                       # Per bank write bursts
system.physmem.perBankWrBursts::12               6992                       # Per bank write bursts
system.physmem.perBankWrBursts::13               7297                       # Per bank write bursts
system.physmem.perBankWrBursts::14               7307                       # Per bank write bursts
system.physmem.perBankWrBursts::15               7482                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                     22296560500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  165050                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 114413                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                     51457                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     43023                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     38384                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                     32167                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                        11                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                      838                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                      874                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     1898                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     3531                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     4839                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6052                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     6591                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     6876                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     7135                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     7308                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     7518                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     7900                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     7742                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     8305                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    10160                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     8364                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     9639                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     8083                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      381                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      175                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      104                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                       44                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                       28                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        5                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        4                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        3                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        52310                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      341.858612                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     200.924906                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     342.625607                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          18434     35.24%     35.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        10645     20.35%     55.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         5863     11.21%     66.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         2906      5.56%     72.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2975      5.69%     78.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1493      2.85%     80.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         2022      3.87%     84.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023          988      1.89%     86.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         6984     13.35%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          52310                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          6990                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        23.610300                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      338.218951                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023           6987     99.96%     99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047            2      0.03%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::27648-28671            1      0.01%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            6990                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          6990                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        16.364664                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       16.334270                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        1.064891                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16               6098     87.24%     87.24% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17                 26      0.37%     87.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18                456      6.52%     94.13% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19                208      2.98%     97.11% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20                103      1.47%     98.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21                 57      0.82%     99.40% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22                 21      0.30%     99.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23                 10      0.14%     99.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24                  8      0.11%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::25                  1      0.01%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26                  1      0.01%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::27                  1      0.01%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            6990                       # Writes before turning the bus around for reads
system.physmem.totQLat                     5731685000                       # Total ticks spent queuing
system.physmem.totMemAccLat                8826260000                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    825220000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       34728.22                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  53478.22                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                         473.74                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                         328.34                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                      473.76                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                      328.41                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           6.27                       # Data bus utilization in percentage
system.physmem.busUtilRead                       3.70                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      2.57                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.93                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        24.49                       # Average write queue length when enqueuing
system.physmem.readRowHits                     145441                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     81669                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   88.12                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  71.38                       # Row buffer hit rate for writes
system.physmem.avgGap                        79783.59                       # Average gap between requests
system.physmem.pageHitRate                      81.27                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  190375920                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  103875750                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 635356800                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                369036000                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy             1456007280                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy             6553881090                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy             7626357750                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy              16934890590                       # Total energy per rank (pJ)
system.physmem_0.averagePower              759.674656                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE    12601715000                       # Time in different power states
system.physmem_0.memoryStateTime::REF       744380000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT      8946212500                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  204815520                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  111754500                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 651565200                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                371893680                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy             1456007280                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy             6747677955                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy             7456388250                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy              17000102385                       # Total energy per rank (pJ)
system.physmem_1.averagePower              762.598381                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE    12320846000                       # Time in different power states
system.physmem_1.memoryStateTime::REF       744380000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT      9227273000                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu.branchPred.lookups                16493971                       # Number of BP lookups
system.cpu.branchPred.condPredicted          10685365                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect            327092                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups              8977635                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                 7282355                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             81.116630                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 1973286                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect               2952                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dtb.fetch_hits                           0                       # ITB hits
system.cpu.dtb.fetch_misses                         0                       # ITB misses
system.cpu.dtb.fetch_acv                            0                       # ITB acv
system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
system.cpu.dtb.read_hits                     22518673                       # DTB read hits
system.cpu.dtb.read_misses                     225961                       # DTB read misses
system.cpu.dtb.read_acv                            15                       # DTB read access violations
system.cpu.dtb.read_accesses                 22744634                       # DTB read accesses
system.cpu.dtb.write_hits                    15824450                       # DTB write hits
system.cpu.dtb.write_misses                     44763                       # DTB write misses
system.cpu.dtb.write_acv                            4                       # DTB write access violations
system.cpu.dtb.write_accesses                15869213                       # DTB write accesses
system.cpu.dtb.data_hits                     38343123                       # DTB hits
system.cpu.dtb.data_misses                     270724                       # DTB misses
system.cpu.dtb.data_acv                            19                       # DTB access violations
system.cpu.dtb.data_accesses                 38613847                       # DTB accesses
system.cpu.itb.fetch_hits                    13750650                       # ITB hits
system.cpu.itb.fetch_misses                     29320                       # ITB misses
system.cpu.itb.fetch_acv                            0                       # ITB acv
system.cpu.itb.fetch_accesses                13779970                       # ITB accesses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.read_acv                             0                       # DTB read access violations
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.write_acv                            0                       # DTB write access violations
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.data_hits                            0                       # DTB hits
system.cpu.itb.data_misses                          0                       # DTB misses
system.cpu.itb.data_acv                             0                       # DTB access violations
system.cpu.itb.data_accesses                        0                       # DTB accesses
system.cpu.workload.num_syscalls                 4583                       # Number of system calls
system.cpu.numCycles                         44593188                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles           15564341                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      105145283                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    16493971                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches            9255641                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                      27572822                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                  891924                       # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles                        262                       # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.MiscStallCycles                 4803                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles        325760                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles           89                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                  13750650                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                190232                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes                       1                       # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples           43914039                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              2.394343                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.128103                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                 24384273     55.53%     55.53% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  1520929      3.46%     58.99% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                  1376099      3.13%     62.12% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                  1504413      3.43%     65.55% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  4198532      9.56%     75.11% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                  1828676      4.16%     79.28% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                   668520      1.52%     80.80% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                  1050487      2.39%     83.19% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                  7382110     16.81%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total             43914039                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.369876                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        2.357878                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 14911775                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles               9756593                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                  18301996                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles                594945                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                 348730                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved              3706760                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                 98994                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts              103174683                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                312811                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                 348730                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 15258388                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                 4434115                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles          96788                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                  18534618                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles               5241400                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              102158813                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                  5649                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                  94745                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents                 345515                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents                4735615                       # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands            61411273                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups             123213365                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups        122896091                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups            317273                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps              52546881                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                  8864392                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts               5712                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts           5765                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                   2362727                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             23149705                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            16384887                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           1256801                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores           494099                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                   90814957                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded                5561                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                  88678954                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued             70817                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        11228761                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined      4483589                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved            978                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples      43914039                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         2.019376                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        2.246135                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0            17441953     39.72%     39.72% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1             5726957     13.04%     52.76% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2             5104887     11.62%     64.38% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3             4381256      9.98%     74.36% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4             4320313      9.84%     84.20% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5             2639459      6.01%     90.21% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6             1947949      4.44%     94.65% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7             1377906      3.14%     97.78% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8              973359      2.22%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total        43914039                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                  242855      9.63%      9.63% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%      9.63% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%      9.63% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%      9.63% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%      9.63% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%      9.63% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%      9.63% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%      9.63% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      9.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%      9.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      9.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%      9.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%      9.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%      9.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%      9.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%      9.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      9.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%      9.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      9.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      9.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      9.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      9.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      9.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      9.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      9.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      9.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      9.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      9.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      9.63% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                1163309     46.14%     55.77% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite               1115010     44.23%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu              49423838     55.73%     55.73% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                43986      0.05%     55.78% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     55.78% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd              121174      0.14%     55.92% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                  92      0.00%     55.92% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt              120676      0.14%     56.06% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                 62      0.00%     56.06% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv               39089      0.04%     56.10% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     56.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     56.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     56.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     56.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     56.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     56.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     56.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     56.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     56.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     56.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     56.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     56.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     56.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     56.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     56.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     56.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     56.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     56.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     56.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     56.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     56.10% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             22912706     25.84%     81.94% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite            16017331     18.06%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total               88678954                       # Type of FU issued
system.cpu.iq.rate                           1.988621                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                     2521174                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.028430                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads          223254204                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         101651163                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses     86893480                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads              609734                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes             418232                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses       299390                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses               90895107                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                  305021                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          1671418                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      2873067                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses         5610                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        20361                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      1771510                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads         3045                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked        204833                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                 348730                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                 1277507                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles               2721681                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           100319642                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            124919                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              23149705                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             16384887                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts               5561                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                   3725                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents               2720217                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          20361                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         118662                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       150973                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts               269635                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts              87973235                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              22745315                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts            705719                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                       9499124                       # number of nop insts executed
system.cpu.iew.exec_refs                     38614853                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 15126858                       # Number of branches executed
system.cpu.iew.exec_stores                   15869538                       # Number of stores executed
system.cpu.iew.exec_rate                     1.972795                       # Inst execution rate
system.cpu.iew.wb_sent                       87594856                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                      87192870                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                  33852684                       # num instructions producing a value
system.cpu.iew.wb_consumers                  44279326                       # num instructions consuming a value
system.cpu.iew.wb_rate                       1.955296                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.764526                       # average fanout of values written-back
system.cpu.commit.commitSquashedInsts         8765402                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls            4583                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts            229860                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples     42628268                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     2.072350                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.885151                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0     21157300     49.63%     49.63% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1      6282680     14.74%     64.37% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2      2903206      6.81%     71.18% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3      1743375      4.09%     75.27% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      1680050      3.94%     79.21% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      1128930      2.65%     81.86% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6      1204133      2.82%     84.68% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7       796945      1.87%     86.55% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      5731649     13.45%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total     42628268                       # Number of insts commited each cycle
system.cpu.commit.committedInsts             88340672                       # Number of instructions committed
system.cpu.commit.committedOps               88340672                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       34890015                       # Number of memory references committed
system.cpu.commit.loads                      20276638                       # Number of loads committed
system.cpu.commit.membars                           0                       # Number of memory barriers committed
system.cpu.commit.branches                   13754477                       # Number of branches committed
system.cpu.commit.fp_insts                     267754                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                  77942044                       # Number of committed integer instructions.
system.cpu.commit.function_calls              1661057                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass      8748916      9.90%      9.90% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu         44394798     50.25%     60.16% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult           41101      0.05%     60.20% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv                0      0.00%     60.20% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd         114304      0.13%     60.33% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp             84      0.00%     60.33% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt         113640      0.13%     60.46% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult            50      0.00%     60.46% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv          37764      0.04%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead        20276638     22.95%     83.46% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite       14613377     16.54%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total          88340672                       # Class of committed instruction
system.cpu.commit.bw_lim_events               5731649                       # number cycles where commit BW limit reached
system.cpu.rob.rob_reads                    132685351                       # The number of ROB reads
system.cpu.rob.rob_writes                   195501271                       # The number of ROB writes
system.cpu.timesIdled                           46319                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                          679149                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                    79591756                       # Number of Instructions Simulated
system.cpu.committedOps                      79591756                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               0.560274                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.560274                       # CPI: Total CPI of All Threads
system.cpu.ipc                               1.784841                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         1.784841                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                116453986                       # number of integer regfile reads
system.cpu.int_regfile_writes                57709287                       # number of integer regfile writes
system.cpu.fp_regfile_reads                    255067                       # number of floating regfile reads
system.cpu.fp_regfile_writes                   240450                       # number of floating regfile writes
system.cpu.misc_regfile_reads                   38270                       # number of misc regfile reads
system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
system.cpu.dcache.tags.replacements            201399                       # number of replacements
system.cpu.dcache.tags.tagsinuse          4070.676822                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            33995451                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs            205495                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs            165.432011                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle         229821500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data  4070.676822                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.993818                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.993818                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           76                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1         2778                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2         1242                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses          70838999                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses         70838999                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data     20434147                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        20434147                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     13561246                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       13561246                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data           58                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total           58                       # number of LoadLockedReq hits
system.cpu.dcache.demand_hits::cpu.data      33995393                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         33995393                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     33995393                       # number of overall hits
system.cpu.dcache.overall_hits::total        33995393                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data       269170                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        269170                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      1052131                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      1052131                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data      1321301                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        1321301                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      1321301                       # number of overall misses
system.cpu.dcache.overall_misses::total       1321301                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  17282869000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  17282869000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  89120990413                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  89120990413                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 106403859413                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 106403859413                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 106403859413                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 106403859413                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     20703317                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     20703317                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     14613377                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     14613377                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data           58                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total           58                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     35316694                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     35316694                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     35316694                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     35316694                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.013001                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.013001                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.071998                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.071998                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.037413                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.037413                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.037413                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.037413                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64208.006093                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 64208.006093                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 84705.222461                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 84705.222461                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 80529.613928                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 80529.613928                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 80529.613928                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 80529.613928                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs      6870751                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets          275                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs             89149                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               2                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    77.070421                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets   137.500000                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       168802                       # number of writebacks
system.cpu.dcache.writebacks::total            168802                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       207068                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       207068                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data       908738                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total       908738                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      1115806                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      1115806                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      1115806                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      1115806                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data        62102                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total        62102                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       143393                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       143393                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data       205495                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total       205495                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data       205495                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total       205495                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   3198491500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total   3198491500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  14240616218                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  14240616218                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  17439107718                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  17439107718                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  17439107718                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  17439107718                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.003000                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.003000                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.009812                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.009812                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.005819                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.005819                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.005819                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.005819                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51503.840456                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51503.840456                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 99311.794983                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 99311.794983                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84863.902859                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 84863.902859                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84863.902859                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 84863.902859                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements             91476                       # number of replacements
system.cpu.icache.tags.tagsinuse          1915.700741                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs            13644579                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs             93524                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs            145.893878                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle       18771424500                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst  1915.700741                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.935401                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.935401                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024         2048                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           68                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1           98                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2           25                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3         1477                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4          380                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses          27594820                       # Number of tag accesses
system.cpu.icache.tags.data_accesses         27594820                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst     13644579                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        13644579                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      13644579                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         13644579                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     13644579                       # number of overall hits
system.cpu.icache.overall_hits::total        13644579                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst       106069                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total        106069                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst       106069                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total         106069                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst       106069                       # number of overall misses
system.cpu.icache.overall_misses::total        106069                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst   1942429499                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total   1942429499                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst   1942429499                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total   1942429499                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst   1942429499                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total   1942429499                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     13750648                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     13750648                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     13750648                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     13750648                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     13750648                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     13750648                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.007714                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.007714                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.007714                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.007714                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.007714                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.007714                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18312.885942                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 18312.885942                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 18312.885942                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 18312.885942                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 18312.885942                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 18312.885942                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs         1399                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                14                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    99.928571                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.writebacks::writebacks        91476                       # number of writebacks
system.cpu.icache.writebacks::total             91476                       # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst        12544                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total        12544                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst        12544                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total        12544                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst        12544                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total        12544                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst        93525                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total        93525                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst        93525                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total        93525                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst        93525                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total        93525                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   1588807000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total   1588807000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst   1588807000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total   1588807000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst   1588807000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total   1588807000                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.006801                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.006801                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.006801                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.006801                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.006801                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.006801                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16988.045977                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16988.045977                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16988.045977                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 16988.045977                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16988.045977                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 16988.045977                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements           133079                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        30599.466713                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs             282960                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           165171                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             1.713134                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 26801.500889                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  1873.610433                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data  1924.355391                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.817917                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.057178                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.058727                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.933822                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        32092                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0          235                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1         3119                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2        28323                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3          361                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4           54                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.979370                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses          5043725                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses         5043725                       # Number of data accesses
system.cpu.l2cache.WritebackDirty_hits::writebacks       168802                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total       168802                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks        91476                       # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total        91476                       # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data        12610                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total        12610                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        87118                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total        87118                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data        34241                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total        34241                       # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst        87118                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data        46851                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total          133969                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst        87118                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data        46851                       # number of overall hits
system.cpu.l2cache.overall_hits::total         133969                       # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data       130784                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       130784                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         6407                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total         6407                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data        27860                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total        27860                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst         6407                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       158644                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        165051                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         6407                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       158644                       # number of overall misses
system.cpu.l2cache.overall_misses::total       165051                       # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  13888951000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  13888951000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    529244000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total    529244000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   2740840500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total   2740840500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    529244000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  16629791500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  17159035500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    529244000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  16629791500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  17159035500                       # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks       168802                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total       168802                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks        91476                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total        91476                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       143394                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       143394                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        93525                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total        93525                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data        62101                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total        62101                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst        93525                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data       205495                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total       299020                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst        93525                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data       205495                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total       299020                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.912060                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.912060                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.068506                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.068506                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.448624                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.448624                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.068506                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.772009                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.551973                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.068506                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.772009                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.551973                       # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 106197.631209                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 106197.631209                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82604.026846                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82604.026846                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 98379.055994                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 98379.055994                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82604.026846                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 104824.585235                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 103962.020830                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82604.026846                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 104824.585235                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 103962.020830                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks       114413                       # number of writebacks
system.cpu.l2cache.writebacks::total           114413                       # number of writebacks
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          112                       # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total          112                       # number of CleanEvict MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       130784                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       130784                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         6407                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total         6407                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        27860                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total        27860                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         6407                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       158644                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       165051                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         6407                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       158644                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       165051                       # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  12581111000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  12581111000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    465184000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    465184000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   2462240500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   2462240500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    465184000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  15043351500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  15508535500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    465184000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  15043351500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  15508535500                       # number of overall MSHR miss cycles
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.912060                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.912060                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.068506                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.068506                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.448624                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.448624                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.068506                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.772009                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.551973                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.068506                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.772009                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.551973                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 96197.631209                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 96197.631209                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72605.587639                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72605.587639                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 88379.055994                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 88379.055994                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72605.587639                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 94824.585235                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 93962.081417                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72605.587639                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 94824.585235                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 93962.081417                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.snoop_filter.tot_requests       591895                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests       292875                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops         4047                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops         4047                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp        155625                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty       283215                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean        91476                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict        51263                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       143394                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       143394                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq        93525                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq        62101                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       278525                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       612389                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total            890914                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     11840000                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     23955008                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total           35795008                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                      133079                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples       432099                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        0.009366                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.096323                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0             428052     99.06%     99.06% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1               4047      0.94%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total         432099                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy      556225500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          2.5                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy     140299972                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.6                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy     308258967                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          1.4                       # Layer utilization (%)
system.membus.trans_dist::ReadResp              34266                       # Transaction distribution
system.membus.trans_dist::WritebackDirty       114413                       # Transaction distribution
system.membus.trans_dist::CleanEvict            14730                       # Transaction distribution
system.membus.trans_dist::ReadExReq            130784                       # Transaction distribution
system.membus.trans_dist::ReadExResp           130784                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq         34266                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       459243                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 459243                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     17885632                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                17885632                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoop_fanout::samples            294193                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                  294193    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total              294193                       # Request fanout histogram
system.membus.reqLayer0.occupancy           777045500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               3.5                       # Layer utilization (%)
system.membus.respLayer1.occupancy          852834000                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              3.8                       # Layer utilization (%)

---------- End Simulation Statistics   ----------