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|
---------- Begin Simulation Statistics ----------
sim_seconds 0.024877 # Number of seconds simulated
sim_ticks 24876941500 # Number of ticks simulated
final_tick 24876941500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 202143 # Simulator instruction rate (inst/s)
host_op_rate 202143 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 63181048 # Simulator tick rate (ticks/s)
host_mem_usage 239772 # Number of bytes of host memory used
host_seconds 393.74 # Real time elapsed on the host
sim_insts 79591756 # Number of instructions simulated
sim_ops 79591756 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 490624 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 10154752 # Number of bytes read from this memory
system.physmem.bytes_read::total 10645376 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 490624 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 490624 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 7297216 # Number of bytes written to this memory
system.physmem.bytes_written::total 7297216 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 7666 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 158668 # Number of read requests responded to by this memory
system.physmem.num_reads::total 166334 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 114019 # Number of write requests responded to by this memory
system.physmem.num_writes::total 114019 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 19722039 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 408199376 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 427921415 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 19722039 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 19722039 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 293332522 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 293332522 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 293332522 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 19722039 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 408199376 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 721253937 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 166334 # Number of read requests accepted
system.physmem.writeReqs 114019 # Number of write requests accepted
system.physmem.readBursts 166334 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 114019 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 10645312 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 64 # Total number of bytes read from write queue
system.physmem.bytesWritten 7297024 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 10645376 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 7297216 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 1 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 10436 # Per bank write bursts
system.physmem.perBankRdBursts::1 10466 # Per bank write bursts
system.physmem.perBankRdBursts::2 10310 # Per bank write bursts
system.physmem.perBankRdBursts::3 10058 # Per bank write bursts
system.physmem.perBankRdBursts::4 10431 # Per bank write bursts
system.physmem.perBankRdBursts::5 10410 # Per bank write bursts
system.physmem.perBankRdBursts::6 9846 # Per bank write bursts
system.physmem.perBankRdBursts::7 10323 # Per bank write bursts
system.physmem.perBankRdBursts::8 10612 # Per bank write bursts
system.physmem.perBankRdBursts::9 10641 # Per bank write bursts
system.physmem.perBankRdBursts::10 10552 # Per bank write bursts
system.physmem.perBankRdBursts::11 10231 # Per bank write bursts
system.physmem.perBankRdBursts::12 10282 # Per bank write bursts
system.physmem.perBankRdBursts::13 10619 # Per bank write bursts
system.physmem.perBankRdBursts::14 10489 # Per bank write bursts
system.physmem.perBankRdBursts::15 10627 # Per bank write bursts
system.physmem.perBankWrBursts::0 7083 # Per bank write bursts
system.physmem.perBankWrBursts::1 7258 # Per bank write bursts
system.physmem.perBankWrBursts::2 7255 # Per bank write bursts
system.physmem.perBankWrBursts::3 6998 # Per bank write bursts
system.physmem.perBankWrBursts::4 7126 # Per bank write bursts
system.physmem.perBankWrBursts::5 7177 # Per bank write bursts
system.physmem.perBankWrBursts::6 6771 # Per bank write bursts
system.physmem.perBankWrBursts::7 7092 # Per bank write bursts
system.physmem.perBankWrBursts::8 7228 # Per bank write bursts
system.physmem.perBankWrBursts::9 6941 # Per bank write bursts
system.physmem.perBankWrBursts::10 7087 # Per bank write bursts
system.physmem.perBankWrBursts::11 6989 # Per bank write bursts
system.physmem.perBankWrBursts::12 6966 # Per bank write bursts
system.physmem.perBankWrBursts::13 7287 # Per bank write bursts
system.physmem.perBankWrBursts::14 7286 # Per bank write bursts
system.physmem.perBankWrBursts::15 7472 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 24876907500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 166334 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 114019 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 71615 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 56813 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 31969 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 5926 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 4795 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 4808 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 4807 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 4805 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 4807 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 4811 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 4806 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 4810 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 4806 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 4815 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 4809 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 4814 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 4825 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 4821 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 4848 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 4871 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 4925 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 5346 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 5647 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 5867 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 6542 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 7048 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 962 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 451 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 107 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 49 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 13 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 4 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 52112 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 344.289837 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 164.462354 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 671.053187 # Bytes accessed per row activation
system.physmem.bytesPerActivate::64-65 22533 43.24% 43.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-129 7819 15.00% 58.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192-193 4221 8.10% 66.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-257 3179 6.10% 72.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320-321 2215 4.25% 76.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-385 1656 3.18% 79.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448-449 1349 2.59% 82.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-513 1165 2.24% 84.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576-577 821 1.58% 86.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-641 640 1.23% 87.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704-705 526 1.01% 88.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-769 503 0.97% 89.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832-833 384 0.74% 90.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-897 279 0.54% 90.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960-961 312 0.60% 91.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1025 436 0.84% 92.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088-1089 202 0.39% 92.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152-1153 182 0.35% 92.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216-1217 166 0.32% 93.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280-1281 352 0.68% 93.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344-1345 220 0.42% 94.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408-1409 250 0.48% 94.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472-1473 131 0.25% 95.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536-1537 818 1.57% 96.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600-1601 224 0.43% 97.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664-1665 79 0.15% 97.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728-1729 35 0.07% 97.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1792-1793 217 0.42% 97.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856-1857 119 0.23% 97.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920-1921 48 0.09% 98.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984-1985 34 0.07% 98.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2048-2049 83 0.16% 98.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112-2113 65 0.12% 98.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176-2177 27 0.05% 98.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240-2241 17 0.03% 98.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304-2305 59 0.11% 98.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368-2369 39 0.07% 98.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2432-2433 22 0.04% 98.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496-2497 18 0.03% 98.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2560-2561 32 0.06% 98.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2624-2625 27 0.05% 98.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688-2689 16 0.03% 98.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2752-2753 9 0.02% 98.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816-2817 20 0.04% 98.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880-2881 18 0.03% 98.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2944-2945 13 0.02% 98.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3008-3009 16 0.03% 99.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3072-3073 32 0.06% 99.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3136-3137 16 0.03% 99.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3200-3201 10 0.02% 99.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3264-3265 10 0.02% 99.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3328-3329 12 0.02% 99.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3392-3393 13 0.02% 99.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456-3457 13 0.02% 99.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3520-3521 4 0.01% 99.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3584-3585 12 0.02% 99.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3648-3649 12 0.02% 99.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3712-3713 5 0.01% 99.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3776-3777 5 0.01% 99.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3840-3841 14 0.03% 99.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3904-3905 6 0.01% 99.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3968-3969 9 0.02% 99.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4032-4033 11 0.02% 99.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4096-4097 10 0.02% 99.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4160-4161 10 0.02% 99.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4224-4225 14 0.03% 99.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4288-4289 2 0.00% 99.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4352-4353 3 0.01% 99.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4416-4417 6 0.01% 99.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4480-4481 9 0.02% 99.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4544-4545 6 0.01% 99.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4608-4609 11 0.02% 99.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4672-4673 4 0.01% 99.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4736-4737 4 0.01% 99.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4800-4801 4 0.01% 99.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4864-4865 9 0.02% 99.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4928-4929 5 0.01% 99.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4992-4993 5 0.01% 99.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5056-5057 3 0.01% 99.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5120-5121 6 0.01% 99.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5184-5185 5 0.01% 99.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5248-5249 3 0.01% 99.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5312-5313 4 0.01% 99.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5376-5377 2 0.00% 99.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5440-5441 6 0.01% 99.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5568-5569 3 0.01% 99.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5632-5633 6 0.01% 99.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5696-5697 3 0.01% 99.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5760-5761 3 0.01% 99.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5888-5889 4 0.01% 99.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5952-5953 4 0.01% 99.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6080-6081 6 0.01% 99.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6144-6145 5 0.01% 99.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6208-6209 5 0.01% 99.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6272-6273 1 0.00% 99.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6336-6337 3 0.01% 99.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6400-6401 9 0.02% 99.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6528-6529 1 0.00% 99.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6592-6593 1 0.00% 99.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6656-6657 1 0.00% 99.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6720-6721 6 0.01% 99.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6784-6785 1 0.00% 99.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6848-6849 4 0.01% 99.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6912-6913 4 0.01% 99.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7040-7041 1 0.00% 99.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7104-7105 2 0.00% 99.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7168-7169 10 0.02% 99.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7232-7233 4 0.01% 99.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7296-7297 3 0.01% 99.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7360-7361 1 0.00% 99.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7424-7425 2 0.00% 99.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7488-7489 1 0.00% 99.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7616-7617 1 0.00% 99.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7808-7809 2 0.00% 99.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7936-7937 1 0.00% 99.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8000-8001 2 0.00% 99.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8064-8065 4 0.01% 99.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8128-8129 15 0.03% 99.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8192-8193 82 0.16% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 52112 # Bytes accessed per row activation
system.physmem.totQLat 6294270000 # Total ticks spent queuing
system.physmem.totMemAccLat 8641432500 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 831665000 # Total ticks spent in databus transfers
system.physmem.totBankLat 1515497500 # Total ticks spent accessing banks
system.physmem.avgQLat 37841.38 # Average queueing delay per DRAM burst
system.physmem.avgBankLat 9111.23 # Average bank access latency per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 51952.60 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 427.92 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 293.32 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 427.92 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 293.33 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 5.63 # Data bus utilization in percentage
system.physmem.busUtilRead 3.34 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 2.29 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 0.35 # Average read queue length when enqueuing
system.physmem.avgWrQLen 9.70 # Average write queue length when enqueuing
system.physmem.readRowHits 152220 # Number of row buffer hits during reads
system.physmem.writeRowHits 76017 # Number of row buffer hits during writes
system.physmem.readRowHitRate 91.52 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 66.67 # Row buffer hit rate for writes
system.physmem.avgGap 88734.23 # Average gap between requests
system.physmem.pageHitRate 81.41 # Row buffer hit rate, read and write combined
system.physmem.prechargeAllPercent 11.97 # Percentage of time for which DRAM has all the banks in precharge state
system.membus.throughput 721253937 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 35533 # Transaction distribution
system.membus.trans_dist::ReadResp 35533 # Transaction distribution
system.membus.trans_dist::Writeback 114019 # Transaction distribution
system.membus.trans_dist::ReadExReq 130801 # Transaction distribution
system.membus.trans_dist::ReadExResp 130801 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446687 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 446687 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17942592 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 17942592 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 17942592 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 1242193000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 5.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 1539567000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 6.2 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.branchPred.lookups 16535475 # Number of BP lookups
system.cpu.branchPred.condPredicted 10680150 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 413128 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 11281450 # Number of BTB lookups
system.cpu.branchPred.BTBHits 7332394 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 64.995138 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 1986702 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 41528 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 22396974 # DTB read hits
system.cpu.dtb.read_misses 220986 # DTB read misses
system.cpu.dtb.read_acv 45 # DTB read access violations
system.cpu.dtb.read_accesses 22617960 # DTB read accesses
system.cpu.dtb.write_hits 15703419 # DTB write hits
system.cpu.dtb.write_misses 41132 # DTB write misses
system.cpu.dtb.write_acv 4 # DTB write access violations
system.cpu.dtb.write_accesses 15744551 # DTB write accesses
system.cpu.dtb.data_hits 38100393 # DTB hits
system.cpu.dtb.data_misses 262118 # DTB misses
system.cpu.dtb.data_acv 49 # DTB access violations
system.cpu.dtb.data_accesses 38362511 # DTB accesses
system.cpu.itb.fetch_hits 13901400 # ITB hits
system.cpu.itb.fetch_misses 35038 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 13936438 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4583 # Number of system calls
system.cpu.numCycles 49753887 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles 15785706 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 105319377 # Number of instructions fetch has processed
system.cpu.fetch.Branches 16535475 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 9319096 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 19535939 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 1995771 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 7614067 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 7763 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 310803 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 76 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 13901400 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 208167 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 44703895 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.355933 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.120018 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 25167956 56.30% 56.30% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 1528006 3.42% 59.72% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 1366750 3.06% 62.77% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 1512499 3.38% 66.16% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 4138976 9.26% 75.42% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 1846420 4.13% 79.55% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 671442 1.50% 81.05% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 1071050 2.40% 83.44% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 7400796 16.56% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 44703895 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.332345 # Number of branch fetches per cycle
system.cpu.fetch.rate 2.116807 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 16874554 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 7142634 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 18558802 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 783225 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 1344680 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 3743647 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 107085 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 103596223 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 302671 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 1344680 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 17346175 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 4853031 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 85455 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 18830704 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 2243850 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 102345999 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 509 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 2584 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 2124299 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 61632193 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 123331325 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 123012632 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 318692 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 9085312 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 5523 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 5521 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 4830878 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 23230757 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 16269125 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 1199559 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 452349 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 90724395 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 5268 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 88415459 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 94171 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 10689316 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 4663748 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 685 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 44703895 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.977802 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 2.109542 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 16507369 36.93% 36.93% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 6840922 15.30% 52.23% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 5582133 12.49% 64.72% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 4775843 10.68% 75.40% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 4724672 10.57% 85.97% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 2622986 5.87% 91.84% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 1924028 4.30% 96.14% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 1282580 2.87% 99.01% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 443362 0.99% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 44703895 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 126532 6.78% 6.78% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 6.78% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 6.78% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.78% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.78% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.78% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 6.78% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.78% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.78% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.78% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.78% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.78% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.78% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.78% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.78% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 6.78% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.78% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 6.78% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.78% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.78% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.78% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.78% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.78% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.78% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.78% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.78% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.78% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.78% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.78% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 788261 42.26% 49.04% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 950494 50.96% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 49348241 55.81% 55.81% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 43886 0.05% 55.86% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.86% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 121319 0.14% 56.00% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 88 0.00% 56.00% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 121135 0.14% 56.14% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 57 0.00% 56.14% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 38977 0.04% 56.18% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.18% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 22847876 25.84% 82.02% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 15893880 17.98% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 88415459 # Type of FU issued
system.cpu.iq.rate 1.777056 # Inst issue rate
system.cpu.iq.fu_busy_cnt 1865287 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.021097 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 222890546 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 101022608 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 86533727 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 603725 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 414375 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 294393 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 89978801 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 301945 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 1469946 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 2954119 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 4771 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 18244 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 1655748 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 3011 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 95424 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 1344680 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 3730457 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 74850 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 100207935 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 218697 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 23230757 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 16269125 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 5268 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 49823 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 6563 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 18244 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 192844 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 159688 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 352532 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 87575579 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 22621211 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 839880 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 9478272 # number of nop insts executed
system.cpu.iew.exec_refs 38366084 # number of memory reference insts executed
system.cpu.iew.exec_branches 15081989 # Number of branches executed
system.cpu.iew.exec_stores 15744873 # Number of stores executed
system.cpu.iew.exec_rate 1.760176 # Inst execution rate
system.cpu.iew.wb_sent 87218892 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 86828120 # cumulative count of insts written-back
system.cpu.iew.wb_producers 33348545 # num instructions producing a value
system.cpu.iew.wb_consumers 43472168 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.745152 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.767124 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts 8870802 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 308267 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 43359215 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 2.037414 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.791048 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 20533772 47.36% 47.36% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 7032064 16.22% 63.58% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 3351851 7.73% 71.31% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 2056930 4.74% 76.05% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 2048633 4.72% 80.77% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 1170984 2.70% 83.48% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 1108500 2.56% 86.03% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 718184 1.66% 87.69% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 5338297 12.31% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 43359215 # Number of insts commited each cycle
system.cpu.commit.committedInsts 88340672 # Number of instructions committed
system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 34890015 # Number of memory references committed
system.cpu.commit.loads 20276638 # Number of loads committed
system.cpu.commit.membars 0 # Number of memory barriers committed
system.cpu.commit.branches 13754477 # Number of branches committed
system.cpu.commit.fp_insts 267754 # Number of committed floating point instructions.
system.cpu.commit.int_insts 77942044 # Number of committed integer instructions.
system.cpu.commit.function_calls 1661057 # Number of function calls committed.
system.cpu.commit.bw_lim_events 5338297 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 133915050 # The number of ROB reads
system.cpu.rob.rob_writes 195770285 # The number of ROB writes
system.cpu.timesIdled 83590 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 5049992 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 79591756 # Number of Instructions Simulated
system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated
system.cpu.cpi 0.625114 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.625114 # CPI: Total CPI of All Threads
system.cpu.ipc 1.599709 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.599709 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 115901393 # number of integer regfile reads
system.cpu.int_regfile_writes 57502981 # number of integer regfile writes
system.cpu.fp_regfile_reads 249622 # number of floating regfile reads
system.cpu.fp_regfile_writes 240154 # number of floating regfile writes
system.cpu.misc_regfile_reads 38048 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
system.cpu.toL2Bus.throughput 1204366702 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 155800 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 155799 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 168930 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 143411 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 143411 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 187341 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 580010 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 767351 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5994880 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23966080 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total 29960960 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus 29960960 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 403000500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.6 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 141888472 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.6 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 326227248 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%)
system.cpu.icache.tags.replacements 91622 # number of replacements
system.cpu.icache.tags.tagsinuse 1926.124790 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 13794941 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 93670 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 147.271709 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 20019697250 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 1926.124790 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.940491 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.940491 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 91 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 1531 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 359 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 27896466 # Number of tag accesses
system.cpu.icache.tags.data_accesses 27896466 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 13794941 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 13794941 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 13794941 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 13794941 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 13794941 # number of overall hits
system.cpu.icache.overall_hits::total 13794941 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 106457 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 106457 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 106457 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 106457 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 106457 # number of overall misses
system.cpu.icache.overall_misses::total 106457 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 2019960968 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 2019960968 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 2019960968 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 2019960968 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 2019960968 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 2019960968 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 13901398 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 13901398 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 13901398 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 13901398 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 13901398 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 13901398 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007658 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.007658 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.007658 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.007658 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.007658 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.007658 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18974.430690 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 18974.430690 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 18974.430690 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 18974.430690 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 18974.430690 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 18974.430690 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 691 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 16 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs 43.187500 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 12786 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 12786 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 12786 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 12786 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 12786 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 12786 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 93671 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 93671 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 93671 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 93671 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 93671 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 93671 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1551735028 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 1551735028 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1551735028 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 1551735028 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1551735028 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 1551735028 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006738 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006738 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006738 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.006738 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006738 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.006738 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16565.799746 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16565.799746 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16565.799746 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 16565.799746 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16565.799746 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 16565.799746 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 132428 # number of replacements
system.cpu.l2cache.tags.tagsinuse 30694.665852 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 159970 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 164497 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.972480 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 26341.005950 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2105.517354 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 2248.142548 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.803864 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.064255 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.068608 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.936727 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32069 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 167 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1443 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 18046 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12352 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 61 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978668 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 4053036 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 4053036 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst 86004 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 34262 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 120266 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 168930 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 168930 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 12610 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 12610 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 86004 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 46872 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 132876 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 86004 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 46872 # number of overall hits
system.cpu.l2cache.overall_hits::total 132876 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 7667 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 27867 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 35534 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 130801 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 130801 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 7667 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 158668 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 166335 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 7667 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 158668 # number of overall misses
system.cpu.l2cache.overall_misses::total 166335 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 597389250 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2119099250 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 2716488500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 13782092500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 13782092500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 597389250 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 15901191750 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 16498581000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 597389250 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 15901191750 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 16498581000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 93671 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 62129 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 155800 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 168930 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 168930 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 143411 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 143411 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 93671 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 205540 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 299211 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 93671 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 205540 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 299211 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.081850 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.448535 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.228074 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.912071 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.912071 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.081850 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.771957 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.555912 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.081850 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.771957 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.555912 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77916.949263 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76043.321850 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 76447.585411 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 105366.874106 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 105366.874106 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77916.949263 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 100216.752905 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 99188.871855 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77916.949263 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 100216.752905 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 99188.871855 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 114019 # number of writebacks
system.cpu.l2cache.writebacks::total 114019 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 7667 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27867 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 35534 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130801 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 130801 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 7667 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 158668 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 166335 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 7667 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 158668 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 166335 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 500389250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1762290750 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2262680000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 12178041500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12178041500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 500389250 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 13940332250 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 14440721500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 500389250 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 13940332250 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 14440721500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.081850 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.448535 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.228074 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.912071 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.912071 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.081850 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771957 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.555912 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.081850 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771957 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.555912 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65265.325421 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63239.342233 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63676.478865 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 93103.581012 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 93103.581012 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65265.325421 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 87858.498563 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 86817.095019 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65265.325421 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 87858.498563 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86817.095019 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements 201444 # number of replacements
system.cpu.dcache.tags.tagsinuse 4074.011744 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 34183901 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 205540 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 166.312645 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 220306250 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 4074.011744 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.994632 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.994632 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 1078 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2940 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 71186914 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 71186914 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 20609776 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 20609776 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 13574069 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 13574069 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 56 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 56 # number of LoadLockedReq hits
system.cpu.dcache.demand_hits::cpu.data 34183845 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 34183845 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 34183845 # number of overall hits
system.cpu.dcache.overall_hits::total 34183845 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 267478 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 267478 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1039308 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 1039308 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 1306786 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 1306786 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 1306786 # number of overall misses
system.cpu.dcache.overall_misses::total 1306786 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 16319754498 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 16319754498 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 88798095012 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 88798095012 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 105117849510 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 105117849510 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 105117849510 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 105117849510 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 20877254 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 20877254 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 56 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 56 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 35490631 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 35490631 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 35490631 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 35490631 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012812 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.012812 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071120 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.071120 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.036821 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.036821 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.036821 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.036821 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61013.445958 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 61013.445958 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 85439.633883 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 85439.633883 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 80439.987504 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 80439.987504 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 80439.987504 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 80439.987504 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 5138864 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 131 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 112181 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 45.808684 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 131 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 168930 # number of writebacks
system.cpu.dcache.writebacks::total 168930 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 205345 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 205345 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895901 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 895901 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 1101246 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 1101246 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 1101246 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 1101246 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62133 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 62133 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143407 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 143407 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 205540 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 205540 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 205540 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 205540 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2525887252 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2525887252 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14052510994 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 14052510994 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16578398246 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 16578398246 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16578398246 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 16578398246 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002976 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002976 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009813 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009813 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005791 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.005791 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005791 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.005791 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40652.909919 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40652.909919 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 97990.411863 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 97990.411863 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80657.770974 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 80657.770974 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80657.770974 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 80657.770974 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
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