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|
---------- Begin Simulation Statistics ----------
sim_seconds 0.022282 # Number of seconds simulated
sim_ticks 22281815500 # Number of ticks simulated
final_tick 22281815500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 227860 # Simulator instruction rate (inst/s)
host_op_rate 227860 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 63789654 # Simulator tick rate (ticks/s)
host_mem_usage 305428 # Number of bytes of host memory used
host_seconds 349.30 # Real time elapsed on the host
sim_insts 79591756 # Number of instructions simulated
sim_ops 79591756 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 487168 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 10151488 # Number of bytes read from this memory
system.physmem.bytes_read::total 10638656 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 487168 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 487168 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 7296384 # Number of bytes written to this memory
system.physmem.bytes_written::total 7296384 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 7612 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 158617 # Number of read requests responded to by this memory
system.physmem.num_reads::total 166229 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 114006 # Number of write requests responded to by this memory
system.physmem.num_writes::total 114006 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 21863928 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 455595192 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 477459119 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 21863928 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 21863928 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 327459134 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 327459134 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 327459134 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 21863928 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 455595192 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 804918253 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 166229 # Number of read requests accepted
system.physmem.writeReqs 114006 # Number of write requests accepted
system.physmem.readBursts 166229 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 114006 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 10638144 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 512 # Total number of bytes read from write queue
system.physmem.bytesWritten 7294656 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 10638656 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 7296384 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 8 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 10438 # Per bank write bursts
system.physmem.perBankRdBursts::1 10454 # Per bank write bursts
system.physmem.perBankRdBursts::2 10317 # Per bank write bursts
system.physmem.perBankRdBursts::3 10059 # Per bank write bursts
system.physmem.perBankRdBursts::4 10417 # Per bank write bursts
system.physmem.perBankRdBursts::5 10393 # Per bank write bursts
system.physmem.perBankRdBursts::6 9837 # Per bank write bursts
system.physmem.perBankRdBursts::7 10310 # Per bank write bursts
system.physmem.perBankRdBursts::8 10606 # Per bank write bursts
system.physmem.perBankRdBursts::9 10643 # Per bank write bursts
system.physmem.perBankRdBursts::10 10543 # Per bank write bursts
system.physmem.perBankRdBursts::11 10224 # Per bank write bursts
system.physmem.perBankRdBursts::12 10268 # Per bank write bursts
system.physmem.perBankRdBursts::13 10616 # Per bank write bursts
system.physmem.perBankRdBursts::14 10478 # Per bank write bursts
system.physmem.perBankRdBursts::15 10618 # Per bank write bursts
system.physmem.perBankWrBursts::0 7083 # Per bank write bursts
system.physmem.perBankWrBursts::1 7253 # Per bank write bursts
system.physmem.perBankWrBursts::2 7255 # Per bank write bursts
system.physmem.perBankWrBursts::3 6997 # Per bank write bursts
system.physmem.perBankWrBursts::4 7126 # Per bank write bursts
system.physmem.perBankWrBursts::5 7169 # Per bank write bursts
system.physmem.perBankWrBursts::6 6770 # Per bank write bursts
system.physmem.perBankWrBursts::7 7085 # Per bank write bursts
system.physmem.perBankWrBursts::8 7220 # Per bank write bursts
system.physmem.perBankWrBursts::9 6943 # Per bank write bursts
system.physmem.perBankWrBursts::10 7084 # Per bank write bursts
system.physmem.perBankWrBursts::11 6988 # Per bank write bursts
system.physmem.perBankWrBursts::12 6964 # Per bank write bursts
system.physmem.perBankWrBursts::13 7287 # Per bank write bursts
system.physmem.perBankWrBursts::14 7283 # Per bank write bursts
system.physmem.perBankWrBursts::15 7472 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 22281781500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 166229 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 114006 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 51659 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 54099 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 45462 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 14988 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 831 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 866 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 1404 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 2462 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 4500 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 5890 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 6399 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 6743 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 7087 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 7519 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 7911 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 8284 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 8943 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 9706 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 8638 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 8945 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 8834 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 8038 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 434 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 257 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 169 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 99 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 29 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 3 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 52189 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 343.580755 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 201.430431 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 344.457165 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 18353 35.17% 35.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 10742 20.58% 55.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 5641 10.81% 66.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 3092 5.92% 72.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 2629 5.04% 77.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1694 3.25% 80.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 1790 3.43% 84.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 1288 2.47% 86.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 6960 13.34% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 52189 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 6966 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 23.861757 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 342.246517 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023 6964 99.97% 99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::27648-28671 1 0.01% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 6966 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 6965 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 16.363676 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 16.332802 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 1.079402 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16 6068 87.12% 87.12% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17 30 0.43% 87.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18 495 7.11% 94.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19 185 2.66% 97.32% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20 91 1.31% 98.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21 46 0.66% 99.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22 21 0.30% 99.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23 10 0.14% 99.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24 10 0.14% 99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::25 5 0.07% 99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26 1 0.01% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::27 3 0.04% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 6965 # Writes before turning the bus around for reads
system.physmem.totQLat 5436579750 # Total ticks spent queuing
system.physmem.totMemAccLat 8553223500 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 831105000 # Total ticks spent in databus transfers
system.physmem.avgQLat 32706.94 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 51456.94 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 477.44 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 327.38 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 477.46 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 327.46 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 6.29 # Data bus utilization in percentage
system.physmem.busUtilRead 3.73 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 2.56 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.80 # Average read queue length when enqueuing
system.physmem.avgWrQLen 24.31 # Average write queue length when enqueuing
system.physmem.readRowHits 146012 # Number of row buffer hits during reads
system.physmem.writeRowHits 81986 # Number of row buffer hits during writes
system.physmem.readRowHitRate 87.84 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 71.91 # Row buffer hit rate for writes
system.physmem.avgGap 79511.06 # Average gap between requests
system.physmem.pageHitRate 81.36 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 190496880 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 103941750 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 641043000 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 367539120 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 1454990160 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 6553751985 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 7617131250 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 16928894145 # Total energy per rank (pJ)
system.physmem_0.averagePower 759.936312 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 12590169250 # Time in different power states
system.physmem_0.memoryStateTime::REF 743860000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 8942711000 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 203779800 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 111189375 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 654919200 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 370694880 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 1454990160 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 6762785805 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 7433764500 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 16992123720 # Total energy per rank (pJ)
system.physmem_1.averagePower 762.774895 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 12284853000 # Time in different power states
system.physmem_1.memoryStateTime::REF 743860000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 9248437000 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.branchPred.lookups 16624924 # Number of BP lookups
system.cpu.branchPred.condPredicted 10755300 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 362268 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 10924107 # Number of BTB lookups
system.cpu.branchPred.BTBHits 7374828 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 67.509665 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 1991560 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 2903 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 22639897 # DTB read hits
system.cpu.dtb.read_misses 226363 # DTB read misses
system.cpu.dtb.read_acv 23 # DTB read access violations
system.cpu.dtb.read_accesses 22866260 # DTB read accesses
system.cpu.dtb.write_hits 15870343 # DTB write hits
system.cpu.dtb.write_misses 44837 # DTB write misses
system.cpu.dtb.write_acv 1 # DTB write access violations
system.cpu.dtb.write_accesses 15915180 # DTB write accesses
system.cpu.dtb.data_hits 38510240 # DTB hits
system.cpu.dtb.data_misses 271200 # DTB misses
system.cpu.dtb.data_acv 24 # DTB access violations
system.cpu.dtb.data_accesses 38781440 # DTB accesses
system.cpu.itb.fetch_hits 13919462 # ITB hits
system.cpu.itb.fetch_misses 31654 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 13951116 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4583 # Number of system calls
system.cpu.numCycles 44563634 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles 15791560 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 106158478 # Number of instructions fetch has processed
system.cpu.fetch.Branches 16624924 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 9366388 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 27217966 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 963396 # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles 137 # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.MiscStallCycles 4946 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 337279 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 111 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 13919462 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 206375 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples 43833697 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.421846 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.133787 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 24095007 54.97% 54.97% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 1538131 3.51% 58.48% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 1406372 3.21% 61.69% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 1524721 3.48% 65.17% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 4235690 9.66% 74.83% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 1846144 4.21% 79.04% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 685371 1.56% 80.60% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 1070354 2.44% 83.05% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 7431907 16.95% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 43833697 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.373060 # Number of branch fetches per cycle
system.cpu.fetch.rate 2.382177 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 15105656 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 9282610 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 18470395 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 592044 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 382992 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 3741910 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 100605 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 104048931 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 315835 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 382992 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 15490766 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 6387964 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 95966 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 18655378 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 2820631 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 102900646 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 4493 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 152365 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 320462 # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents 2296242 # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands 61929819 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 124171537 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 123841536 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 330000 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 9382938 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 5791 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 5849 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 2464589 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 23265416 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 16459353 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 1262626 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 544604 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 91320451 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 5681 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 89124415 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 80151 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 11242959 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 4725710 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 1098 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 43833697 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 2.033240 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 2.247678 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 17209661 39.26% 39.26% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 5800175 13.23% 52.49% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 5098270 11.63% 64.12% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 4410681 10.06% 74.19% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 4347575 9.92% 84.11% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 2649961 6.05% 90.15% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 1950790 4.45% 94.60% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 1381860 3.15% 97.75% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 984724 2.25% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 43833697 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 244354 9.65% 9.65% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 9.65% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 9.65% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.65% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.65% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.65% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 9.65% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.65% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.65% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.65% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.65% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.65% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.65% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.65% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.65% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 9.65% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.65% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 9.65% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.65% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.65% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.65% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.65% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.65% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.65% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.65% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.65% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.65% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.65% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.65% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 1175209 46.41% 56.06% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 1112799 43.94% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 49663354 55.72% 55.72% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 44187 0.05% 55.77% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.77% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 122171 0.14% 55.91% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 88 0.00% 55.91% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 121874 0.14% 56.05% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 57 0.00% 56.05% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 39065 0.04% 56.09% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.09% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 23057459 25.87% 81.96% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 16076160 18.04% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 89124415 # Type of FU issued
system.cpu.iq.rate 1.999936 # Inst issue rate
system.cpu.iq.fu_busy_cnt 2532362 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.028414 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 224079080 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 102152200 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 87178162 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 615960 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 437940 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 301333 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 91348643 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 308134 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 1658507 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 2988778 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 6943 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 21591 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 1845976 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 3051 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 325532 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 382992 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 1216204 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 4841557 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 100851766 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 147146 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 23265416 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 16459353 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 5598 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 3356 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 4819285 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 21591 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 151679 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 156559 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 308238 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 88344034 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 22866899 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 780381 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 9525634 # number of nop insts executed
system.cpu.iew.exec_refs 38782381 # number of memory reference insts executed
system.cpu.iew.exec_branches 15172546 # Number of branches executed
system.cpu.iew.exec_stores 15915482 # Number of stores executed
system.cpu.iew.exec_rate 1.982424 # Inst execution rate
system.cpu.iew.wb_sent 87895909 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 87479495 # cumulative count of insts written-back
system.cpu.iew.wb_producers 33899568 # num instructions producing a value
system.cpu.iew.wb_consumers 44349597 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.963024 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.764372 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts 9308985 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 263562 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 42463328 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 2.080399 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.884681 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 20917493 49.26% 49.26% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 6333939 14.92% 64.18% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 2944595 6.93% 71.11% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 1757333 4.14% 75.25% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 1653620 3.89% 79.14% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 1138333 2.68% 81.82% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 1205391 2.84% 84.66% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 793939 1.87% 86.53% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 5718685 13.47% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 42463328 # Number of insts commited each cycle
system.cpu.commit.committedInsts 88340672 # Number of instructions committed
system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 34890015 # Number of memory references committed
system.cpu.commit.loads 20276638 # Number of loads committed
system.cpu.commit.membars 0 # Number of memory barriers committed
system.cpu.commit.branches 13754477 # Number of branches committed
system.cpu.commit.fp_insts 267754 # Number of committed floating point instructions.
system.cpu.commit.int_insts 77942044 # Number of committed integer instructions.
system.cpu.commit.function_calls 1661057 # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass 8748916 9.90% 9.90% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu 44394798 50.25% 60.16% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult 41101 0.05% 60.20% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 0 0.00% 60.20% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 114304 0.13% 60.33% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 84 0.00% 60.33% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 113640 0.13% 60.46% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 50 0.00% 60.46% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 37764 0.04% 60.51% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 60.51% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead 20276638 22.95% 83.46% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 14613377 16.54% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 88340672 # Class of committed instruction
system.cpu.commit.bw_lim_events 5718685 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 133076958 # The number of ROB reads
system.cpu.rob.rob_writes 196673244 # The number of ROB writes
system.cpu.timesIdled 48172 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 729937 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 79591756 # Number of Instructions Simulated
system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated
system.cpu.cpi 0.559903 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.559903 # CPI: Total CPI of All Threads
system.cpu.ipc 1.786025 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.786025 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 116925772 # number of integer regfile reads
system.cpu.int_regfile_writes 57936362 # number of integer regfile writes
system.cpu.fp_regfile_reads 255891 # number of floating regfile reads
system.cpu.fp_regfile_writes 241873 # number of floating regfile writes
system.cpu.misc_regfile_reads 38152 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
system.cpu.dcache.tags.replacements 201381 # number of replacements
system.cpu.dcache.tags.tagsinuse 4071.852002 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 34090259 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 205477 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 165.907907 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 215961000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 4071.852002 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.994104 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.994104 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 77 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 2773 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 1246 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 71020605 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 71020605 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 20525911 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 20525911 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 13564288 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 13564288 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 60 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 60 # number of LoadLockedReq hits
system.cpu.dcache.demand_hits::cpu.data 34090199 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 34090199 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 34090199 # number of overall hits
system.cpu.dcache.overall_hits::total 34090199 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 268215 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 268215 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1049089 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 1049089 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 1317304 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 1317304 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 1317304 # number of overall misses
system.cpu.dcache.overall_misses::total 1317304 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 16911598996 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 16911598996 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 85714857886 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 85714857886 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 92750 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 92750 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 102626456882 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 102626456882 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 102626456882 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 102626456882 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 20794126 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 20794126 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 35407503 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 35407503 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 35407503 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 35407503 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012899 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.012899 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071790 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.071790 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.016393 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.016393 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.037204 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.037204 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.037204 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.037204 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63052.398248 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 63052.398248 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 81704.086008 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 81704.086008 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 92750 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 92750 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 77906.433809 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 77906.433809 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 77906.433809 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 77906.433809 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 6293239 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 254 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 146230 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 43.036579 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 127 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 168920 # number of writebacks
system.cpu.dcache.writebacks::total 168920 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 206147 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 206147 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 905681 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 905681 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 1111828 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 1111828 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 1111828 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 1111828 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62068 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 62068 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143408 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 143408 # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 205476 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 205476 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 205476 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 205476 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3016288253 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 3016288253 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13368781676 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 13368781676 # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 90250 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 90250 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16385069929 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 16385069929 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16385069929 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 16385069929 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002985 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002985 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009813 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009813 # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.016393 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.016393 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005803 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.005803 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005803 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.005803 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48596.511133 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48596.511133 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 93222.007670 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 93222.007670 # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 90250 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 90250 # average LoadLockedReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 79742.013320 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 79742.013320 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 79742.013320 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 79742.013320 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 93674 # number of replacements
system.cpu.icache.tags.tagsinuse 1918.313943 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 13810732 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 95722 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 144.279601 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 18796346250 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 1918.313943 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.936677 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.936677 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 82 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 1489 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 370 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 27934642 # Number of tag accesses
system.cpu.icache.tags.data_accesses 27934642 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 13810732 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 13810732 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 13810732 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 13810732 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 13810732 # number of overall hits
system.cpu.icache.overall_hits::total 13810732 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 108728 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 108728 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 108728 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 108728 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 108728 # number of overall misses
system.cpu.icache.overall_misses::total 108728 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 2006428959 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 2006428959 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 2006428959 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 2006428959 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 2006428959 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 2006428959 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 13919460 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 13919460 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 13919460 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 13919460 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 13919460 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 13919460 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007811 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.007811 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.007811 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.007811 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.007811 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.007811 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18453.654615 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 18453.654615 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 18453.654615 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 18453.654615 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 18453.654615 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 18453.654615 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 1061 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 16 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs 66.312500 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 13005 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 13005 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 13005 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 13005 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 13005 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 13005 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 95723 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 95723 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 95723 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 95723 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 95723 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 95723 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1546277535 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 1546277535 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1546277535 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 1546277535 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1546277535 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 1546277535 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006877 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006877 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006877 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.006877 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006877 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.006877 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16153.667718 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16153.667718 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16153.667718 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 16153.667718 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16153.667718 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 16153.667718 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 132323 # number of replacements
system.cpu.l2cache.tags.tagsinuse 30650.354019 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 162059 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 164389 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.985826 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 26718.517593 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2110.418463 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 1821.417963 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.815384 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.064405 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.055585 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.935375 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32066 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 183 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3005 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 28611 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 209 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 58 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978577 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 4068759 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 4068759 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst 88110 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 34237 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 122347 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 168920 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 168920 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 12623 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 12623 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 88110 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 46860 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 134970 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 88110 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 46860 # number of overall hits
system.cpu.l2cache.overall_hits::total 134970 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 7613 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 27830 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 35443 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 130787 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 130787 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 7613 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 158617 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 166230 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 7613 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 158617 # number of overall misses
system.cpu.l2cache.overall_misses::total 166230 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 568819250 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2608707000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 3177526250 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 13094816500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 13094816500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 568819250 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 15703523500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 16272342750 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 568819250 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 15703523500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 16272342750 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 95723 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 62067 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 157790 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 168920 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 168920 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 143410 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 143410 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 95723 # number of demand (read+write) accesses
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system.cpu.l2cache.overall_accesses::total 301200 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.079532 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.448386 # miss rate for ReadReq accesses
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system.cpu.l2cache.ReadExReq_miss_rate::total 0.911980 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.079532 # miss rate for demand accesses
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system.cpu.l2cache.overall_miss_rate::cpu.inst 0.079532 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.771945 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.551892 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74716.833049 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 93737.226015 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 89651.729538 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 100123.227079 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 100123.227079 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74716.833049 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 99002.777130 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 97890.529688 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74716.833049 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 99002.777130 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 97890.529688 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 114006 # number of writebacks
system.cpu.l2cache.writebacks::total 114006 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 7613 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27830 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 35443 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130787 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 130787 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 7613 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 158617 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 166230 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 7613 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 158617 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 166230 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 472609250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2266008500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2738617750 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 11494650500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 11494650500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 472609250 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 13760659000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 14233268250 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 472609250 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 13760659000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 14233268250 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.079532 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.448386 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.224621 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911980 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911980 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.079532 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771945 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.551892 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.079532 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771945 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.551892 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62079.239459 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 81423.230327 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 77268.226448 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 87888.326057 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 87888.326057 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62079.239459 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 86753.998626 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 85623.944234 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62079.239459 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 86753.998626 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 85623.944234 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq 157790 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 157789 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 168920 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 143410 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 143410 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 191445 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 579874 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 771319 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6126208 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23961408 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 30087616 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 470120 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 470120 100.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 470120 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 403980000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.8 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 144944965 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.7 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 321950247 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%)
system.membus.trans_dist::ReadReq 35442 # Transaction distribution
system.membus.trans_dist::ReadResp 35442 # Transaction distribution
system.membus.trans_dist::Writeback 114006 # Transaction distribution
system.membus.trans_dist::ReadExReq 130787 # Transaction distribution
system.membus.trans_dist::ReadExResp 130787 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446464 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 446464 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17935040 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 17935040 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 280235 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 280235 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 280235 # Request fanout histogram
system.membus.reqLayer0.occupancy 1235714000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 5.5 # Layer utilization (%)
system.membus.respLayer1.occupancy 1525262750 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 6.8 # Layer utilization (%)
---------- End Simulation Statistics ----------
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