path: root/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.022578                       # Number of seconds simulated
sim_ticks                                 22578120000                       # Number of ticks simulated
final_tick                                22578120000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 210348                       # Simulator instruction rate (inst/s)
host_op_rate                                   210348                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               59670380                       # Simulator tick rate (ticks/s)
host_mem_usage                                 234940                       # Number of bytes of host memory used
host_seconds                                   378.38                       # Real time elapsed on the host
sim_insts                                    79591756                       # Number of instructions simulated
sim_ops                                      79591756                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst            487616                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          10151104                       # Number of bytes read from this memory
system.physmem.bytes_read::total             10638720                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       487616                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          487616                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      7296832                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7296832                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst               7619                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             158611                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                166230                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          114013                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               114013                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst             21596838                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data            449599169                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total               471196007                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst        21596838                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total           21596838                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks         323181558                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total              323181558                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks         323181558                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst            21596838                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data           449599169                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              794377566                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        166230                       # Number of read requests accepted
system.physmem.writeReqs                       114013                       # Number of write requests accepted
system.physmem.readBursts                      166230                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     114013                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 10638144                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                       576                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   7294912                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  10638720                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                7296832                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                        9                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               10435                       # Per bank write bursts
system.physmem.perBankRdBursts::1               10460                       # Per bank write bursts
system.physmem.perBankRdBursts::2               10318                       # Per bank write bursts
system.physmem.perBankRdBursts::3               10058                       # Per bank write bursts
system.physmem.perBankRdBursts::4               10413                       # Per bank write bursts
system.physmem.perBankRdBursts::5               10396                       # Per bank write bursts
system.physmem.perBankRdBursts::6                9837                       # Per bank write bursts
system.physmem.perBankRdBursts::7               10308                       # Per bank write bursts
system.physmem.perBankRdBursts::8               10587                       # Per bank write bursts
system.physmem.perBankRdBursts::9               10644                       # Per bank write bursts
system.physmem.perBankRdBursts::10              10547                       # Per bank write bursts
system.physmem.perBankRdBursts::11              10228                       # Per bank write bursts
system.physmem.perBankRdBursts::12              10270                       # Per bank write bursts
system.physmem.perBankRdBursts::13              10618                       # Per bank write bursts
system.physmem.perBankRdBursts::14              10481                       # Per bank write bursts
system.physmem.perBankRdBursts::15              10621                       # Per bank write bursts
system.physmem.perBankWrBursts::0                7083                       # Per bank write bursts
system.physmem.perBankWrBursts::1                7259                       # Per bank write bursts
system.physmem.perBankWrBursts::2                7255                       # Per bank write bursts
system.physmem.perBankWrBursts::3                6997                       # Per bank write bursts
system.physmem.perBankWrBursts::4                7126                       # Per bank write bursts
system.physmem.perBankWrBursts::5                7171                       # Per bank write bursts
system.physmem.perBankWrBursts::6                6772                       # Per bank write bursts
system.physmem.perBankWrBursts::7                7083                       # Per bank write bursts
system.physmem.perBankWrBursts::8                7219                       # Per bank write bursts
system.physmem.perBankWrBursts::9                6939                       # Per bank write bursts
system.physmem.perBankWrBursts::10               7083                       # Per bank write bursts
system.physmem.perBankWrBursts::11               6988                       # Per bank write bursts
system.physmem.perBankWrBursts::12               6964                       # Per bank write bursts
system.physmem.perBankWrBursts::13               7288                       # Per bank write bursts
system.physmem.perBankWrBursts::14               7284                       # Per bank write bursts
system.physmem.perBankWrBursts::15               7472                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                     22578086500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  166230                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 114013                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                     52462                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     43160                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     38431                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                     32153                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                        12                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                      784                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                      809                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     2168                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     3478                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     4829                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6154                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     6617                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     6971                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     7123                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     7222                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     7425                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     7835                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     7650                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     8007                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    10134                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     8246                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     9963                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     7925                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      349                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      161                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                       84                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                       35                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                       16                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        7                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        3                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        52260                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      343.127440                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     201.641716                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     343.309325                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          18423     35.25%     35.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        10477     20.05%     55.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         5934     11.35%     66.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         2978      5.70%     72.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2855      5.46%     77.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1509      2.89%     80.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         2072      3.96%     84.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023          924      1.77%     86.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         7088     13.56%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          52260                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          6982                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        23.804927                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      342.249057                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023           6981     99.99%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::27648-28671            1      0.01%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            6982                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          6982                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        16.325265                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       16.299310                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        0.979398                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16               6150     88.08%     88.08% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17                 25      0.36%     88.44% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18                468      6.70%     95.14% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19                181      2.59%     97.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20                 78      1.12%     98.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21                 46      0.66%     99.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22                 19      0.27%     99.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23                 10      0.14%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24                  4      0.06%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::25                  1      0.01%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            6982                       # Writes before turning the bus around for reads
system.physmem.totQLat                     5742111500                       # Total ticks spent queuing
system.physmem.totMemAccLat                8858755250                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    831105000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       34545.04                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  53295.04                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                         471.17                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                         323.10                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                      471.20                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                      323.18                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           6.21                       # Data bus utilization in percentage
system.physmem.busUtilRead                       3.68                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      2.52                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.91                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        24.41                       # Average write queue length when enqueuing
system.physmem.readRowHits                     146222                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     81709                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   87.97                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  71.67                       # Row buffer hit rate for writes
system.physmem.avgGap                        80566.10                       # Average gap between requests
system.physmem.pageHitRate                      81.34                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  190685880                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  104044875                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 641035200                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                367584480                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy             1474315440                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy             6555814245                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy             7792863750                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy              17126343870                       # Total energy per rank (pJ)
system.physmem_0.averagePower              758.721685                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE    12883309000                       # Time in different power states
system.physmem_0.memoryStateTime::REF       753740000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT      8935594000                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  204104880                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  111366750                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 654919200                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                370701360                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy             1474315440                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy             6889050495                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy             7500532500                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy              17204990625                       # Total energy per rank (pJ)
system.physmem_1.averagePower              762.206905                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE    12395641000                       # Time in different power states
system.physmem_1.memoryStateTime::REF       753740000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT      9423231500                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu.branchPred.lookups                16619938                       # Number of BP lookups
system.cpu.branchPred.condPredicted          10751763                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect            361573                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             10694449                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                 7373128                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             68.943505                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 1990233                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect               3119                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dtb.fetch_hits                           0                       # ITB hits
system.cpu.dtb.fetch_misses                         0                       # ITB misses
system.cpu.dtb.fetch_acv                            0                       # ITB acv
system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
system.cpu.dtb.read_hits                     22587975                       # DTB read hits
system.cpu.dtb.read_misses                     226213                       # DTB read misses
system.cpu.dtb.read_acv                            17                       # DTB read access violations
system.cpu.dtb.read_accesses                 22814188                       # DTB read accesses
system.cpu.dtb.write_hits                    15866557                       # DTB write hits
system.cpu.dtb.write_misses                     44947                       # DTB write misses
system.cpu.dtb.write_acv                            1                       # DTB write access violations
system.cpu.dtb.write_accesses                15911504                       # DTB write accesses
system.cpu.dtb.data_hits                     38454532                       # DTB hits
system.cpu.dtb.data_misses                     271160                       # DTB misses
system.cpu.dtb.data_acv                            18                       # DTB access violations
system.cpu.dtb.data_accesses                 38725692                       # DTB accesses
system.cpu.itb.fetch_hits                    13913083                       # ITB hits
system.cpu.itb.fetch_misses                     32600                       # ITB misses
system.cpu.itb.fetch_acv                            0                       # ITB acv
system.cpu.itb.fetch_accesses                13945683                       # ITB accesses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.read_acv                             0                       # DTB read access violations
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.write_acv                            0                       # DTB write access violations
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.data_hits                            0                       # DTB hits
system.cpu.itb.data_misses                          0                       # DTB misses
system.cpu.itb.data_acv                             0                       # DTB access violations
system.cpu.itb.data_accesses                        0                       # DTB accesses
system.cpu.workload.num_syscalls                 4583                       # Number of system calls
system.cpu.numCycles                         45156244                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles           15767330                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      106100961                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    16619938                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches            9363361                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                      27775290                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                  962592                       # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles                        208                       # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.MiscStallCycles                 5030                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles        339291                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles           71                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                  13913083                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                207051                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes                       2                       # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples           44368516                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              2.391357                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.125574                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                 24640012     55.53%     55.53% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  1537852      3.47%     59.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                  1401576      3.16%     62.16% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                  1522530      3.43%     65.59% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  4244947      9.57%     75.16% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                  1845094      4.16%     79.32% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                   677475      1.53%     80.84% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                  1069981      2.41%     83.26% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                  7429049     16.74%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total             44368516                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.368054                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        2.349641                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 15099347                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles               9823247                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                  18465046                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles                597969                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                 382907                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved              3741515                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                100209                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts              104016227                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                314595                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                 382907                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 15487504                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                 6707215                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles          96849                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                  18654699                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles               3039342                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              102867556                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                  4643                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                 101006                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents                 348263                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents                2491758                       # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands            61906530                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups             124122948                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups        123794647                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups            328300                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps              52546881                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                  9359649                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts               5745                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts           5793                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                   2522683                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             23265731                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            16453437                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           1244012                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores           539260                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                   91299347                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded                5639                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                  89055311                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued             77552                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        11713229                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined      4714239                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved           1056                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples      44368516                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         2.007174                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        2.246117                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0            17795444     40.11%     40.11% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1             5774110     13.01%     53.12% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2             5077311     11.44%     64.57% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3             4396727      9.91%     74.48% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4             4357066      9.82%     84.30% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5             2650893      5.97%     90.27% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6             1948119      4.39%     94.66% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7             1385813      3.12%     97.78% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8              983033      2.22%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total        44368516                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                  243204      9.64%      9.64% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      1      0.00%      9.64% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%      9.64% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%      9.64% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%      9.64% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%      9.64% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%      9.64% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%      9.64% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      9.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%      9.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      9.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%      9.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%      9.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%      9.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%      9.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%      9.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      9.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%      9.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      9.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      9.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      9.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      9.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      9.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      9.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      9.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      9.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      9.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      9.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      9.64% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                1172094     46.45%     56.09% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite               1108166     43.91%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu              49651741     55.75%     55.75% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                44157      0.05%     55.80% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     55.80% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd              121956      0.14%     55.94% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                  89      0.00%     55.94% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt              121436      0.14%     56.08% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                 54      0.00%     56.08% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv               39055      0.04%     56.12% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     56.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     56.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     56.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     56.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     56.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     56.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     56.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     56.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     56.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     56.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     56.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     56.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     56.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     56.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     56.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     56.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     56.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     56.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     56.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     56.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     56.12% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             23004684     25.83%     81.95% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite            16072139     18.05%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total               89055311                       # Type of FU issued
system.cpu.iq.rate                           1.972159                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                     2523465                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.028336                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads          224465346                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         102605449                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses     87163804                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads              614809                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes             433844                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses       300747                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses               91271228                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                  307548                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          1661543                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      2989093                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses         6317                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        21548                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      1840060                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads         3023                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked        186080                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                 382907                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                 1413856                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles               4974138                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           100829471                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            151929                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              23265731                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             16453437                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts               5565                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                   4999                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents               4957861                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          21548                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         151078                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       158072                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts               309150                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts              88275465                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              22814985                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts            779846                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                       9524485                       # number of nop insts executed
system.cpu.iew.exec_refs                     38726852                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 15171568                       # Number of branches executed
system.cpu.iew.exec_stores                   15911867                       # Number of stores executed
system.cpu.iew.exec_rate                     1.954889                       # Inst execution rate
system.cpu.iew.wb_sent                       87882002                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                      87464551                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                  33900833                       # num instructions producing a value
system.cpu.iew.wb_consumers                  44342613                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.936931                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.764520                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts         9282281                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls            4583                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts            263184                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples     43000551                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     2.054408                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.876009                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0     21467431     49.92%     49.92% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1      6329802     14.72%     64.64% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2      2918642      6.79%     71.43% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3      1760390      4.09%     75.53% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      1670777      3.89%     79.41% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      1138707      2.65%     82.06% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6      1203989      2.80%     84.86% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7       794665      1.85%     86.71% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      5716148     13.29%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total     43000551                       # Number of insts commited each cycle
system.cpu.commit.committedInsts             88340672                       # Number of instructions committed
system.cpu.commit.committedOps               88340672                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       34890015                       # Number of memory references committed
system.cpu.commit.loads                      20276638                       # Number of loads committed
system.cpu.commit.membars                           0                       # Number of memory barriers committed
system.cpu.commit.branches                   13754477                       # Number of branches committed
system.cpu.commit.fp_insts                     267754                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                  77942044                       # Number of committed integer instructions.
system.cpu.commit.function_calls              1661057                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass      8748916      9.90%      9.90% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu         44394798     50.25%     60.16% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult           41101      0.05%     60.20% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv                0      0.00%     60.20% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd         114304      0.13%     60.33% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp             84      0.00%     60.33% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt         113640      0.13%     60.46% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult            50      0.00%     60.46% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv          37764      0.04%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead        20276638     22.95%     83.46% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite       14613377     16.54%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total          88340672                       # Class of committed instruction
system.cpu.commit.bw_lim_events               5716148                       # number cycles where commit BW limit reached
system.cpu.rob.rob_reads                    133590014                       # The number of ROB reads
system.cpu.rob.rob_writes                   196617452                       # The number of ROB writes
system.cpu.timesIdled                           47547                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                          787728                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                    79591756                       # Number of Instructions Simulated
system.cpu.committedOps                      79591756                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               0.567348                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.567348                       # CPI: Total CPI of All Threads
system.cpu.ipc                               1.762586                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         1.762586                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                116851082                       # number of integer regfile reads
system.cpu.int_regfile_writes                57926468                       # number of integer regfile writes
system.cpu.fp_regfile_reads                    255690                       # number of floating regfile reads
system.cpu.fp_regfile_writes                   241313                       # number of floating regfile writes
system.cpu.misc_regfile_reads                   38160                       # number of misc regfile reads
system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
system.cpu.dcache.tags.replacements            201362                       # number of replacements
system.cpu.dcache.tags.tagsinuse          4070.706489                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            34086491                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs            205458                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs            165.904910                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle         231989000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data  4070.706489                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.993825                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.993825                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           76                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1         2590                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2         1430                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses          71020044                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses         71020044                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data     20525035                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        20525035                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     13561393                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       13561393                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data           63                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total           63                       # number of LoadLockedReq hits
system.cpu.dcache.demand_hits::cpu.data      34086428                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         34086428                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     34086428                       # number of overall hits
system.cpu.dcache.overall_hits::total        34086428                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data       268817                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        268817                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      1051984                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      1051984                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data            1                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total            1                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data      1320801                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        1320801                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      1320801                       # number of overall misses
system.cpu.dcache.overall_misses::total       1320801                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  17503667749                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  17503667749                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  89467046923                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  89467046923                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data        99750                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total        99750                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 106970714672                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 106970714672                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 106970714672                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 106970714672                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     20793852                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     20793852                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     14613377                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     14613377                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data           64                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total           64                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     35407229                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     35407229                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     35407229                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     35407229                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.012928                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.012928                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.071988                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.071988                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.015625                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.015625                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.037303                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.037303                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.037303                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.037303                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 65113.693513                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 65113.693513                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 85046.014885                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 85046.014885                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        99750                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        99750                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 80989.274442                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 80989.274442                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 80989.274442                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 80989.274442                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs      6831456                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets          275                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs             88055                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               2                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    77.581693                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets   137.500000                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       168921                       # number of writebacks
system.cpu.dcache.writebacks::total            168921                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       206754                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       206754                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data       908590                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total       908590                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      1115344                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      1115344                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      1115344                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      1115344                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data        62063                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total        62063                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       143394                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       143394                       # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data            1                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total            1                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data       205457                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total       205457                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data       205457                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total       205457                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   3191920501                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total   3191920501                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  14187677704                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  14187677704                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data        97750                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total        97750                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  17379598205                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  17379598205                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  17379598205                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  17379598205                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002985                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002985                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.009813                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.009813                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.015625                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.015625                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.005803                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.005803                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.005803                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.005803                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51430.328875                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51430.328875                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 98941.920192                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 98941.920192                       # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data        97750                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total        97750                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84589.954127                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 84589.954127                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84589.954127                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 84589.954127                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements             92948                       # number of replacements
system.cpu.icache.tags.tagsinuse          1916.254210                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs            13805160                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs             94996                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs            145.323593                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle       19026930250                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst  1916.254210                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.935671                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.935671                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024         2048                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           69                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1           92                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2           30                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3         1478                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4          379                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses          27921160                       # Number of tag accesses
system.cpu.icache.tags.data_accesses         27921160                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst     13805160                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        13805160                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      13805160                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         13805160                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     13805160                       # number of overall hits
system.cpu.icache.overall_hits::total        13805160                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst       107922                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total        107922                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst       107922                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total         107922                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst       107922                       # number of overall misses
system.cpu.icache.overall_misses::total        107922                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst   2071977734                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total   2071977734                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst   2071977734                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total   2071977734                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst   2071977734                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total   2071977734                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     13913082                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     13913082                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     13913082                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     13913082                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     13913082                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     13913082                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.007757                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.007757                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.007757                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.007757                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.007757                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.007757                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19198.844851                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 19198.844851                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 19198.844851                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 19198.844851                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 19198.844851                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 19198.844851                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs          448                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                10                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    44.800000                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst        12925                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total        12925                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst        12925                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total        12925                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst        12925                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total        12925                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst        94997                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total        94997                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst        94997                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total        94997                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst        94997                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total        94997                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   1636224764                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total   1636224764                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst   1636224764                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total   1636224764                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst   1636224764                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total   1636224764                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.006828                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.006828                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.006828                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.006828                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.006828                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.006828                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17223.962483                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17223.962483                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17223.962483                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 17223.962483                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17223.962483                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 17223.962483                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements           132323                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        30601.222528                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs             161333                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           164386                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             0.981428                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 26658.229296                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  2102.973655                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data  1840.019577                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.813545                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.064178                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.056153                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.933875                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        32063                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0          168                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1         2820                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2        28790                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3          228                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4           57                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.978485                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses          4062789                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses         4062789                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst        87377                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data        34233                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total         121610                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks       168921                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total       168921                       # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data        12614                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total        12614                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst        87377                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data        46847                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total          134224                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst        87377                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data        46847                       # number of overall hits
system.cpu.l2cache.overall_hits::total         134224                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst         7620                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data        27830                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total        35450                       # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       130781                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       130781                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst         7620                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       158611                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        166231                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         7620                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       158611                       # number of overall misses
system.cpu.l2cache.overall_misses::total       166231                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    623216750                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data   2766024500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   3389241250                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  13898935250                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  13898935250                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    623216750                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  16664959750                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  17288176500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    623216750                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  16664959750                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  17288176500                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst        94997                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data        62063                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total       157060                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks       168921                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total       168921                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       143395                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       143395                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst        94997                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data       205458                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total       300455                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst        94997                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data       205458                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total       300455                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.080213                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.448415                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.225710                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.912033                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.912033                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.080213                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.771987                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.553264                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.080213                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.771987                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.553264                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 81786.975066                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 99390.028746                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 95606.241185                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 106276.410564                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 106276.410564                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81786.975066                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 105068.121063                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 104000.917398                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81786.975066                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 105068.121063                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 104000.917398                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks       114013                       # number of writebacks
system.cpu.l2cache.writebacks::total           114013                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         7620                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        27830                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total        35450                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       130781                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       130781                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         7620                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       158611                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       166231                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         7620                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       158611                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       166231                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    527900750                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   2422370000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   2950270750                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  12290499750                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  12290499750                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    527900750                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  14712869750                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  15240770500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    527900750                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  14712869750                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  15240770500                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.080213                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.448415                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.225710                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.912033                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.912033                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.080213                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.771987                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.553264                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.080213                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.771987                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.553264                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69278.313648                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 87041.681639                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 83223.434415                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 93977.716564                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 93977.716564                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69278.313648                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 92760.714894                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 91684.285723                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69278.313648                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 92760.714894                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 91684.285723                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq         157060                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp        157059                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback       168921                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       143395                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       143395                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       189993                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       579837                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total            769830                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      6079744                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     23960256                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total           30040000                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples       469376                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1             469376    100.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total         469376                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy      403609000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          1.8                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy     143899236                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.6                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy     325469999                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          1.4                       # Layer utilization (%)
system.membus.trans_dist::ReadReq               35449                       # Transaction distribution
system.membus.trans_dist::ReadResp              35449                       # Transaction distribution
system.membus.trans_dist::Writeback            114013                       # Transaction distribution
system.membus.trans_dist::ReadExReq            130781                       # Transaction distribution
system.membus.trans_dist::ReadExResp           130781                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       446473                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 446473                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     17935552                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                17935552                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoop_fanout::samples            280243                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                  280243    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total              280243                       # Request fanout histogram
system.membus.reqLayer0.occupancy           786749500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               3.5                       # Layer utilization (%)
system.membus.respLayer1.occupancy          865056500                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              3.8                       # Layer utilization (%)

---------- End Simulation Statistics   ----------