path: root/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.022294                       # Number of seconds simulated
sim_ticks                                 22293541500                       # Number of ticks simulated
final_tick                                22293541500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 223643                       # Simulator instruction rate (inst/s)
host_op_rate                                   223643                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               62642230                       # Simulator tick rate (ticks/s)
host_mem_usage                                 265292                       # Number of bytes of host memory used
host_seconds                                   355.89                       # Real time elapsed on the host
sim_insts                                    79591756                       # Number of instructions simulated
sim_ops                                      79591756                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED  22293541500                       # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst            413888                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          10171008                       # Number of bytes read from this memory
system.physmem.bytes_read::total             10584896                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       413888                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          413888                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      7372800                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7372800                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst               6467                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             158922                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                165389                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          115200                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               115200                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst             18565377                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data            456231147                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total               474796523                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst        18565377                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total           18565377                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks         330714615                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total              330714615                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks         330714615                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst            18565377                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data           456231147                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              805511139                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        165389                       # Number of read requests accepted
system.physmem.writeReqs                       115200                       # Number of write requests accepted
system.physmem.readBursts                      165389                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     115200                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 10584320                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                       576                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   7371392                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  10584896                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                7372800                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                        9                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               10310                       # Per bank write bursts
system.physmem.perBankRdBursts::1               10350                       # Per bank write bursts
system.physmem.perBankRdBursts::2               10221                       # Per bank write bursts
system.physmem.perBankRdBursts::3               10037                       # Per bank write bursts
system.physmem.perBankRdBursts::4               10349                       # Per bank write bursts
system.physmem.perBankRdBursts::5               10325                       # Per bank write bursts
system.physmem.perBankRdBursts::6                9802                       # Per bank write bursts
system.physmem.perBankRdBursts::7               10210                       # Per bank write bursts
system.physmem.perBankRdBursts::8               10556                       # Per bank write bursts
system.physmem.perBankRdBursts::9               10619                       # Per bank write bursts
system.physmem.perBankRdBursts::10              10516                       # Per bank write bursts
system.physmem.perBankRdBursts::11              10224                       # Per bank write bursts
system.physmem.perBankRdBursts::12              10277                       # Per bank write bursts
system.physmem.perBankRdBursts::13              10556                       # Per bank write bursts
system.physmem.perBankRdBursts::14              10475                       # Per bank write bursts
system.physmem.perBankRdBursts::15              10553                       # Per bank write bursts
system.physmem.perBankWrBursts::0                7167                       # Per bank write bursts
system.physmem.perBankWrBursts::1                7278                       # Per bank write bursts
system.physmem.perBankWrBursts::2                7300                       # Per bank write bursts
system.physmem.perBankWrBursts::3                7008                       # Per bank write bursts
system.physmem.perBankWrBursts::4                7143                       # Per bank write bursts
system.physmem.perBankWrBursts::5                7301                       # Per bank write bursts
system.physmem.perBankWrBursts::6                6892                       # Per bank write bursts
system.physmem.perBankWrBursts::7                7161                       # Per bank write bursts
system.physmem.perBankWrBursts::8                7241                       # Per bank write bursts
system.physmem.perBankWrBursts::9                7068                       # Per bank write bursts
system.physmem.perBankWrBursts::10               7202                       # Per bank write bursts
system.physmem.perBankWrBursts::11               7125                       # Per bank write bursts
system.physmem.perBankWrBursts::12               7069                       # Per bank write bursts
system.physmem.perBankWrBursts::13               7390                       # Per bank write bursts
system.physmem.perBankWrBursts::14               7350                       # Per bank write bursts
system.physmem.perBankWrBursts::15               7483                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                     22293510500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  165389                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 115200                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                     51841                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     42842                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     37971                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                     32721                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         4                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                      573                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                      592                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     1926                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     4151                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     5795                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     7104                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     7170                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     7199                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     7221                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     7239                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     7342                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     7855                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     7431                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     7928                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    11020                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     7854                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     8872                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     7759                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      116                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                       28                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                       10                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        44806                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      400.727760                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     239.628821                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     367.162466                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          13215     29.49%     29.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255         8315     18.56%     48.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         5340     11.92%     59.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         2750      6.14%     66.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2605      5.81%     71.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1593      3.56%     75.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1654      3.69%     79.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1106      2.47%     81.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         8228     18.36%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          44806                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          7098                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        23.298957                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::gmean       17.933264                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      317.077516                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023           7097     99.99%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::26624-27647            1      0.01%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            7098                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          7098                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        16.226824                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       16.209944                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        0.780993                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16               6477     91.25%     91.25% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17                 22      0.31%     91.56% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18                336      4.73%     96.29% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19                168      2.37%     98.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20                 66      0.93%     99.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21                 27      0.38%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22                  1      0.01%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23                  1      0.01%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            7098                       # Writes before turning the bus around for reads
system.physmem.totQLat                     5599085250                       # Total ticks spent queuing
system.physmem.totMemAccLat                8699960250                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    826900000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       33855.88                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  52605.88                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                         474.77                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                         330.65                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                      474.80                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                      330.71                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           6.29                       # Data bus utilization in percentage
system.physmem.busUtilRead                       3.71                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      2.58                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.93                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        24.72                       # Average write queue length when enqueuing
system.physmem.readRowHits                     145830                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     89913                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   88.18                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  78.05                       # Row buffer hit rate for writes
system.physmem.avgGap                        79452.55                       # Average gap between requests
system.physmem.pageHitRate                      84.02                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  163424520                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                   89170125                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 636441000                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                370882800                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy             1456007280                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy             6110627715                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy             8015176500                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy              16841729940                       # Total energy per rank (pJ)
system.physmem_0.averagePower              755.495604                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE    13256940500                       # Time in different power states
system.physmem_0.memoryStateTime::REF       744380000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT      8290987000                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  175218120                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                   95605125                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 653343600                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                375366960                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy             1456007280                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy             6480752940                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy             7690505250                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy              16926799275                       # Total energy per rank (pJ)
system.physmem_1.averagePower              759.311692                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE    12714890500                       # Time in different power states
system.physmem_1.memoryStateTime::REF       744380000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT      8833037000                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.pwrStateResidencyTicks::UNDEFINED  22293541500                       # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups                16464676                       # Number of BP lookups
system.cpu.branchPred.condPredicted          10658312                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect            322373                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups              8884191                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                 7232535                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             81.409044                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 1975403                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect               3321                       # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups           39323                       # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits              31540                       # Number of indirect target hits.
system.cpu.branchPred.indirectMisses             7783                       # Number of indirect misses.
system.cpu.branchPredindirectMispredicted         2655                       # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dtb.fetch_hits                           0                       # ITB hits
system.cpu.dtb.fetch_misses                         0                       # ITB misses
system.cpu.dtb.fetch_acv                            0                       # ITB acv
system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
system.cpu.dtb.read_hits                     22505585                       # DTB read hits
system.cpu.dtb.read_misses                     226699                       # DTB read misses
system.cpu.dtb.read_acv                            16                       # DTB read access violations
system.cpu.dtb.read_accesses                 22732284                       # DTB read accesses
system.cpu.dtb.write_hits                    15808846                       # DTB write hits
system.cpu.dtb.write_misses                     44546                       # DTB write misses
system.cpu.dtb.write_acv                            6                       # DTB write access violations
system.cpu.dtb.write_accesses                15853392                       # DTB write accesses
system.cpu.dtb.data_hits                     38314431                       # DTB hits
system.cpu.dtb.data_misses                     271245                       # DTB misses
system.cpu.dtb.data_acv                            22                       # DTB access violations
system.cpu.dtb.data_accesses                 38585676                       # DTB accesses
system.cpu.itb.fetch_hits                    13724143                       # ITB hits
system.cpu.itb.fetch_misses                     29345                       # ITB misses
system.cpu.itb.fetch_acv                            0                       # ITB acv
system.cpu.itb.fetch_accesses                13753488                       # ITB accesses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.read_acv                             0                       # DTB read access violations
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.write_acv                            0                       # DTB write access violations
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.data_hits                            0                       # DTB hits
system.cpu.itb.data_misses                          0                       # DTB misses
system.cpu.itb.data_acv                             0                       # DTB access violations
system.cpu.itb.data_accesses                        0                       # DTB accesses
system.cpu.workload.num_syscalls                 4583                       # Number of system calls
system.cpu.pwrStateResidencyTicks::ON     22293541500                       # Cumulative time (in ticks) in various power states
system.cpu.numCycles                         44587088                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles           15537600                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      105003279                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    16464676                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches            9239478                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                      27573681                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                  883330                       # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles                        247                       # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.MiscStallCycles                 4700                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles        330450                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles           85                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                  13724143                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                187041                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes                       1                       # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples           43888428                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              2.392505                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.127693                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                 24387762     55.57%     55.57% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  1515251      3.45%     59.02% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                  1377134      3.14%     62.16% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                  1500310      3.42%     65.58% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  4190997      9.55%     75.13% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                  1825571      4.16%     79.29% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                   669926      1.53%     80.81% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                  1050385      2.39%     83.20% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                  7371092     16.80%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total             43888428                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.369270                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        2.355015                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 14897050                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles               9776190                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                  18280655                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles                589828                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                 344705                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved              3701787                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                 98635                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts              103032848                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                312916                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                 344705                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 15240775                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                 4552016                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles          97125                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                  18511621                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles               5142186                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              102032260                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                  5895                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                  92509                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents                 354670                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents                4626637                       # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands            61342957                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups             123044735                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups        122725402                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups            319332                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps              52546881                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                  8796076                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts               5684                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts           5736                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                   2358572                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             23134576                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            16358313                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           1246652                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores           504576                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                   90719727                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded                5556                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                  88603709                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued             68043                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        11133526                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined      4439018                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved            973                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples      43888428                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         2.018840                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        2.245634                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0            17434377     39.72%     39.72% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1             5720394     13.03%     52.76% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2             5103914     11.63%     64.39% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3             4383916      9.99%     74.38% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4             4317842      9.84%     84.21% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5             2637316      6.01%     90.22% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6             1940633      4.42%     94.65% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7             1378295      3.14%     97.79% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8              971741      2.21%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total        43888428                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                  241284      9.57%      9.57% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%      9.57% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%      9.57% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%      9.57% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%      9.57% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%      9.57% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%      9.57% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%      9.57% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      9.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%      9.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      9.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%      9.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%      9.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%      9.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%      9.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%      9.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      9.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%      9.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      9.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      9.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      9.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      9.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      9.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      9.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      9.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      9.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      9.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      9.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      9.57% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                1166228     46.24%     55.80% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite               1114848     44.20%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu              49379489     55.73%     55.73% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                44005      0.05%     55.78% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     55.78% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd              121171      0.14%     55.92% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                  92      0.00%     55.92% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt              120707      0.14%     56.05% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                 62      0.00%     56.05% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv               39092      0.04%     56.10% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     56.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     56.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     56.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     56.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     56.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     56.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     56.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     56.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     56.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     56.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     56.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     56.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     56.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     56.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     56.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     56.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     56.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     56.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     56.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     56.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     56.10% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             22899221     25.84%     81.94% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite            15999870     18.06%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total               88603709                       # Type of FU issued
system.cpu.iq.rate                           1.987206                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                     2522360                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.028468                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads          223074890                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         101458980                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses     86835527                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads              611359                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes             420488                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses       299878                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses               90820238                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                  305831                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          1672227                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      2857938                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses         5878                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        20874                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      1744936                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads         3021                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked        200758                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                 344705                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                 1315985                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles               2729229                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           100214269                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            118431                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              23134576                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             16358313                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts               5556                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                   3898                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents               2727794                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          20874                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         113179                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       152389                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts               265568                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts              87909421                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              22732927                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts            694288                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                       9488986                       # number of nop insts executed
system.cpu.iew.exec_refs                     38586655                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 15119960                       # Number of branches executed
system.cpu.iew.exec_stores                   15853728                       # Number of stores executed
system.cpu.iew.exec_rate                     1.971634                       # Inst execution rate
system.cpu.iew.wb_sent                       87537444                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                      87135405                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                  33842966                       # num instructions producing a value
system.cpu.iew.wb_consumers                  44247648                       # num instructions consuming a value
system.cpu.iew.wb_rate                       1.954274                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.764853                       # average fanout of values written-back
system.cpu.commit.commitSquashedInsts         8653815                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls            4583                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts            225413                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples     42617548                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     2.072871                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.885939                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0     21149374     49.63%     49.63% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1      6281932     14.74%     64.37% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2      2908445      6.82%     71.19% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3      1738602      4.08%     75.27% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      1681485      3.95%     79.22% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      1121192      2.63%     81.85% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6      1200701      2.82%     84.66% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7       796598      1.87%     86.53% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      5739219     13.47%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total     42617548                       # Number of insts commited each cycle
system.cpu.commit.committedInsts             88340672                       # Number of instructions committed
system.cpu.commit.committedOps               88340672                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       34890015                       # Number of memory references committed
system.cpu.commit.loads                      20276638                       # Number of loads committed
system.cpu.commit.membars                           0                       # Number of memory barriers committed
system.cpu.commit.branches                   13754477                       # Number of branches committed
system.cpu.commit.fp_insts                     267754                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                  77942044                       # Number of committed integer instructions.
system.cpu.commit.function_calls              1661057                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass      8748916      9.90%      9.90% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu         44394798     50.25%     60.16% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult           41101      0.05%     60.20% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv                0      0.00%     60.20% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd         114304      0.13%     60.33% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp             84      0.00%     60.33% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt         113640      0.13%     60.46% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult            50      0.00%     60.46% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv          37764      0.04%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead        20276638     22.95%     83.46% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite       14613377     16.54%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total          88340672                       # Class of committed instruction
system.cpu.commit.bw_lim_events               5739219                       # number cycles where commit BW limit reached
system.cpu.rob.rob_reads                    132555474                       # The number of ROB reads
system.cpu.rob.rob_writes                   195263120                       # The number of ROB writes
system.cpu.timesIdled                           45271                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                          698660                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                    79591756                       # Number of Instructions Simulated
system.cpu.committedOps                      79591756                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               0.560197                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.560197                       # CPI: Total CPI of All Threads
system.cpu.ipc                               1.785085                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         1.785085                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                116363135                       # number of integer regfile reads
system.cpu.int_regfile_writes                57669565                       # number of integer regfile writes
system.cpu.fp_regfile_reads                    255561                       # number of floating regfile reads
system.cpu.fp_regfile_writes                   240404                       # number of floating regfile writes
system.cpu.misc_regfile_reads                   38263                       # number of misc regfile reads
system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED  22293541500                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements            201400                       # number of replacements
system.cpu.dcache.tags.tagsinuse          4070.443451                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            33984025                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs            205496                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs            165.375603                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle         232048500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data  4070.443451                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.993761                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.993761                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           76                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1         2679                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2         1341                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses          70817108                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses         70817108                       # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED  22293541500                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data     20422994                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        20422994                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     13560978                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       13560978                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data           53                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total           53                       # number of LoadLockedReq hits
system.cpu.dcache.demand_hits::cpu.data      33983972                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         33983972                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     33983972                       # number of overall hits
system.cpu.dcache.overall_hits::total        33983972                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data       269382                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        269382                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      1052399                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      1052399                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data      1321781                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        1321781                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      1321781                       # number of overall misses
system.cpu.dcache.overall_misses::total       1321781                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  18043068500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  18043068500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  88421559159                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  88421559159                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 106464627659                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 106464627659                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 106464627659                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 106464627659                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     20692376                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     20692376                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     14613377                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     14613377                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data           53                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total           53                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     35305753                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     35305753                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     35305753                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     35305753                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.013018                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.013018                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.072016                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.072016                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.037438                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.037438                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.037438                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.037438                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66979.488236                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 66979.488236                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 84019.045209                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 84019.045209                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 80546.344409                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 80546.344409                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 80546.344409                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 80546.344409                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs      6874865                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets          279                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs             86609                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               2                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    79.378182                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets   139.500000                       # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks       168502                       # number of writebacks
system.cpu.dcache.writebacks::total            168502                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       207279                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       207279                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data       909006                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total       909006                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      1116285                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      1116285                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      1116285                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      1116285                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data        62103                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total        62103                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       143393                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       143393                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data       205496                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total       205496                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data       205496                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total       205496                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   3336459000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total   3336459000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  14128429272                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  14128429272                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  17464888272                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  17464888272                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  17464888272                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  17464888272                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.003001                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.003001                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.009812                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.009812                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.005820                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.005820                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.005820                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.005820                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53724.602676                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53724.602676                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 98529.421046                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 98529.421046                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84988.945147                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 84988.945147                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84988.945147                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 84988.945147                       # average overall mshr miss latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED  22293541500                       # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements             90436                       # number of replacements
system.cpu.icache.tags.tagsinuse          1916.490065                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs            13619166                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs             92484                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs            147.259699                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle       18779712500                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst  1916.490065                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.935786                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.935786                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024         2048                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           68                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          106                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2           25                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3         1460                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4          389                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses          27540768                       # Number of tag accesses
system.cpu.icache.tags.data_accesses         27540768                       # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED  22293541500                       # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst     13619166                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        13619166                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      13619166                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         13619166                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     13619166                       # number of overall hits
system.cpu.icache.overall_hits::total        13619166                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst       104976                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total        104976                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst       104976                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total         104976                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst       104976                       # number of overall misses
system.cpu.icache.overall_misses::total        104976                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst   1956506499                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total   1956506499                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst   1956506499                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total   1956506499                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst   1956506499                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total   1956506499                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     13724142                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     13724142                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     13724142                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     13724142                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     13724142                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     13724142                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.007649                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.007649                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.007649                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.007649                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.007649                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.007649                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18637.655264                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 18637.655264                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 18637.655264                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 18637.655264                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 18637.655264                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 18637.655264                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs         1136                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                15                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    75.733333                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks        90436                       # number of writebacks
system.cpu.icache.writebacks::total             90436                       # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst        12491                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total        12491                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst        12491                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total        12491                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst        12491                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total        12491                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst        92485                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total        92485                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst        92485                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total        92485                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst        92485                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total        92485                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   1595124000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total   1595124000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst   1595124000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total   1595124000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst   1595124000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total   1595124000                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.006739                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.006739                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.006739                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.006739                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.006739                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.006739                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17247.380656                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17247.380656                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17247.380656                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 17247.380656                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17247.380656                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 17247.380656                       # average overall mshr miss latency
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED  22293541500                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements           134874                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        31863.975507                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs             422062                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           167642                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             2.517639                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle       4859656000                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks   722.364840                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  1777.470792                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 29364.139876                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.022045                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.054244                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.896122                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.972411                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        32768                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0          208                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1         2938                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2        29364                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3          202                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4           56                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses          4886178                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses         4886178                       # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED  22293541500                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks       168502                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total       168502                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks        90436                       # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total        90436                       # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data        12584                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total        12584                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        86017                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total        86017                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data        33990                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total        33990                       # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst        86017                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data        46574                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total          132591                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst        86017                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data        46574                       # number of overall hits
system.cpu.l2cache.overall_hits::total         132591                       # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data       130811                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       130811                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         6468                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total         6468                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data        28111                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total        28111                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst         6468                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       158922                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        165390                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         6468                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       158922                       # number of overall misses
system.cpu.l2cache.overall_misses::total       165390                       # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  13777150000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  13777150000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    548837500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total    548837500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   2881866500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total   2881866500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    548837500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  16659016500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  17207854000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    548837500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  16659016500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  17207854000                       # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks       168502                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total       168502                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks        90436                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total        90436                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       143395                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       143395                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        92485                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total        92485                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data        62101                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total        62101                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst        92485                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data       205496                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total       297981                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst        92485                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data       205496                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total       297981                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.912242                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.912242                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.069936                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.069936                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.452666                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.452666                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.069936                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.773358                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.555035                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.069936                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.773358                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.555035                       # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 105321.035693                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 105321.035693                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 84854.282622                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 84854.282622                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 102517.395326                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 102517.395326                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 84854.282622                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 104825.112319                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 104044.101820                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 84854.282622                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 104825.112319                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 104044.101820                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.writebacks::writebacks       115201                       # number of writebacks
system.cpu.l2cache.writebacks::total           115201                       # number of writebacks
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          112                       # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total          112                       # number of CleanEvict MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       130811                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       130811                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         6468                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total         6468                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        28111                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total        28111                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         6468                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       158922                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       165390                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         6468                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       158922                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       165390                       # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  12469040000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  12469040000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    484167500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    484167500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   2600756500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   2600756500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    484167500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  15069796500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  15553964000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    484167500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  15069796500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  15553964000                       # number of overall MSHR miss cycles
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.912242                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.912242                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.069936                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.069936                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.452666                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.452666                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.069936                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.773358                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.555035                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.069936                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.773358                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.555035                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95321.035693                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95321.035693                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 74855.828695                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 74855.828695                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 92517.395326                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 92517.395326                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 74855.828695                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 94825.112319                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 94044.162283                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 74855.828695                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 94825.112319                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 94044.162283                       # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests       589817                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests       291836                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops         4239                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops         4239                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED  22293541500                       # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp        154585                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty       283703                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean        90436                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict        52571                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       143395                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       143395                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq        92485                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq        62101                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       275405                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       612392                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total            887797                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     11706880                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     23935872                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total           35642752                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                      134874                       # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic               7372864                       # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples       432855                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        0.009793                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.098475                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0             428616     99.02%     99.02% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1               4239      0.98%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total         432855                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy      553846500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          2.5                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy     138734483                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.6                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy     308248491                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          1.4                       # Layer utilization (%)
system.membus.snoop_filter.tot_requests        296135                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests       130746                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED  22293541500                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp              34578                       # Transaction distribution
system.membus.trans_dist::WritebackDirty       115200                       # Transaction distribution
system.membus.trans_dist::CleanEvict            15546                       # Transaction distribution
system.membus.trans_dist::ReadExReq            130811                       # Transaction distribution
system.membus.trans_dist::ReadExResp           130811                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq         34578                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       461524                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 461524                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     17957696                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                17957696                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples            165389                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                  165389    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total              165389                       # Request fanout histogram
system.membus.reqLayer0.occupancy           780841500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               3.5                       # Layer utilization (%)
system.membus.respLayer1.occupancy          854544750                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              3.8                       # Layer utilization (%)

---------- End Simulation Statistics   ----------