path: root/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.022330                       # Number of seconds simulated
sim_ticks                                 22329989500                       # Number of ticks simulated
final_tick                                22329989500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 232150                       # Simulator instruction rate (inst/s)
host_op_rate                                   232150                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               65131135                       # Simulator tick rate (ticks/s)
host_mem_usage                                 301288                       # Number of bytes of host memory used
host_seconds                                   342.85                       # Real time elapsed on the host
sim_insts                                    79591756                       # Number of instructions simulated
sim_ops                                      79591756                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst            487424                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          10151616                       # Number of bytes read from this memory
system.physmem.bytes_read::total             10639040                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       487424                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          487424                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      7296896                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7296896                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst               7616                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             158619                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                166235                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          114014                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               114014                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst             21828223                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data            454618037                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total               476446261                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst        21828223                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total           21828223                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks         326775613                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total              326775613                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks         326775613                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst            21828223                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data           454618037                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              803221873                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        166235                       # Number of read requests accepted
system.physmem.writeReqs                       114014                       # Number of write requests accepted
system.physmem.readBursts                      166235                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     114014                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 10638592                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                       448                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   7294848                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  10639040                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                7296896                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                        7                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               10441                       # Per bank write bursts
system.physmem.perBankRdBursts::1               10459                       # Per bank write bursts
system.physmem.perBankRdBursts::2               10317                       # Per bank write bursts
system.physmem.perBankRdBursts::3               10059                       # Per bank write bursts
system.physmem.perBankRdBursts::4               10419                       # Per bank write bursts
system.physmem.perBankRdBursts::5               10394                       # Per bank write bursts
system.physmem.perBankRdBursts::6                9840                       # Per bank write bursts
system.physmem.perBankRdBursts::7               10309                       # Per bank write bursts
system.physmem.perBankRdBursts::8               10592                       # Per bank write bursts
system.physmem.perBankRdBursts::9               10641                       # Per bank write bursts
system.physmem.perBankRdBursts::10              10546                       # Per bank write bursts
system.physmem.perBankRdBursts::11              10221                       # Per bank write bursts
system.physmem.perBankRdBursts::12              10273                       # Per bank write bursts
system.physmem.perBankRdBursts::13              10617                       # Per bank write bursts
system.physmem.perBankRdBursts::14              10480                       # Per bank write bursts
system.physmem.perBankRdBursts::15              10620                       # Per bank write bursts
system.physmem.perBankWrBursts::0                7082                       # Per bank write bursts
system.physmem.perBankWrBursts::1                7259                       # Per bank write bursts
system.physmem.perBankWrBursts::2                7256                       # Per bank write bursts
system.physmem.perBankWrBursts::3                6997                       # Per bank write bursts
system.physmem.perBankWrBursts::4                7126                       # Per bank write bursts
system.physmem.perBankWrBursts::5                7168                       # Per bank write bursts
system.physmem.perBankWrBursts::6                6771                       # Per bank write bursts
system.physmem.perBankWrBursts::7                7079                       # Per bank write bursts
system.physmem.perBankWrBursts::8                7221                       # Per bank write bursts
system.physmem.perBankWrBursts::9                6942                       # Per bank write bursts
system.physmem.perBankWrBursts::10               7083                       # Per bank write bursts
system.physmem.perBankWrBursts::11               6989                       # Per bank write bursts
system.physmem.perBankWrBursts::12               6966                       # Per bank write bursts
system.physmem.perBankWrBursts::13               7287                       # Per bank write bursts
system.physmem.perBankWrBursts::14               7284                       # Per bank write bursts
system.physmem.perBankWrBursts::15               7472                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                     22329955500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  166235                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 114014                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                     51693                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     53757                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     45708                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                     15052                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                        15                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                      792                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                      828                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     1375                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     2435                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     4487                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     5816                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     6333                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     6671                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     7023                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     7411                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     7844                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     8187                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     8759                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     9546                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     8478                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     8990                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     9356                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     8428                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      619                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      313                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      172                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                       99                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                       24                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        7                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        3                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        51907                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      345.459688                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     202.593638                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     345.239241                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          18141     34.95%     34.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        10684     20.58%     55.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         5599     10.79%     66.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         2999      5.78%     72.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2733      5.27%     77.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1724      3.32%     80.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1780      3.43%     84.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1211      2.33%     86.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         7036     13.56%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          51907                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          6971                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        23.843208                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      342.237754                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023           6969     99.97%     99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047            1      0.01%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::27648-28671            1      0.01%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            6971                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          6971                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        16.350882                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       16.321302                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        1.052955                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16               6113     87.69%     87.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17                 29      0.42%     88.11% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18                435      6.24%     94.35% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19                209      3.00%     97.35% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20                 90      1.29%     98.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21                 57      0.82%     99.45% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22                 19      0.27%     99.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23                  5      0.07%     99.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24                  4      0.06%     99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::25                  6      0.09%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26                  4      0.06%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            6971                       # Writes before turning the bus around for reads
system.physmem.totQLat                     5659900500                       # Total ticks spent queuing
system.physmem.totMemAccLat                8776675500                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    831140000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       34049.02                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  52799.02                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                         476.43                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                         326.68                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                      476.45                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                      326.78                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           6.27                       # Data bus utilization in percentage
system.physmem.busUtilRead                       3.72                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      2.55                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.81                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        24.55                       # Average write queue length when enqueuing
system.physmem.readRowHits                     146045                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     82245                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   87.86                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  72.14                       # Row buffer hit rate for writes
system.physmem.avgGap                        79678.98                       # Average gap between requests
system.physmem.pageHitRate                      81.46                       # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE       9562649000                       # Time in different power states
system.physmem.memoryStateTime::REF         745420000                       # Time in different power states
system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
system.physmem.memoryStateTime::ACT       12015383500                       # Time in different power states
system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
system.membus.trans_dist::ReadReq               35446                       # Transaction distribution
system.membus.trans_dist::ReadResp              35446                       # Transaction distribution
system.membus.trans_dist::Writeback            114014                       # Transaction distribution
system.membus.trans_dist::ReadExReq            130789                       # Transaction distribution
system.membus.trans_dist::ReadExResp           130789                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       446484                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 446484                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     17935936                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                17935936                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoop_fanout::samples            280249                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                  280249    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total              280249                       # Request fanout histogram
system.membus.reqLayer0.occupancy          1235861000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               5.5                       # Layer utilization (%)
system.membus.respLayer1.occupancy         1525180500                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              6.8                       # Layer utilization (%)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.branchPred.lookups                16618969                       # Number of BP lookups
system.cpu.branchPred.condPredicted          10749423                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect            361100                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             10742405                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                 7368684                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             68.594360                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 1994688                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect               3025                       # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits                           0                       # ITB hits
system.cpu.dtb.fetch_misses                         0                       # ITB misses
system.cpu.dtb.fetch_acv                            0                       # ITB acv
system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
system.cpu.dtb.read_hits                     22640578                       # DTB read hits
system.cpu.dtb.read_misses                     225727                       # DTB read misses
system.cpu.dtb.read_acv                            15                       # DTB read access violations
system.cpu.dtb.read_accesses                 22866305                       # DTB read accesses
system.cpu.dtb.write_hits                    15860065                       # DTB write hits
system.cpu.dtb.write_misses                     44717                       # DTB write misses
system.cpu.dtb.write_acv                            7                       # DTB write access violations
system.cpu.dtb.write_accesses                15904782                       # DTB write accesses
system.cpu.dtb.data_hits                     38500643                       # DTB hits
system.cpu.dtb.data_misses                     270444                       # DTB misses
system.cpu.dtb.data_acv                            22                       # DTB access violations
system.cpu.dtb.data_accesses                 38771087                       # DTB accesses
system.cpu.itb.fetch_hits                    13913295                       # ITB hits
system.cpu.itb.fetch_misses                     31383                       # ITB misses
system.cpu.itb.fetch_acv                            0                       # ITB acv
system.cpu.itb.fetch_accesses                13944678                       # ITB accesses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.read_acv                             0                       # DTB read access violations
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.write_acv                            0                       # DTB write access violations
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.data_hits                            0                       # DTB hits
system.cpu.itb.data_misses                          0                       # DTB misses
system.cpu.itb.data_acv                             0                       # DTB access violations
system.cpu.itb.data_accesses                        0                       # DTB accesses
system.cpu.workload.num_syscalls                 4583                       # Number of system calls
system.cpu.numCycles                         44659983                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles           15776454                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      106093576                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    16618969                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches            9363372                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                      27339445                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                  961528                       # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles                        166                       # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.MiscStallCycles                 5126                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles        335016                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles           84                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                  13913295                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                207298                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes                       1                       # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples           43937055                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              2.414672                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.131710                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                 24208191     55.10%     55.10% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  1538198      3.50%     58.60% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                  1405905      3.20%     61.80% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                  1524697      3.47%     65.27% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  4231594      9.63%     74.90% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                  1847884      4.21%     79.11% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                   684699      1.56%     80.66% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                  1071609      2.44%     83.10% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                  7424278     16.90%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total             43937055                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.372122                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        2.375585                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 15090542                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles               9411892                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                  18462094                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles                590748                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                 381779                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved              3738870                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                100752                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts              103984898                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                316746                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                 381779                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 15474298                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                 6446400                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles          97317                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                  18646914                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles               2890347                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              102848317                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                  4603                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                 150963                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents                 325598                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents                2361182                       # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands            61896036                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups             124089387                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups        123759844                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups            329542                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps              52546881                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                  9349155                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts               5813                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts           5869                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                   2465054                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             23265818                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            16448253                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           1251433                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores           545590                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                   91286622                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded                5695                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                  89090659                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued             79052                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        11213817                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined      4716109                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved           1112                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples      43937055                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         2.027688                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        2.246728                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0            17318675     39.42%     39.42% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1             5798510     13.20%     52.61% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2             5098508     11.60%     64.22% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3             4414835     10.05%     74.27% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4             4342383      9.88%     84.15% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5             2650303      6.03%     90.18% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6             1951252      4.44%     94.62% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7             1378643      3.14%     97.76% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8              983946      2.24%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total        43937055                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                  243742      9.63%      9.63% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%      9.63% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%      9.63% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%      9.63% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%      9.63% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%      9.63% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%      9.63% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%      9.63% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      9.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%      9.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      9.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%      9.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%      9.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%      9.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%      9.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%      9.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      9.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%      9.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      9.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      9.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      9.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      9.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      9.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      9.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      9.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      9.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      9.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      9.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      9.63% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                1177038     46.48%     56.11% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite               1111319     43.89%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu              49642313     55.72%     55.72% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                44169      0.05%     55.77% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     55.77% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd              122147      0.14%     55.91% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                  87      0.00%     55.91% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt              121699      0.14%     56.04% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                 55      0.00%     56.04% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv               39048      0.04%     56.09% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     56.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     56.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     56.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     56.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     56.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     56.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     56.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     56.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     56.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     56.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     56.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     56.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     56.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     56.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     56.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     56.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     56.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     56.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     56.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     56.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     56.09% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             23057514     25.88%     81.97% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite            16063627     18.03%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total               89090659                       # Type of FU issued
system.cpu.iq.rate                           1.994865                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                     2532099                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.028422                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads          224114042                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         102090455                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses     87155295                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads              615482                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes             436927                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses       301089                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses               91314862                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                  307896                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          1660010                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      2989180                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses         6359                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        21743                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      1834876                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads         2985                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked        325715                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                 381779                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                 1212086                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles               4898049                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           100815278                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            146031                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              23265818                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             16448253                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts               5611                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                   3372                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents               4875472                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          21743                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         149411                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       157245                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts               306656                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts              88317091                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              22866843                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts            773568                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                       9522961                       # number of nop insts executed
system.cpu.iew.exec_refs                     38771937                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 15172750                       # Number of branches executed
system.cpu.iew.exec_stores                   15905094                       # Number of stores executed
system.cpu.iew.exec_rate                     1.977544                       # Inst execution rate
system.cpu.iew.wb_sent                       87870804                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                      87456384                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                  33898733                       # num instructions producing a value
system.cpu.iew.wb_consumers                  44340261                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.958272                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.764514                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts         9275726                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls            4583                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts            262115                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples     42571128                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     2.075131                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.882631                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0     21025343     49.39%     49.39% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1      6328820     14.87%     64.26% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2      2946361      6.92%     71.18% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3      1760662      4.14%     75.31% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      1654958      3.89%     79.20% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      1139679      2.68%     81.88% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6      1203795      2.83%     84.70% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7       795933      1.87%     86.57% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      5715577     13.43%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total     42571128                       # Number of insts commited each cycle
system.cpu.commit.committedInsts             88340672                       # Number of instructions committed
system.cpu.commit.committedOps               88340672                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       34890015                       # Number of memory references committed
system.cpu.commit.loads                      20276638                       # Number of loads committed
system.cpu.commit.membars                           0                       # Number of memory barriers committed
system.cpu.commit.branches                   13754477                       # Number of branches committed
system.cpu.commit.fp_insts                     267754                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                  77942044                       # Number of committed integer instructions.
system.cpu.commit.function_calls              1661057                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass      8748916      9.90%      9.90% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu         44394798     50.25%     60.16% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult           41101      0.05%     60.20% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv                0      0.00%     60.20% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd         114304      0.13%     60.33% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp             84      0.00%     60.33% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt         113640      0.13%     60.46% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult            50      0.00%     60.46% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv          37764      0.04%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     60.51% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead        20276638     22.95%     83.46% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite       14613377     16.54%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total          88340672                       # Class of committed instruction
system.cpu.commit.bw_lim_events               5715577                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                    133154607                       # The number of ROB reads
system.cpu.rob.rob_writes                   196602232                       # The number of ROB writes
system.cpu.timesIdled                           47762                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                          722928                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                    79591756                       # Number of Instructions Simulated
system.cpu.committedOps                      79591756                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               0.561113                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.561113                       # CPI: Total CPI of All Threads
system.cpu.ipc                               1.782172                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         1.782172                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                116877675                       # number of integer regfile reads
system.cpu.int_regfile_writes                57921110                       # number of integer regfile writes
system.cpu.fp_regfile_reads                    255696                       # number of floating regfile reads
system.cpu.fp_regfile_writes                   241715                       # number of floating regfile writes
system.cpu.misc_regfile_reads                   38130                       # number of misc regfile reads
system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
system.cpu.toL2Bus.trans_dist::ReadReq         157630                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp        157629                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback       168931                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       143405                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       143405                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       191099                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       579901                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total            771000                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      6115136                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     23962624                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total           30077760                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples       469974                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1             469974    100.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total         469974                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy      403921992                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          1.8                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy     144682208                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.6                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy     321839246                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          1.4                       # Layer utilization (%)
system.cpu.icache.tags.replacements             93501                       # number of replacements
system.cpu.icache.tags.tagsinuse          1918.858110                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs            13804656                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs             95549                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs            144.477242                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle       18832337250                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst  1918.858110                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.936942                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.936942                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024         2048                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           84                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1           81                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2           26                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3         1480                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4          377                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses          27922137                       # Number of tag accesses
system.cpu.icache.tags.data_accesses         27922137                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst     13804656                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        13804656                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      13804656                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         13804656                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     13804656                       # number of overall hits
system.cpu.icache.overall_hits::total        13804656                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst       108638                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total        108638                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst       108638                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total         108638                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst       108638                       # number of overall misses
system.cpu.icache.overall_misses::total        108638                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst   2007932205                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total   2007932205                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst   2007932205                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total   2007932205                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst   2007932205                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total   2007932205                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     13913294                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     13913294                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     13913294                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     13913294                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     13913294                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     13913294                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.007808                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.007808                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.007808                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.007808                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.007808                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.007808                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18482.779552                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 18482.779552                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 18482.779552                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 18482.779552                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 18482.779552                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 18482.779552                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs          567                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                12                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    47.250000                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst        13088                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total        13088                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst        13088                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total        13088                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst        13088                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total        13088                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst        95550                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total        95550                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst        95550                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total        95550                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst        95550                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total        95550                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   1542742292                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total   1542742292                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst   1542742292                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total   1542742292                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst   1542742292                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total   1542742292                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.006868                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.006868                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.006868                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.006868                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.006868                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.006868                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16145.916190                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16145.916190                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16145.916190                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 16145.916190                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16145.916190                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 16145.916190                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements           132334                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        30651.520219                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs             161905                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           164393                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             0.984866                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 26718.655997                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  2108.933972                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data  1823.930250                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.815389                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.064360                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.055662                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.935410                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        32059                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0          184                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1         3021                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2        28588                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3          209                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4           57                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.978363                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses          4067526                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses         4067526                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst        87933                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data        34250                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total         122183                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks       168931                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total       168931                       # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data        12616                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total        12616                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst        87933                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data        46866                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total          134799                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst        87933                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data        46866                       # number of overall hits
system.cpu.l2cache.overall_hits::total         134799                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst         7617                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data        27830                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total        35447                       # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       130789                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       130789                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst         7617                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       158619                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        166236                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         7617                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       158619                       # number of overall misses
system.cpu.l2cache.overall_misses::total       166236                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    567334000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data   2641860995                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   3209194995                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  13292879000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  13292879000                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    567334000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  15934739995                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  16502073995                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    567334000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  15934739995                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  16502073995                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst        95550                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data        62080                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total       157630                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks       168931                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total       168931                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       143405                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       143405                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst        95550                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data       205485                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total       301035                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst        95550                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data       205485                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total       301035                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.079717                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.448293                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.224875                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.912025                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.912025                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.079717                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.771925                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.552215                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.079717                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.771925                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.552215                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74482.604700                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 94928.530183                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 90535.023979                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 101636.062666                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 101636.062666                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74482.604700                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 100459.213556                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 99268.954950                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74482.604700                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 100459.213556                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 99268.954950                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks       114014                       # number of writebacks
system.cpu.l2cache.writebacks::total           114014                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         7617                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        27830                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total        35447                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       130789                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       130789                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         7617                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       158619                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       166236                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         7617                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       158619                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       166236                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    471133000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   2299062995                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   2770195995                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  11693000000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  11693000000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    471133000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  13992062995                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  14463195995                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    471133000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  13992062995                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  14463195995                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.079717                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.448293                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.224875                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.912025                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.912025                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.079717                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.771925                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.552215                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.079717                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.771925                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.552215                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61852.829198                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 82610.959217                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 78150.365193                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 89403.543111                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 89403.543111                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61852.829198                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 88211.771572                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 87003.994291                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61852.829198                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 88211.771572                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 87003.994291                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements            201389                       # number of replacements
system.cpu.dcache.tags.tagsinuse          4071.903515                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            34089462                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs            205485                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs            165.897569                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle         215961000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data  4071.903515                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.994117                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.994117                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           77                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1         2789                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2         1230                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses          71018847                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses         71018847                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data     20525187                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        20525187                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     13564218                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       13564218                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data           57                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total           57                       # number of LoadLockedReq hits
system.cpu.dcache.demand_hits::cpu.data      34089405                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         34089405                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     34089405                       # number of overall hits
system.cpu.dcache.overall_hits::total        34089405                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data       268059                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        268059                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      1049159                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      1049159                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data            1                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total            1                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data      1317218                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        1317218                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      1317218                       # number of overall misses
system.cpu.dcache.overall_misses::total       1317218                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  17086669746                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  17086669746                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  86915323054                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  86915323054                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data        92250                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total        92250                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 104001992800                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 104001992800                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 104001992800                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 104001992800                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     20793246                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     20793246                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     14613377                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     14613377                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data           58                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total           58                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     35406623                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     35406623                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     35406623                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     35406623                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.012892                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.012892                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.071794                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.071794                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.017241                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.017241                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.037203                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.037203                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.037203                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.037203                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63742.197598                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 63742.197598                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 82842.851326                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 82842.851326                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        92250                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        92250                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 78955.793802                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 78955.793802                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 78955.793802                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 78955.793802                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs      6406656                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets          254                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs            146327                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               2                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    43.783143                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          127                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       168931                       # number of writebacks
system.cpu.dcache.writebacks::total            168931                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       205979                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       205979                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data       905755                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total       905755                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      1111734                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      1111734                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      1111734                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      1111734                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data        62080                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total        62080                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       143404                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       143404                       # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data            1                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total            1                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data       205484                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total       205484                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data       205484                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total       205484                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   3049561754                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total   3049561754                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  13566762195                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  13566762195                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data        89750                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total        89750                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  16616323949                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  16616323949                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  16616323949                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  16616323949                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002986                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002986                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.009813                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.009813                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.017241                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.017241                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.005804                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.005804                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.005804                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.005804                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49123.095264                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49123.095264                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 94605.186710                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 94605.186710                       # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data        89750                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total        89750                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80864.320088                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 80864.320088                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80864.320088                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 80864.320088                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------