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|
---------- Begin Simulation Statistics ----------
sim_seconds 0.133635 # Number of seconds simulated
sim_ticks 133634727000 # Number of ticks simulated
final_tick 133634727000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1560477 # Simulator instruction rate (inst/s)
host_op_rate 1560477 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2360564466 # Simulator tick rate (ticks/s)
host_mem_usage 272464 # Number of bytes of host memory used
host_seconds 56.61 # Real time elapsed on the host
sim_insts 88340673 # Number of instructions simulated
sim_ops 88340673 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 432896 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 10136896 # Number of bytes read from this memory
system.physmem.bytes_read::total 10569792 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 432896 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 432896 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 7294848 # Number of bytes written to this memory
system.physmem.bytes_written::total 7294848 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 6764 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 158389 # Number of read requests responded to by this memory
system.physmem.num_reads::total 165153 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 113982 # Number of write requests responded to by this memory
system.physmem.num_writes::total 113982 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 3239397 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 75855253 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 79094650 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 3239397 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 3239397 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 54587966 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 54587966 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 54587966 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 3239397 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 75855253 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 133682617 # Total bandwidth to/from this memory (bytes/s)
system.membus.throughput 133682617 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 34272 # Transaction distribution
system.membus.trans_dist::ReadResp 34272 # Transaction distribution
system.membus.trans_dist::Writeback 113982 # Transaction distribution
system.membus.trans_dist::ReadExReq 130881 # Transaction distribution
system.membus.trans_dist::ReadExResp 130881 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 444288 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 444288 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17864640 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 17864640 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 17864640 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 1190991000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.9 # Layer utilization (%)
system.membus.respLayer1.occupancy 1486377000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 1.1 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 20276638 # DTB read hits
system.cpu.dtb.read_misses 90148 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 20366786 # DTB read accesses
system.cpu.dtb.write_hits 14613377 # DTB write hits
system.cpu.dtb.write_misses 7252 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 14620629 # DTB write accesses
system.cpu.dtb.data_hits 34890015 # DTB hits
system.cpu.dtb.data_misses 97400 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 34987415 # DTB accesses
system.cpu.itb.fetch_hits 88438074 # ITB hits
system.cpu.itb.fetch_misses 3934 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 88442008 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4583 # Number of system calls
system.cpu.numCycles 267269454 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 88340673 # Number of instructions committed
system.cpu.committedOps 88340673 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 78039444 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 267757 # Number of float alu accesses
system.cpu.num_func_calls 3321606 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 8920848 # number of instructions that are conditional controls
system.cpu.num_int_insts 78039444 # number of integer instructions
system.cpu.num_fp_insts 267757 # number of float instructions
system.cpu.num_int_register_reads 105931758 # number of times the integer registers were read
system.cpu.num_int_register_writes 52319251 # number of times the integer registers were written
system.cpu.num_fp_register_reads 229023 # number of times the floating registers were read
system.cpu.num_fp_register_writes 227630 # number of times the floating registers were written
system.cpu.num_mem_refs 34987415 # number of memory refs
system.cpu.num_load_insts 20366786 # Number of load instructions
system.cpu.num_store_insts 14620629 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 267269454 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.Branches 13754477 # Number of branches fetched
system.cpu.op_class::No_OpClass 8748916 9.89% 9.89% # Class of executed instruction
system.cpu.op_class::IntAlu 44394799 50.20% 60.09% # Class of executed instruction
system.cpu.op_class::IntMult 41101 0.05% 60.14% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 60.14% # Class of executed instruction
system.cpu.op_class::FloatAdd 114304 0.13% 60.27% # Class of executed instruction
system.cpu.op_class::FloatCmp 84 0.00% 60.27% # Class of executed instruction
system.cpu.op_class::FloatCvt 113640 0.13% 60.40% # Class of executed instruction
system.cpu.op_class::FloatMult 50 0.00% 60.40% # Class of executed instruction
system.cpu.op_class::FloatDiv 37764 0.04% 60.44% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::MemRead 20366786 23.03% 83.47% # Class of executed instruction
system.cpu.op_class::MemWrite 14620629 16.53% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 88438073 # Class of executed instruction
system.cpu.icache.tags.replacements 74391 # number of replacements
system.cpu.icache.tags.tagsinuse 1871.686406 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 88361638 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 76436 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 1156.021220 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 1871.686406 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.913909 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.913909 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 2045 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 104 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 191 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1708 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.998535 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 176952584 # Number of tag accesses
system.cpu.icache.tags.data_accesses 176952584 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 88361638 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 88361638 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 88361638 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 88361638 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 88361638 # number of overall hits
system.cpu.icache.overall_hits::total 88361638 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 76436 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 76436 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 76436 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 76436 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 76436 # number of overall misses
system.cpu.icache.overall_misses::total 76436 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 1278112000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 1278112000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 1278112000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 1278112000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 1278112000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 1278112000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 88438074 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 88438074 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 88438074 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 88438074 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 88438074 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 88438074 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000864 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000864 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000864 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000864 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000864 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000864 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16721.335496 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 16721.335496 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 16721.335496 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 16721.335496 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 16721.335496 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 16721.335496 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 76436 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 76436 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 76436 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 76436 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 76436 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 76436 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1125240000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 1125240000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1125240000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 1125240000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1125240000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 1125240000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000864 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000864 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000864 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14721.335496 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14721.335496 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14721.335496 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 14721.335496 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14721.335496 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 14721.335496 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 131235 # number of replacements
system.cpu.l2cache.tags.tagsinuse 30728.810101 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 142024 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 163291 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.869760 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 27298.448351 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1874.507766 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 1555.853984 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.833083 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.057205 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.047481 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.937769 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32056 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 655 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9976 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 21194 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 117 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978271 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 3900109 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 3900109 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst 69672 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 33258 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 102930 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 168375 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 168375 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 12697 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 12697 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 69672 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 45955 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 115627 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 69672 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 45955 # number of overall hits
system.cpu.l2cache.overall_hits::total 115627 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 6764 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 27508 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 34272 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 130881 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 130881 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 6764 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 158389 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 165153 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 6764 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 158389 # number of overall misses
system.cpu.l2cache.overall_misses::total 165153 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 352084000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1430874000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 1782958000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6805851000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 6805851000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 352084000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 8236725000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 8588809000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 352084000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 8236725000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 8588809000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 76436 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 60766 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 137202 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 168375 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 168375 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 143578 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 143578 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 76436 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 204344 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 280780 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 76436 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 204344 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 280780 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.088492 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.452687 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.249792 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911567 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.911567 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.088492 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.775110 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.588194 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.088492 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.775110 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.588194 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52052.631579 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52016.649702 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52023.751167 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.297981 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.297981 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52052.631579 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52003.137844 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52005.164908 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52052.631579 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52003.137844 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52005.164908 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 113982 # number of writebacks
system.cpu.l2cache.writebacks::total 113982 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 6764 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27508 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 34272 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130881 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 130881 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 6764 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 158389 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 165153 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 6764 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 158389 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 165153 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 270916000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1100778000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1371694000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5235279000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5235279000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 270916000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6336057000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 6606973000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 270916000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6336057000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 6606973000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.088492 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.452687 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.249792 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911567 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911567 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.088492 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775110 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.588194 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.088492 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775110 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.588194 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40052.631579 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40016.649702 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40023.751167 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.297981 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.297981 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40052.631579 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40003.137844 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40005.164908 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40052.631579 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40003.137844 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40005.164908 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements 200248 # number of replacements
system.cpu.dcache.tags.tagsinuse 4078.863631 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 34685671 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 204344 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 169.741568 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 936463000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 4078.863631 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.995816 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.995816 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 482 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 3562 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 69984374 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 69984374 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 20215872 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 20215872 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 14469799 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 14469799 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 34685671 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 34685671 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 34685671 # number of overall hits
system.cpu.dcache.overall_hits::total 34685671 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 60766 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 60766 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 143578 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 143578 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 204344 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 204344 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 204344 # number of overall misses
system.cpu.dcache.overall_misses::total 204344 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 1945752000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 1945752000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 7363555000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 7363555000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 9309307000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 9309307000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 9309307000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 9309307000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 34890015 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 34890015 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 34890015 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002997 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.002997 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009825 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.009825 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.005857 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.005857 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.005857 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.005857 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32020.406148 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 32020.406148 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 51286.095363 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 51286.095363 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 45557.036174 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 45557.036174 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 45557.036174 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 45557.036174 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 168375 # number of writebacks
system.cpu.dcache.writebacks::total 168375 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60766 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 60766 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143578 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 143578 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 204344 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 204344 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 204344 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 204344 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1824220000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 1824220000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7076399000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 7076399000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8900619000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 8900619000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8900619000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 8900619000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009825 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30020.406148 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30020.406148 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49286.095363 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49286.095363 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43557.036174 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 43557.036174 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43557.036174 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 43557.036174 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.throughput 215108158 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 137202 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 137202 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 168375 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 143578 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 143578 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 152872 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 577063 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 729935 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4891904 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23854016 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total 28745920 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus 28745920 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 392952500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 114654000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 306516000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
---------- End Simulation Statistics ----------
|
