path: root/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.057717                       # Number of seconds simulated
sim_ticks                                 57716694500                       # Number of ticks simulated
final_tick                                57716694500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 194770                       # Simulator instruction rate (inst/s)
host_op_rate                                   249082                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                              158520150                       # Simulator tick rate (ticks/s)
host_mem_usage                                 322420                       # Number of bytes of host memory used
host_seconds                                   364.10                       # Real time elapsed on the host
sim_insts                                    70915128                       # Number of instructions simulated
sim_ops                                      90690084                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst            324096                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           7923392                       # Number of bytes read from this memory
system.physmem.bytes_read::total              8247488                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       324096                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          324096                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      5372992                       # Number of bytes written to this memory
system.physmem.bytes_written::total           5372992                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst               5064                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             123803                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                128867                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           83953                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                83953                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst              5615290                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data            137280765                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total               142896056                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst         5615290                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total            5615290                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks          93092511                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total               93092511                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks          93092511                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst             5615290                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data           137280765                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              235988567                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        128867                       # Number of read requests accepted
system.physmem.writeReqs                        83953                       # Number of write requests accepted
system.physmem.readBursts                      128867                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                      83953                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                  8247040                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                       448                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   5371776                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                   8247488                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                5372992                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                        7                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                8159                       # Per bank write bursts
system.physmem.perBankRdBursts::1                8373                       # Per bank write bursts
system.physmem.perBankRdBursts::2                8230                       # Per bank write bursts
system.physmem.perBankRdBursts::3                8170                       # Per bank write bursts
system.physmem.perBankRdBursts::4                8318                       # Per bank write bursts
system.physmem.perBankRdBursts::5                8449                       # Per bank write bursts
system.physmem.perBankRdBursts::6                8089                       # Per bank write bursts
system.physmem.perBankRdBursts::7                7972                       # Per bank write bursts
system.physmem.perBankRdBursts::8                8072                       # Per bank write bursts
system.physmem.perBankRdBursts::9                7639                       # Per bank write bursts
system.physmem.perBankRdBursts::10               7818                       # Per bank write bursts
system.physmem.perBankRdBursts::11               7829                       # Per bank write bursts
system.physmem.perBankRdBursts::12               7882                       # Per bank write bursts
system.physmem.perBankRdBursts::13               7878                       # Per bank write bursts
system.physmem.perBankRdBursts::14               7976                       # Per bank write bursts
system.physmem.perBankRdBursts::15               8006                       # Per bank write bursts
system.physmem.perBankWrBursts::0                5185                       # Per bank write bursts
system.physmem.perBankWrBursts::1                5376                       # Per bank write bursts
system.physmem.perBankWrBursts::2                5285                       # Per bank write bursts
system.physmem.perBankWrBursts::3                5155                       # Per bank write bursts
system.physmem.perBankWrBursts::4                5266                       # Per bank write bursts
system.physmem.perBankWrBursts::5                5518                       # Per bank write bursts
system.physmem.perBankWrBursts::6                5200                       # Per bank write bursts
system.physmem.perBankWrBursts::7                5050                       # Per bank write bursts
system.physmem.perBankWrBursts::8                5033                       # Per bank write bursts
system.physmem.perBankWrBursts::9                5087                       # Per bank write bursts
system.physmem.perBankWrBursts::10               5254                       # Per bank write bursts
system.physmem.perBankWrBursts::11               5143                       # Per bank write bursts
system.physmem.perBankWrBursts::12               5343                       # Per bank write bursts
system.physmem.perBankWrBursts::13               5363                       # Per bank write bursts
system.physmem.perBankWrBursts::14               5451                       # Per bank write bursts
system.physmem.perBankWrBursts::15               5225                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                     57716659500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  128867                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                  83953                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    116721                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     12117                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                        22                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                      624                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                      639                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     4066                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     5054                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     5149                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     5174                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     5166                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     5175                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     5177                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     5199                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     5195                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     5213                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     5335                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     5261                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     5300                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     5730                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     5307                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     5162                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                       12                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        38389                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      354.703274                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     215.932875                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     335.531195                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          12049     31.39%     31.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255         8167     21.27%     52.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         4156     10.83%     63.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         2841      7.40%     70.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2531      6.59%     77.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1630      4.25%     81.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1300      3.39%     85.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1165      3.03%     88.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         4550     11.85%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          38389                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          5156                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        24.991854                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      361.399783                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023           5153     99.94%     99.94% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047            1      0.02%     99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::3072-4095            1      0.02%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::25600-26623            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            5156                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          5156                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        16.278898                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       16.261929                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        0.774840                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16               4519     87.65%     87.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17                  7      0.14%     87.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18                495      9.60%     97.38% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19                111      2.15%     99.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20                 19      0.37%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22                  3      0.06%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23                  2      0.04%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            5156                       # Writes before turning the bus around for reads
system.physmem.totQLat                     1645819000                       # Total ticks spent queuing
system.physmem.totMemAccLat                4061944000                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    644300000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       12772.15                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  31522.15                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                         142.89                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                          93.07                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                      142.90                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                       93.09                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           1.84                       # Data bus utilization in percentage
system.physmem.busUtilRead                       1.12                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.73                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.03                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        23.40                       # Average write queue length when enqueuing
system.physmem.readRowHits                     112172                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     62224                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   87.05                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  74.12                       # Row buffer hit rate for writes
system.physmem.avgGap                       271199.41                       # Average gap between requests
system.physmem.pageHitRate                      81.95                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  151063920                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                   82425750                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 512577000                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                272309040                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy             3769446720                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            11829284955                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy            24250601250                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy              40867708635                       # Total energy per rank (pJ)
system.physmem_0.averagePower              708.132582                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE    40213391000                       # Time in different power states
system.physmem_0.memoryStateTime::REF      1927120000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     15571447750                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  139058640                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                   75875250                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 492008400                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                271479600                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy             3769446720                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            11209873365                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy            24793944750                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy              40751686725                       # Total energy per rank (pJ)
system.physmem_1.averagePower              706.122220                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE    41121510500                       # Time in different power states
system.physmem_1.memoryStateTime::REF      1927120000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     14663764500                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu.branchPred.lookups                14827145                       # Number of BP lookups
system.cpu.branchPred.condPredicted           9920468                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect            395132                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups              9565987                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                 6746821                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             70.529272                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 1718856                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect                  3                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.walks                         0                       # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                 1946                       # Number of system calls
system.cpu.numCycles                        115433389                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                    70915128                       # Number of instructions committed
system.cpu.committedOps                      90690084                       # Number of ops (including micro ops) committed
system.cpu.discardedOps                       1146778                       # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
system.cpu.cpi                               1.627768                       # CPI: cycles per instruction
system.cpu.ipc                               0.614338                       # IPC: instructions per cycle
system.cpu.tickCycles                        96895866                       # Number of cycles that the object actually ticked
system.cpu.idleCycles                        18537523                       # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements            156436                       # number of replacements
system.cpu.dcache.tags.tagsinuse          4067.344190                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            42626825                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs            160532                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs            265.534753                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle         829717250                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data  4067.344190                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.993004                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.993004                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           44                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1         1141                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2         2911                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses          86020072                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses         86020072                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data     22868301                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        22868301                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     19642179                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       19642179                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data        84507                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total         84507                       # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data        15919                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total        15919                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data        15919                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total        15919                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      42510480                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         42510480                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     42594987                       # number of overall hits
system.cpu.dcache.overall_hits::total        42594987                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data        51533                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total         51533                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       207722                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       207722                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data        43690                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total        43690                       # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data       259255                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total         259255                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data       302945                       # number of overall misses
system.cpu.dcache.overall_misses::total        302945                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data   1474342937                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total   1474342937                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  16908501000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  16908501000                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  18382843937                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  18382843937                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  18382843937                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  18382843937                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     22919834                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     22919834                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     19849901                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     19849901                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data       128197                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total       128197                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data        15919                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total        15919                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data        15919                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total        15919                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     42769735                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     42769735                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     42897932                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     42897932                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.002248                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.002248                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.010465                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.010465                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.340804                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.340804                       # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.006062                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.006062                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.007062                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.007062                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28609.685774                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 28609.685774                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 81399.663974                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 81399.663974                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 70906.420077                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 70906.420077                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 60680.466543                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 60680.466543                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       128445                       # number of writebacks
system.cpu.dcache.writebacks::total            128445                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data        22036                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total        22036                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data       100688                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total       100688                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data       122724                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total       122724                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data       122724                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total       122724                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data        29497                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total        29497                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       107034                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       107034                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data        24001                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total        24001                       # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data       136531                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total       136531                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data       160532                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total       160532                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data    558577313                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total    558577313                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8440191000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   8440191000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1682073500                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1682073500                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data   8998768313                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total   8998768313                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  10680841813                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  10680841813                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.001287                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.001287                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.005392                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.005392                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.187220                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.187220                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.003192                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.003192                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.003742                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.003742                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18936.749941                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18936.749941                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78855.232917                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78855.232917                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 70083.475689                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 70083.475689                       # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65910.073998                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 65910.073998                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66534.035663                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 66534.035663                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements             42847                       # number of replacements
system.cpu.icache.tags.tagsinuse          1854.482229                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs            25082964                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs             44889                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs            558.777518                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst  1854.482229                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.905509                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.905509                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024         2042                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           81                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1           40                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3          916                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4         1005                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.997070                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses          50300597                       # Number of tag accesses
system.cpu.icache.tags.data_accesses         50300597                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst     25082964                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        25082964                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      25082964                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         25082964                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     25082964                       # number of overall hits
system.cpu.icache.overall_hits::total        25082964                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst        44890                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total         44890                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst        44890                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total          44890                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst        44890                       # number of overall misses
system.cpu.icache.overall_misses::total         44890                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    936252739                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    936252739                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    936252739                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    936252739                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    936252739                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    936252739                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     25127854                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     25127854                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     25127854                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     25127854                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     25127854                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     25127854                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.001786                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.001786                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.001786                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.001786                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.001786                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.001786                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20856.599220                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 20856.599220                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 20856.599220                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 20856.599220                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 20856.599220                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 20856.599220                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst        44890                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total        44890                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst        44890                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total        44890                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst        44890                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total        44890                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    867000761                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    867000761                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    867000761                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    867000761                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    867000761                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    867000761                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.001786                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.001786                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.001786                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.001786                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.001786                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.001786                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19313.895322                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19313.895322                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19313.895322                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 19313.895322                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19313.895322                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 19313.895322                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements            95728                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        29864.649447                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs              99882                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           126846                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             0.787427                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 26742.608070                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  1559.046569                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data  1562.994808                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.816120                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.047578                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.047699                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.911397                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        31118                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0          119                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1         1812                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2        12771                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3        15838                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4          578                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.949646                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses          2904816                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses         2904816                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst        39815                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data        31912                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total          71727                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks       128445                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total       128445                       # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data         4754                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total         4754                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst        39815                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data        36666                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total           76481                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst        39815                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data        36666                       # number of overall hits
system.cpu.l2cache.overall_hits::total          76481                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst         5075                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data        21586                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total        26661                       # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       102280                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       102280                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst         5075                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       123866                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        128941                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         5075                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       123866                       # number of overall misses
system.cpu.l2cache.overall_misses::total       128941                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    404023750                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data   1851742250                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   2255766000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   8283203500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   8283203500                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    404023750                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  10134945750                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  10538969500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    404023750                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  10134945750                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  10538969500                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst        44890                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data        53498                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total        98388                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks       128445                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total       128445                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       107034                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       107034                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst        44890                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data       160532                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total       205422                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst        44890                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data       160532                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total       205422                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.113054                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.403492                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.270978                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.955584                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.955584                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.113054                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.771597                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.627688                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.113054                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.771597                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.627688                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79610.591133                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 85784.408876                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 84609.204456                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80985.564138                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80985.564138                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79610.591133                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81821.853858                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 81734.820577                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79610.591133                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81821.853858                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 81734.820577                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        83953                       # number of writebacks
system.cpu.l2cache.writebacks::total            83953                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           10                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           63                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total           73                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst           10                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data           63                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           73                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst           10                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data           63                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           73                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         5065                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        21523                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total        26588                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       102280                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       102280                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         5065                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       123803                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       128868                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         5065                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       123803                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       128868                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    339808000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1578466750                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1918274750                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   7004628000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7004628000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    339808000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   8583094750                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total   8922902750                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    339808000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   8583094750                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total   8922902750                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.112831                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.402314                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.270236                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.955584                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.955584                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.112831                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.771204                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.627333                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.112831                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.771204                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.627333                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67089.437315                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 73338.602890                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 72148.140138                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68484.825968                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68484.825968                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67089.437315                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69328.649144                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69240.639647                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67089.437315                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69328.649144                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69240.639647                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq          98388                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp         98387                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback       128445                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       107034                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       107034                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        89779                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       449509                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total            539288                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2872896                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     18494528                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total           21367424                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples       333867                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1             333867    100.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total         333867                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy      295378500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.5                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy      68292739                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy     268237687                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.5                       # Layer utilization (%)
system.membus.trans_dist::ReadReq               26587                       # Transaction distribution
system.membus.trans_dist::ReadResp              26587                       # Transaction distribution
system.membus.trans_dist::Writeback             83953                       # Transaction distribution
system.membus.trans_dist::ReadExReq            102280                       # Transaction distribution
system.membus.trans_dist::ReadExResp           102280                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       341687                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 341687                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     13620480                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                13620480                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoop_fanout::samples            212820                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                  212820    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total              212820                       # Request fanout histogram
system.membus.reqLayer0.occupancy           578469000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               1.0                       # Layer utilization (%)
system.membus.respLayer1.occupancy          680054250                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              1.2                       # Layer utilization (%)

---------- End Simulation Statistics   ----------