blob: c949b9a6e6678c0190a8ad2f1830e0952ff304ed (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
|
---------- Begin Simulation Statistics ----------
sim_seconds 0.057847 # Number of seconds simulated
sim_ticks 57847312000 # Number of ticks simulated
final_tick 57847312000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 186854 # Simulator instruction rate (inst/s)
host_op_rate 238959 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 152421830 # Simulator tick rate (ticks/s)
host_mem_usage 261476 # Number of bytes of host memory used
host_seconds 379.52 # Real time elapsed on the host
sim_insts 70915127 # Number of instructions simulated
sim_ops 90690083 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 8247680 # Number of bytes read from this memory
system.physmem.bytes_read::total 8247680 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 324352 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 324352 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 5372864 # Number of bytes written to this memory
system.physmem.bytes_written::total 5372864 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 128870 # Number of read requests responded to by this memory
system.physmem.num_reads::total 128870 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 83951 # Number of write requests responded to by this memory
system.physmem.num_writes::total 83951 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 142576720 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 142576720 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 5607037 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 5607037 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 92880098 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 92880098 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 92880098 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 142576720 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 235456818 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 128870 # Number of read requests accepted
system.physmem.writeReqs 83951 # Number of write requests accepted
system.physmem.readBursts 128870 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 83951 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 8247360 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 320 # Total number of bytes read from write queue
system.physmem.bytesWritten 5370944 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 8247680 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 5372864 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 5 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 8158 # Per bank write bursts
system.physmem.perBankRdBursts::1 8375 # Per bank write bursts
system.physmem.perBankRdBursts::2 8229 # Per bank write bursts
system.physmem.perBankRdBursts::3 8171 # Per bank write bursts
system.physmem.perBankRdBursts::4 8319 # Per bank write bursts
system.physmem.perBankRdBursts::5 8450 # Per bank write bursts
system.physmem.perBankRdBursts::6 8089 # Per bank write bursts
system.physmem.perBankRdBursts::7 7970 # Per bank write bursts
system.physmem.perBankRdBursts::8 8071 # Per bank write bursts
system.physmem.perBankRdBursts::9 7641 # Per bank write bursts
system.physmem.perBankRdBursts::10 7819 # Per bank write bursts
system.physmem.perBankRdBursts::11 7830 # Per bank write bursts
system.physmem.perBankRdBursts::12 7881 # Per bank write bursts
system.physmem.perBankRdBursts::13 7879 # Per bank write bursts
system.physmem.perBankRdBursts::14 7977 # Per bank write bursts
system.physmem.perBankRdBursts::15 8006 # Per bank write bursts
system.physmem.perBankWrBursts::0 5181 # Per bank write bursts
system.physmem.perBankWrBursts::1 5376 # Per bank write bursts
system.physmem.perBankWrBursts::2 5285 # Per bank write bursts
system.physmem.perBankWrBursts::3 5155 # Per bank write bursts
system.physmem.perBankWrBursts::4 5266 # Per bank write bursts
system.physmem.perBankWrBursts::5 5517 # Per bank write bursts
system.physmem.perBankWrBursts::6 5198 # Per bank write bursts
system.physmem.perBankWrBursts::7 5047 # Per bank write bursts
system.physmem.perBankWrBursts::8 5033 # Per bank write bursts
system.physmem.perBankWrBursts::9 5087 # Per bank write bursts
system.physmem.perBankWrBursts::10 5251 # Per bank write bursts
system.physmem.perBankWrBursts::11 5143 # Per bank write bursts
system.physmem.perBankWrBursts::12 5343 # Per bank write bursts
system.physmem.perBankWrBursts::13 5363 # Per bank write bursts
system.physmem.perBankWrBursts::14 5451 # Per bank write bursts
system.physmem.perBankWrBursts::15 5225 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 57847280000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 128870 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 83951 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 126560 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 2283 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 22 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 620 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 634 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 4283 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 5143 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 5159 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 5165 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 5165 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 5166 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 5168 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 5180 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 5181 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 5171 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 5287 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 5241 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 5206 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 5744 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 5252 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 5160 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 8 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 38379 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 354.780687 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 215.561409 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 335.824723 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 12139 31.63% 31.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 8088 21.07% 52.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 4086 10.65% 63.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 2872 7.48% 70.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 2530 6.59% 77.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1664 4.34% 81.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 1273 3.32% 85.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 1227 3.20% 88.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 4500 11.73% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 38379 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 5156 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 24.981187 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 361.178240 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023 5153 99.94% 99.94% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::25600-26623 1 0.02% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 5156 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 5156 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 16.276377 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 16.259366 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 0.777117 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16 4528 87.82% 87.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17 7 0.14% 87.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18 480 9.31% 97.27% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19 121 2.35% 99.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20 14 0.27% 99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21 2 0.04% 99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22 2 0.04% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24 1 0.02% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::25 1 0.02% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 5156 # Writes before turning the bus around for reads
system.physmem.totQLat 1539171500 # Total ticks spent queuing
system.physmem.totMemAccLat 3955390250 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 644325000 # Total ticks spent in databus transfers
system.physmem.avgQLat 11944.06 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 30694.06 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 142.57 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 92.85 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 142.58 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 92.88 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 1.84 # Data bus utilization in percentage
system.physmem.busUtilRead 1.11 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.73 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing
system.physmem.avgWrQLen 23.48 # Average write queue length when enqueuing
system.physmem.readRowHits 112176 # Number of row buffer hits during reads
system.physmem.writeRowHits 62224 # Number of row buffer hits during writes
system.physmem.readRowHitRate 87.05 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 74.12 # Row buffer hit rate for writes
system.physmem.avgGap 271811.90 # Average gap between requests
system.physmem.pageHitRate 81.95 # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE 32236826000 # Time in different power states
system.physmem.memoryStateTime::REF 1931540000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem.memoryStateTime::ACT 23675959000 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem.actEnergy::0 151237800 # Energy for activate commands per rank (pJ)
system.physmem.actEnergy::1 138899880 # Energy for activate commands per rank (pJ)
system.physmem.preEnergy::0 82520625 # Energy for precharge commands per rank (pJ)
system.physmem.preEnergy::1 75788625 # Energy for precharge commands per rank (pJ)
system.physmem.readEnergy::0 512678400 # Energy for read commands per rank (pJ)
system.physmem.readEnergy::1 492078600 # Energy for read commands per rank (pJ)
system.physmem.writeEnergy::0 272322000 # Energy for write commands per rank (pJ)
system.physmem.writeEnergy::1 271486080 # Energy for write commands per rank (pJ)
system.physmem.refreshEnergy::0 3778092240 # Energy for refresh commands per rank (pJ)
system.physmem.refreshEnergy::1 3778092240 # Energy for refresh commands per rank (pJ)
system.physmem.actBackEnergy::0 11712850200 # Energy for active background per rank (pJ)
system.physmem.actBackEnergy::1 11277598770 # Energy for active background per rank (pJ)
system.physmem.preBackEnergy::0 24432156750 # Energy for precharge background per rank (pJ)
system.physmem.preBackEnergy::1 24813956250 # Energy for precharge background per rank (pJ)
system.physmem.totalEnergy::0 40941858015 # Total energy per rank (pJ)
system.physmem.totalEnergy::1 40847900445 # Total energy per rank (pJ)
system.physmem.averagePower::0 707.794027 # Core power per rank (mW)
system.physmem.averagePower::1 706.169709 # Core power per rank (mW)
system.cpu.branchPred.lookups 14825675 # Number of BP lookups
system.cpu.branchPred.condPredicted 9917897 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 395023 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 9456669 # Number of BTB lookups
system.cpu.branchPred.BTBHits 6745546 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 71.331100 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 1719567 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 3 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 1946 # Number of system calls
system.cpu.numCycles 115694624 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 70915127 # Number of instructions committed
system.cpu.committedOps 90690083 # Number of ops (including micro ops) committed
system.cpu.discardedOps 1146301 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 1.631452 # CPI: cycles per instruction
system.cpu.ipc 0.612951 # IPC: instructions per cycle
system.cpu.tickCycles 96938261 # Number of cycles that the object actually ticked
system.cpu.idleCycles 18756363 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements 156422 # number of replacements
system.cpu.dcache.tags.tagsinuse 4068.596798 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 42665450 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 160518 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 265.798540 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 784159000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.inst 4068.596798 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.inst 0.993310 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.993310 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 750 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 3296 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 86015580 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 86015580 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.inst 22989734 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 22989734 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.inst 19643878 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 19643878 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.inst 15919 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.inst 15919 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.inst 42633612 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 42633612 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.inst 42633612 # number of overall hits
system.cpu.dcache.overall_hits::total 42633612 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.inst 56058 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 56058 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.inst 206023 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 206023 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.inst 262081 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 262081 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.inst 262081 # number of overall misses
system.cpu.dcache.overall_misses::total 262081 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.inst 2156088187 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 2156088187 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.inst 15241867750 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 15241867750 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.inst 17397955937 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 17397955937 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.inst 17397955937 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 17397955937 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.inst 23045792 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 23045792 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.inst 19849901 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 15919 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.inst 15919 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.inst 42895693 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 42895693 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.inst 42895693 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 42895693 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.002432 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.002432 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.010379 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.010379 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.inst 0.006110 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.006110 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.inst 0.006110 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.006110 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 38461.739395 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 38461.739395 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 73981.389214 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 73981.389214 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66383.888710 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 66383.888710 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66383.888710 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 66383.888710 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 128433 # number of writebacks
system.cpu.dcache.writebacks::total 128433 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 2574 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 2574 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 98989 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 98989 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.inst 101563 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 101563 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.inst 101563 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 101563 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 53484 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 53484 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 107034 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 107034 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.inst 160518 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 160518 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.inst 160518 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 160518 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 1995361313 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 1995361313 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 7633992250 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 7633992250 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 9629353563 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 9629353563 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 9629353563 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 9629353563 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.002321 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002321 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.005392 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.003742 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.003742 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.003742 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 37307.630562 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 37307.630562 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 71323.058561 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71323.058561 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 59989.244589 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 59989.244589 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 59989.244589 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 59989.244589 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 42703 # number of replacements
system.cpu.icache.tags.tagsinuse 1858.978148 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 25082437 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 44745 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 560.564018 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 1858.978148 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.907704 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.907704 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 88 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 804 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1118 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 50299111 # Number of tag accesses
system.cpu.icache.tags.data_accesses 50299111 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 25082437 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 25082437 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 25082437 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 25082437 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 25082437 # number of overall hits
system.cpu.icache.overall_hits::total 25082437 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 44746 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 44746 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 44746 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 44746 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 44746 # number of overall misses
system.cpu.icache.overall_misses::total 44746 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 897678738 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 897678738 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 897678738 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 897678738 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 897678738 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 897678738 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 25127183 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 25127183 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 25127183 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 25127183 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 25127183 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 25127183 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001781 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.001781 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.001781 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.001781 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.001781 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.001781 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20061.653287 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 20061.653287 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 20061.653287 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 20061.653287 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 20061.653287 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 20061.653287 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 44746 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 44746 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 44746 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 44746 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 44746 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 44746 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 806263262 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 806263262 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 806263262 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 806263262 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 806263262 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 806263262 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001781 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001781 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001781 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.001781 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001781 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.001781 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18018.666741 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18018.666741 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18018.666741 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 18018.666741 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18018.666741 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 18018.666741 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 95732 # number of replacements
system.cpu.l2cache.tags.tagsinuse 29937.969910 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 99708 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 126850 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.786031 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 26706.762922 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 3231.206988 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.815026 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.098609 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.913634 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 31118 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 131 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1136 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9726 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 19542 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 583 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949646 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 2903460 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 2903460 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst 71567 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 71567 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 128433 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 128433 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.inst 4753 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 4753 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 76320 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 76320 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 76320 # number of overall hits
system.cpu.l2cache.overall_hits::total 76320 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 26663 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 26663 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.inst 102281 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 102281 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 128944 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 128944 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 128944 # number of overall misses
system.cpu.l2cache.overall_misses::total 128944 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1987300500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 1987300500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 7479393750 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 7479393750 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 9466694250 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 9466694250 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 9466694250 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 9466694250 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 98230 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 98230 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 128433 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 128433 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.inst 107034 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 107034 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 205264 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 205264 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 205264 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 205264 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.271434 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.271434 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.955594 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.955594 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.628186 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.628186 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.628186 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.628186 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74534.017177 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 74534.017177 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 73125.934924 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73125.934924 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73417.097732 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 73417.097732 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73417.097732 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 73417.097732 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 83951 # number of writebacks
system.cpu.l2cache.writebacks::total 83951 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 73 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 73 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 73 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 73 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 26590 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 26590 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 102281 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 102281 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 128871 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 128871 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 128871 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 128871 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1644904750 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1644904750 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 6188348750 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6188348750 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7833253500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 7833253500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7833253500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 7833253500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.270691 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.270691 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.955594 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955594 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.627831 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.627831 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.627831 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.627831 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61861.780745 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61861.780745 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 60503.404836 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60503.404836 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60783.679028 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60783.679028 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60783.679028 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60783.679028 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq 98230 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 98229 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 128433 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 107034 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 107034 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 89491 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 449469 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 538960 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2863680 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18492864 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 21356544 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 333697 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::5 333697 100.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 333697 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 295281500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 68080238 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 268447937 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%)
system.membus.trans_dist::ReadReq 26589 # Transaction distribution
system.membus.trans_dist::ReadResp 26589 # Transaction distribution
system.membus.trans_dist::Writeback 83951 # Transaction distribution
system.membus.trans_dist::ReadExReq 102281 # Transaction distribution
system.membus.trans_dist::ReadExResp 102281 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 341691 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 341691 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13620544 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 13620544 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 212821 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 212821 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 212821 # Request fanout histogram
system.membus.reqLayer0.occupancy 929388500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 1.6 # Layer utilization (%)
system.membus.respLayer1.occupancy 1213397000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 2.1 # Layer utilization (%)
---------- End Simulation Statistics ----------
|