path: root/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.057054                       # Number of seconds simulated
sim_ticks                                 57053790500                       # Number of ticks simulated
final_tick                                57053790500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 195523                       # Simulator instruction rate (inst/s)
host_op_rate                                   250045                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                              157305109                       # Simulator tick rate (ticks/s)
host_mem_usage                                 323528                       # Number of bytes of host memory used
host_seconds                                   362.70                       # Real time elapsed on the host
sim_insts                                    70915128                       # Number of instructions simulated
sim_ops                                      90690084                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst            319296                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           7924224                       # Number of bytes read from this memory
system.physmem.bytes_read::total              8243520                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       319296                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          319296                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      5514240                       # Number of bytes written to this memory
system.physmem.bytes_written::total           5514240                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst               4989                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             123816                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                128805                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           86160                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                86160                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst              5596403                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data            138890404                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total               144486807                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst         5596403                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total            5596403                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks          96649845                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total               96649845                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks          96649845                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst             5596403                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data           138890404                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              241136652                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        128805                       # Number of read requests accepted
system.physmem.writeReqs                        86160                       # Number of write requests accepted
system.physmem.readBursts                      128805                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                      86160                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                  8243200                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                       320                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   5512512                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                   8243520                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                5514240                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                        5                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                8145                       # Per bank write bursts
system.physmem.perBankRdBursts::1                8375                       # Per bank write bursts
system.physmem.perBankRdBursts::2                8247                       # Per bank write bursts
system.physmem.perBankRdBursts::3                8170                       # Per bank write bursts
system.physmem.perBankRdBursts::4                8318                       # Per bank write bursts
system.physmem.perBankRdBursts::5                8434                       # Per bank write bursts
system.physmem.perBankRdBursts::6                8084                       # Per bank write bursts
system.physmem.perBankRdBursts::7                7957                       # Per bank write bursts
system.physmem.perBankRdBursts::8                8058                       # Per bank write bursts
system.physmem.perBankRdBursts::9                7633                       # Per bank write bursts
system.physmem.perBankRdBursts::10               7816                       # Per bank write bursts
system.physmem.perBankRdBursts::11               7829                       # Per bank write bursts
system.physmem.perBankRdBursts::12               7882                       # Per bank write bursts
system.physmem.perBankRdBursts::13               7879                       # Per bank write bursts
system.physmem.perBankRdBursts::14               7977                       # Per bank write bursts
system.physmem.perBankRdBursts::15               7996                       # Per bank write bursts
system.physmem.perBankWrBursts::0                5393                       # Per bank write bursts
system.physmem.perBankWrBursts::1                5541                       # Per bank write bursts
system.physmem.perBankWrBursts::2                5463                       # Per bank write bursts
system.physmem.perBankWrBursts::3                5328                       # Per bank write bursts
system.physmem.perBankWrBursts::4                5352                       # Per bank write bursts
system.physmem.perBankWrBursts::5                5550                       # Per bank write bursts
system.physmem.perBankWrBursts::6                5247                       # Per bank write bursts
system.physmem.perBankWrBursts::7                5180                       # Per bank write bursts
system.physmem.perBankWrBursts::8                5155                       # Per bank write bursts
system.physmem.perBankWrBursts::9                5102                       # Per bank write bursts
system.physmem.perBankWrBursts::10               5289                       # Per bank write bursts
system.physmem.perBankWrBursts::11               5270                       # Per bank write bursts
system.physmem.perBankWrBursts::12               5531                       # Per bank write bursts
system.physmem.perBankWrBursts::13               5597                       # Per bank write bursts
system.physmem.perBankWrBursts::14               5703                       # Per bank write bursts
system.physmem.perBankWrBursts::15               5432                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                     57053759500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  128805                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                  86160                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    116563                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     12216                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                        21                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                      600                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                      606                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     4083                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     5179                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     5276                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     5314                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     5314                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     5322                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     5317                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     5327                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     5353                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     5371                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     5464                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     5434                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     5475                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     5912                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     5475                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     5307                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                       13                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        38707                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      355.314336                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     216.053807                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     335.949103                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          12175     31.45%     31.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255         8182     21.14%     52.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         4142     10.70%     63.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         2786      7.20%     70.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2727      7.05%     77.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1625      4.20%     81.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1301      3.36%     85.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1172      3.03%     88.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         4597     11.88%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          38707                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          5298                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        24.311061                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      351.967739                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023           5296     99.96%     99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-3071            1      0.02%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::24576-25599            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            5298                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          5297                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        16.259581                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       16.243681                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        0.749380                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16               4690     88.54%     88.54% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17                  4      0.08%     88.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18                472      8.91%     97.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19                106      2.00%     99.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20                 18      0.34%     99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21                  5      0.09%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22                  2      0.04%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            5297                       # Writes before turning the bus around for reads
system.physmem.totQLat                     1693807750                       # Total ticks spent queuing
system.physmem.totMemAccLat                4108807750                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    644000000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       13150.68                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  31900.68                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                         144.48                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                          96.62                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                      144.49                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                       96.65                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           1.88                       # Data bus utilization in percentage
system.physmem.busUtilRead                       1.13                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.75                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.03                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        23.52                       # Average write queue length when enqueuing
system.physmem.readRowHits                     112096                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     64121                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   87.03                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  74.42                       # Row buffer hit rate for writes
system.physmem.avgGap                       265409.53                       # Average gap between requests
system.physmem.pageHitRate                      81.98                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  151956000                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                   82912500                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 512405400                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                278951040                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy             3726219120                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            11612859660                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy            24043349250                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy              40408652970                       # Total energy per rank (pJ)
system.physmem_0.averagePower              708.301006                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE    39871864500                       # Time in different power states
system.physmem_0.memoryStateTime::REF      1905020000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     15273243000                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  140638680                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                   76737375                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 491797800                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                279151920                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy             3726219120                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            11026970910                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy            24557286750                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy              40298802555                       # Total energy per rank (pJ)
system.physmem_1.averagePower              706.375499                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE    40728832250                       # Time in different power states
system.physmem_1.memoryStateTime::REF      1905020000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     14416275250                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu.branchPred.lookups                14816555                       # Number of BP lookups
system.cpu.branchPred.condPredicted           9915062                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect            392110                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups              9527196                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                 6742365                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             70.769668                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 1716488                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect                  3                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.walks                         0                       # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                 1946                       # Number of system calls
system.cpu.numCycles                        114107581                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                    70915128                       # Number of instructions committed
system.cpu.committedOps                      90690084                       # Number of ops (including micro ops) committed
system.cpu.discardedOps                       1163698                       # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
system.cpu.cpi                               1.609072                       # CPI: cycles per instruction
system.cpu.ipc                               0.621476                       # IPC: instructions per cycle
system.cpu.tickCycles                        95702284                       # Number of cycles that the object actually ticked
system.cpu.idleCycles                        18405297                       # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements            156420                       # number of replacements
system.cpu.dcache.tags.tagsinuse          4067.153595                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            42625103                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs            160516                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs            265.550493                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle         823362500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data  4067.153595                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.992957                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.992957                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           47                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1         1109                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2         2940                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses          86018450                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses         86018450                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data     22867482                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        22867482                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     19642183                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       19642183                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data        83600                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total         83600                       # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data        15919                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total        15919                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data        15919                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total        15919                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      42509665                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         42509665                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     42593265                       # number of overall hits
system.cpu.dcache.overall_hits::total        42593265                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data        51591                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total         51591                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       207718                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       207718                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data        44555                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total        44555                       # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data       259309                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total         259309                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data       303864                       # number of overall misses
system.cpu.dcache.overall_misses::total        303864                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data   1486882500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total   1486882500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  16821632500                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  16821632500                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  18308515000                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  18308515000                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  18308515000                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  18308515000                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     22919073                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     22919073                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     19849901                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     19849901                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data       128155                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total       128155                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data        15919                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total        15919                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data        15919                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total        15919                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     42768974                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     42768974                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     42897129                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     42897129                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.002251                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.002251                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.010464                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.010464                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.347665                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.347665                       # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.006063                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.006063                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.007084                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.007084                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28820.579171                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 28820.579171                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80983.027470                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 80983.027470                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 70605.011781                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 70605.011781                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 60252.333281                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 60252.333281                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       128380                       # number of writebacks
system.cpu.dcache.writebacks::total            128380                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data        22097                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total        22097                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data       100690                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total       100690                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data       122787                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total       122787                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data       122787                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total       122787                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data        29494                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total        29494                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       107028                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       107028                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data        23994                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total        23994                       # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data       136522                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total       136522                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data       160516                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total       160516                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data    572555000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total    572555000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8494060500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   8494060500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1717129000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1717129000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data   9066615500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total   9066615500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  10783744500                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  10783744500                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.001287                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.001287                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.005392                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.005392                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.187226                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.187226                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.003192                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.003192                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.003742                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.003742                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19412.592392                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19412.592392                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79362.975109                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79362.975109                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 71564.932900                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 71564.932900                       # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66411.387908                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 66411.387908                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67181.742007                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 67181.742007                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements             42980                       # number of replacements
system.cpu.icache.tags.tagsinuse          1852.974873                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs            24976744                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs             45022                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs            554.767536                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst  1852.974873                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.904773                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.904773                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024         2042                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           82                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1           39                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3          914                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4         1007                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.997070                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses          50088556                       # Number of tag accesses
system.cpu.icache.tags.data_accesses         50088556                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst     24976744                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        24976744                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      24976744                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         24976744                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     24976744                       # number of overall hits
system.cpu.icache.overall_hits::total        24976744                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst        45023                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total         45023                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst        45023                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total          45023                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst        45023                       # number of overall misses
system.cpu.icache.overall_misses::total         45023                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    929482000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    929482000                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    929482000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    929482000                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    929482000                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    929482000                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     25021767                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     25021767                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     25021767                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     25021767                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     25021767                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     25021767                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.001799                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.001799                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.001799                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.001799                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.001799                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.001799                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20644.603869                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 20644.603869                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 20644.603869                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 20644.603869                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 20644.603869                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 20644.603869                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst        45023                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total        45023                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst        45023                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total        45023                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst        45023                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total        45023                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    884460000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    884460000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    884460000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    884460000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    884460000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    884460000                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.001799                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.001799                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.001799                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.001799                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.001799                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.001799                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19644.626080                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19644.626080                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19644.626080                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 19644.626080                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19644.626080                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 19644.626080                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements            95667                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        29860.905352                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs             161834                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           126786                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             1.276434                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 26582.278991                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  1621.458035                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data  1657.168326                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.811227                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.049483                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.050573                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.911283                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        31119                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0          123                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1         1810                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2        12715                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3        15870                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4          601                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.949677                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses          3410862                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses         3410862                       # Number of data accesses
system.cpu.l2cache.Writeback_hits::writebacks       128380                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total       128380                       # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data         4747                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total         4747                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        40023                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total        40023                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data        31889                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total        31889                       # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst        40023                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data        36636                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total           76659                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst        40023                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data        36636                       # number of overall hits
system.cpu.l2cache.overall_hits::total          76659                       # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data       102281                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       102281                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         5000                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total         5000                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data        21599                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total        21599                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst         5000                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       123880                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        128880                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         5000                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       123880                       # number of overall misses
system.cpu.l2cache.overall_misses::total       128880                       # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   8283634000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   8283634000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    396631500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total    396631500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   1874203500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total   1874203500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    396631500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  10157837500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  10554469000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    396631500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  10157837500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  10554469000                       # number of overall miss cycles
system.cpu.l2cache.Writeback_accesses::writebacks       128380                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total       128380                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       107028                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       107028                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        45023                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total        45023                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data        53488                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total        53488                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst        45023                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data       160516                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total       205539                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst        45023                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data       160516                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total       205539                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.955647                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.955647                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.111054                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.111054                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.403810                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.403810                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.111054                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.771761                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.627034                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.111054                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.771761                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.627034                       # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80988.981336                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80988.981336                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79326.300000                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79326.300000                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86772.697810                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86772.697810                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79326.300000                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81997.396674                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 81893.769398                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79326.300000                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81997.396674                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 81893.769398                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        86160                       # number of writebacks
system.cpu.l2cache.writebacks::total            86160                       # number of writebacks
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst           10                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total           10                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           64                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total           64                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst           10                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data           64                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           74                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst           10                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data           64                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           74                       # number of overall MSHR hits
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks         1376                       # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total         1376                       # number of CleanEvict MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       102281                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       102281                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         4990                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total         4990                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        21535                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total        21535                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         4990                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       123816                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       128806                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         4990                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       123816                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       128806                       # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   7260824000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7260824000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    346082000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    346082000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   1654286500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   1654286500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    346082000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   8915110500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total   9261192500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    346082000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   8915110500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total   9261192500                       # number of overall MSHR miss cycles
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.955647                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.955647                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.110832                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.110832                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.402614                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.402614                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.110832                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.771362                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.626674                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.110832                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.771362                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.626674                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70988.981336                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70988.981336                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69355.110220                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69355.110220                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76818.504760                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76818.504760                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69355.110220                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72002.895425                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71900.319085                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69355.110220                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72002.895425                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71900.319085                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadResp         98510                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback       214540                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict        72719                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       107028                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       107028                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq        45023                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq        53488                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       129456                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       473213                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total            602669                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2881408                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     18489344                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total           21370752                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                       95667                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples       500606                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        1.191102                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.393170                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1             404939     80.89%     80.89% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2              95667     19.11%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total         500606                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy      330849500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.6                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy      67538489                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy     240805936                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.4                       # Layer utilization (%)
system.membus.trans_dist::ReadResp              26524                       # Transaction distribution
system.membus.trans_dist::Writeback             86160                       # Transaction distribution
system.membus.trans_dist::CleanEvict             7518                       # Transaction distribution
system.membus.trans_dist::ReadExReq            102281                       # Transaction distribution
system.membus.trans_dist::ReadExResp           102281                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq         26524                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       351288                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 351288                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     13757760                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                13757760                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoop_fanout::samples            222483                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                  222483    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total              222483                       # Request fanout histogram
system.membus.reqLayer0.occupancy           591579500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               1.0                       # Layer utilization (%)
system.membus.respLayer1.occupancy          679724750                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              1.2                       # Layer utilization (%)

---------- End Simulation Statistics   ----------