path: root/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.033709                       # Number of seconds simulated
sim_ticks                                 33708718000                       # Number of ticks simulated
final_tick                                33708718000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  58097                       # Simulator instruction rate (inst/s)
host_op_rate                                    74299                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               27618733                       # Simulator tick rate (ticks/s)
host_mem_usage                                 312228                       # Number of bytes of host memory used
host_seconds                                  1220.50                       # Real time elapsed on the host
sim_insts                                    70907652                       # Number of instructions simulated
sim_ops                                      90682607                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst            642112                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           2851904                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.l2cache.prefetcher      6180288                       # Number of bytes read from this memory
system.physmem.bytes_read::total              9674304                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       642112                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          642112                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      6216192                       # Number of bytes written to this memory
system.physmem.bytes_written::total           6216192                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst              10033                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data              44561                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.l2cache.prefetcher        96567                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                151161                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           97128                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                97128                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst             19048841                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             84604345                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.l2cache.prefetcher    183343905                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total               286997091                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst        19048841                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total           19048841                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks         184409030                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total              184409030                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks         184409030                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst            19048841                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            84604345                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.l2cache.prefetcher    183343905                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              471406121                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        151162                       # Number of read requests accepted
system.physmem.writeReqs                        97128                       # Number of write requests accepted
system.physmem.readBursts                      151162                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                      97128                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                  9665216                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      9152                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   6214528                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                   9674368                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                6216192                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      143                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                9070                       # Per bank write bursts
system.physmem.perBankRdBursts::1                9361                       # Per bank write bursts
system.physmem.perBankRdBursts::2                9561                       # Per bank write bursts
system.physmem.perBankRdBursts::3               11292                       # Per bank write bursts
system.physmem.perBankRdBursts::4               10590                       # Per bank write bursts
system.physmem.perBankRdBursts::5               10416                       # Per bank write bursts
system.physmem.perBankRdBursts::6                9949                       # Per bank write bursts
system.physmem.perBankRdBursts::7                8975                       # Per bank write bursts
system.physmem.perBankRdBursts::8                9423                       # Per bank write bursts
system.physmem.perBankRdBursts::9                9187                       # Per bank write bursts
system.physmem.perBankRdBursts::10               9162                       # Per bank write bursts
system.physmem.perBankRdBursts::11               8879                       # Per bank write bursts
system.physmem.perBankRdBursts::12               8652                       # Per bank write bursts
system.physmem.perBankRdBursts::13               8689                       # Per bank write bursts
system.physmem.perBankRdBursts::14               8733                       # Per bank write bursts
system.physmem.perBankRdBursts::15               9080                       # Per bank write bursts
system.physmem.perBankWrBursts::0                5971                       # Per bank write bursts
system.physmem.perBankWrBursts::1                6177                       # Per bank write bursts
system.physmem.perBankWrBursts::2                6109                       # Per bank write bursts
system.physmem.perBankWrBursts::3                6172                       # Per bank write bursts
system.physmem.perBankWrBursts::4                6049                       # Per bank write bursts
system.physmem.perBankWrBursts::5                6259                       # Per bank write bursts
system.physmem.perBankWrBursts::6                6017                       # Per bank write bursts
system.physmem.perBankWrBursts::7                5953                       # Per bank write bursts
system.physmem.perBankWrBursts::8                5939                       # Per bank write bursts
system.physmem.perBankWrBursts::9                6100                       # Per bank write bursts
system.physmem.perBankWrBursts::10               6208                       # Per bank write bursts
system.physmem.perBankWrBursts::11               5866                       # Per bank write bursts
system.physmem.perBankWrBursts::12               6052                       # Per bank write bursts
system.physmem.perBankWrBursts::13               6067                       # Per bank write bursts
system.physmem.perBankWrBursts::14               6159                       # Per bank write bursts
system.physmem.perBankWrBursts::15               6004                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                     33708706500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  151162                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                  97128                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                     48274                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     54259                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     13865                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                     10322                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      6132                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      5295                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      4724                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      4390                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      3645                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                        73                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                       33                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        6                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     1199                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     1243                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     1720                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     2271                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     2935                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     3759                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     4746                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     5409                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     5932                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     6426                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     6856                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     7461                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     8097                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     8693                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     9095                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     7779                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     6737                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     6264                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      232                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      117                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                       50                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                       30                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                       23                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                       16                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                       10                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        7                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        6                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        94915                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      167.290734                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     105.391717                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     236.347458                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          59184     62.35%     62.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        22349     23.55%     85.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         4070      4.29%     90.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         1460      1.54%     91.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639          942      0.99%     92.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767          824      0.87%     93.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895          583      0.61%     94.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023          753      0.79%     95.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         4750      5.00%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          94915                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          5848                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        25.821990                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      198.480384                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-511            5847     99.98%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::14848-15359            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            5848                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          5848                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        16.604309                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       16.557483                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        1.326112                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16               4590     78.49%     78.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17                 34      0.58%     79.07% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18                732     12.52%     91.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19                206      3.52%     95.11% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20                140      2.39%     97.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21                 85      1.45%     98.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22                 32      0.55%     99.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23                 13      0.22%     99.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24                  5      0.09%     99.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::25                  7      0.12%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26                  1      0.02%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::27                  1      0.02%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28                  1      0.02%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::30                  1      0.02%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            5848                       # Writes before turning the bus around for reads
system.physmem.totQLat                     6766168330                       # Total ticks spent queuing
system.physmem.totMemAccLat                9597774580                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    755095000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       44803.42                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  63553.42                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                         286.73                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                         184.36                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                      287.00                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                      184.41                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           3.68                       # Data bus utilization in percentage
system.physmem.busUtilRead                       2.24                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      1.44                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.45                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        24.44                       # Average write queue length when enqueuing
system.physmem.readRowHits                     120218                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     32977                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   79.60                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  33.95                       # Row buffer hit rate for writes
system.physmem.avgGap                       135763.45                       # Average gap between requests
system.physmem.pageHitRate                      61.74                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  372428280                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  203209875                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 617682000                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                315563040                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy             2201556240                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            14512366440                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy             7494015750                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy              25716821625                       # Total energy per rank (pJ)
system.physmem_0.averagePower              762.953400                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE    12364292410                       # Time in different power states
system.physmem_0.memoryStateTime::REF      1125540000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     20217117590                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  345038400                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  188265000                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 559977600                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                313554240                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy             2201556240                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            13559944320                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy             8329473750                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy              25497809550                       # Total energy per rank (pJ)
system.physmem_1.averagePower              756.455863                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE    13760038430                       # Time in different power states
system.physmem_1.memoryStateTime::REF      1125540000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     18821462070                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu.branchPred.lookups                17213709                       # Number of BP lookups
system.cpu.branchPred.condPredicted          11523003                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect            650148                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups              9341134                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                 7678896                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             82.205180                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 1872990                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect             101556                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.walks                         0                       # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                 1946                       # Number of system calls
system.cpu.numCycles                         67417437                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles            5107349                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                       88247579                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    17213709                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches            9551886                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                      60722717                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 1326923                       # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles                 4938                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles            27                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles        12869                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                  22781060                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                 69770                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples           66511361                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              1.678949                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             1.300919                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                 20706181     31.13%     31.13% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  8267608     12.43%     43.56% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                  9211127     13.85%     57.41% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                 28326445     42.59%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total             66511361                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.255330                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        1.308973                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                  8663293                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              20135580                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                  31585821                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               5633203                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                 493464                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved              3182521                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                171963                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts              101430430                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts               3050546                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                 493464                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 13424917                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                 5969682                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles         834240                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                  32240480                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              13548578                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts               99223336                       # Number of instructions processed by rename
system.cpu.rename.SquashedInsts                980873                       # Number of squashed instructions processed by rename
system.cpu.rename.ROBFullEvents               3826325                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                  67087                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents                4382425                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents                5163178                       # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands           103933922                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups             457817395                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups        115439825                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups               550                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps              93629369                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                 10304553                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts              18670                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts          18666                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  12721444                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             24327620                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            22002844                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           1418421                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores          2362163                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                   98185716                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded               34529                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                  94914966                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            694952                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined         7537638                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined     20282691                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved            743                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples      66511361                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         1.427049                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.152183                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0            18195190     27.36%     27.36% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            17483152     26.29%     53.64% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2            17116175     25.73%     79.38% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3            11668879     17.54%     96.92% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4             2046998      3.08%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5                 967      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total        66511361                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                 6715190     22.43%     22.43% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                     42      0.00%     22.43% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     22.43% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     22.43% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     22.43% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     22.43% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     22.43% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     22.43% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     22.43% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     22.43% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     22.43% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     22.43% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     22.43% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     22.43% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     22.43% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     22.43% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     22.43% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     22.43% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     22.43% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     22.43% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     22.43% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     22.43% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     22.43% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     22.43% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     22.43% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     22.43% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     22.43% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     22.43% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     22.43% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead               11181767     37.35%     59.78% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite              12039186     40.22%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu              49504183     52.16%     52.16% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                89872      0.09%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                  31      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               1      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              8      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             24074068     25.36%     77.61% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite            21246803     22.39%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total               94914966                       # Type of FU issued
system.cpu.iq.rate                           1.407870                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                    29936185                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.315400                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads          286972221                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         105769455                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses     93478190                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                 209                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes                248                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses           59                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              124851032                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                     119                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          1366282                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      1461358                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses         2098                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        12063                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      1447106                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads       140885                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked        185939                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                 493464                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                  630348                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                519071                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts            98230120                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              24327620                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             22002844                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts              18609                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                   1657                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                514382                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          12063                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         303781                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       221600                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts               525381                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts              93994405                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              23766194                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts            920561                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                          9875                       # number of nop insts executed
system.cpu.iew.exec_refs                     44755394                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 14253394                       # Number of branches executed
system.cpu.iew.exec_stores                   20989200                       # Number of stores executed
system.cpu.iew.exec_rate                     1.394215                       # Inst execution rate
system.cpu.iew.wb_sent                       93600457                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                      93478249                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                  44984526                       # num instructions producing a value
system.cpu.iew.wb_consumers                  76573166                       # num instructions consuming a value
system.cpu.iew.wb_rate                       1.386559                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.587471                       # average fanout of values written-back
system.cpu.commit.commitSquashedInsts         6555355                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls           33786                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts            480151                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples     65449475                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.385621                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.157530                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0     31837500     48.64%     48.64% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     16816023     25.69%     74.34% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2      4347616      6.64%     80.98% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3      4166544      6.37%     87.35% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      1933514      2.95%     90.30% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      1257718      1.92%     92.22% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6       744905      1.14%     93.36% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7       580044      0.89%     94.25% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      3765611      5.75%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total     65449475                       # Number of insts commited each cycle
system.cpu.commit.committedInsts             70913204                       # Number of instructions committed
system.cpu.commit.committedOps               90688159                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       43422000                       # Number of memory references committed
system.cpu.commit.loads                      22866262                       # Number of loads committed
system.cpu.commit.membars                       15920                       # Number of memory barriers committed
system.cpu.commit.branches                   13741468                       # Number of branches committed
system.cpu.commit.fp_insts                         56                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                  81528527                       # Number of committed integer instructions.
system.cpu.commit.function_calls              1679850                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu         47186033     52.03%     52.03% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult           80119      0.09%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv                0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd              0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp              0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt              0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv              0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc            7      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead        22866262     25.21%     77.33% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite       20555738     22.67%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total          90688159                       # Class of committed instruction
system.cpu.commit.bw_lim_events               3765611                       # number cycles where commit BW limit reached
system.cpu.rob.rob_reads                    158902079                       # The number of ROB reads
system.cpu.rob.rob_writes                   195550630                       # The number of ROB writes
system.cpu.timesIdled                           26501                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                          906076                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                    70907652                       # Number of Instructions Simulated
system.cpu.committedOps                      90682607                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               0.950778                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.950778                       # CPI: Total CPI of All Threads
system.cpu.ipc                               1.051770                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         1.051770                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                102290676                       # number of integer regfile reads
system.cpu.int_regfile_writes                56801575                       # number of integer regfile writes
system.cpu.fp_regfile_reads                        38                       # number of floating regfile reads
system.cpu.fp_regfile_writes                       22                       # number of floating regfile writes
system.cpu.cc_regfile_reads                 346161860                       # number of cc regfile reads
system.cpu.cc_regfile_writes                 38808202                       # number of cc regfile writes
system.cpu.misc_regfile_reads                44217642                       # number of misc regfile reads
system.cpu.misc_regfile_writes                  31840                       # number of misc regfile writes
system.cpu.dcache.tags.replacements            485010                       # number of replacements
system.cpu.dcache.tags.tagsinuse           510.749644                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            40413326                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs            485522                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             83.236858                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle         153371500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   510.749644                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.997558                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.997558                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           56                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          456                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses          84616114                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses         84616114                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data     21490425                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        21490425                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     18831304                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       18831304                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data        60283                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total         60283                       # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data        15350                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total        15350                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data        15919                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total        15919                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      40321729                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         40321729                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     40382012                       # number of overall hits
system.cpu.dcache.overall_hits::total        40382012                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data       564289                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        564289                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      1018597                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      1018597                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data        68553                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total        68553                       # number of SoftPFReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data          576                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total          576                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data      1582886                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        1582886                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      1651439                       # number of overall misses
system.cpu.dcache.overall_misses::total       1651439                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data   9271463500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total   9271463500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  14268416431                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  14268416431                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data      5543500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total      5543500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  23539879931                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  23539879931                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  23539879931                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  23539879931                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     22054714                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     22054714                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     19849901                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     19849901                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data       128836                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total       128836                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data        15926                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total        15926                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data        15919                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total        15919                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     41904615                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     41904615                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     42033451                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     42033451                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.025586                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.025586                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.051315                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.051315                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.532095                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.532095                       # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.036167                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.036167                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.037774                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.037774                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.039289                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.039289                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16430.345975                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 16430.345975                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14007.911304                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 14007.911304                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data  9624.131944                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total  9624.131944                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 14871.494176                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 14871.494176                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 14254.162540                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 14254.162540                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs           63                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets      2905402                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                11                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets          131245                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs     5.727273                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets    22.137240                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       485010                       # number of writebacks
system.cpu.dcache.writebacks::total            485010                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       264882                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       264882                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data       870061                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total       870061                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data          576                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total          576                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      1134943                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      1134943                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      1134943                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      1134943                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       299407                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       299407                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       148536                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       148536                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data        37590                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total        37590                       # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data       447943                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total       447943                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data       485533                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total       485533                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   3623952500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total   3623952500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   2306335972                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   2306335972                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1883780500                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1883780500                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data   5930288472                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total   5930288472                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data   7814068972                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total   7814068972                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.013576                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.013576                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.007483                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.007483                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.291766                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.291766                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.010690                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.010690                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.011551                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.011551                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12103.766779                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12103.766779                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15527.117817                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15527.117817                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50113.873371                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50113.873371                       # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13238.935472                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 13238.935472                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16093.795833                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 16093.795833                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements            322968                       # number of replacements
system.cpu.icache.tags.tagsinuse           510.276903                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs            22446876                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs            323480                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs             69.391851                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle        1134274500                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   510.276903                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.996635                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.996635                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           88                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1           58                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2           21                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3          338                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4            7                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses          45885393                       # Number of tag accesses
system.cpu.icache.tags.data_accesses         45885393                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst     22446876                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        22446876                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      22446876                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         22446876                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     22446876                       # number of overall hits
system.cpu.icache.overall_hits::total        22446876                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst       334075                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total        334075                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst       334075                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total         334075                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst       334075                       # number of overall misses
system.cpu.icache.overall_misses::total        334075                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst   3448429403                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total   3448429403                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst   3448429403                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total   3448429403                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst   3448429403                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total   3448429403                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     22780951                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     22780951                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     22780951                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     22780951                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     22780951                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     22780951                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.014665                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.014665                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.014665                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.014665                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.014665                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.014665                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10322.321045                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 10322.321045                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 10322.321045                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 10322.321045                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 10322.321045                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 10322.321045                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs       262312                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets           50                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs             16368                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               2                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    16.025904                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets           25                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.writebacks::writebacks       322968                       # number of writebacks
system.cpu.icache.writebacks::total            322968                       # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst        10583                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total        10583                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst        10583                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total        10583                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst        10583                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total        10583                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst       323492                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total       323492                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst       323492                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total       323492                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst       323492                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total       323492                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   3173672438                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total   3173672438                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst   3173672438                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total   3173672438                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst   3173672438                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total   3173672438                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.014200                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.014200                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.014200                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.014200                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.014200                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.014200                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  9810.667460                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  9810.667460                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  9810.667460                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total  9810.667460                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  9810.667460                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total  9810.667460                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.prefetcher.num_hwpf_issued       822850                       # number of hwpf issued
system.cpu.l2cache.prefetcher.pfIdentified       826406                       # number of prefetch candidates identified
system.cpu.l2cache.prefetcher.pfBufferHit         3117                       # number of redundant prefetches already in prefetch queue
system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu.l2cache.prefetcher.pfSpanPage        78938                       # number of prefetches not generated due to page crossing
system.cpu.l2cache.tags.replacements           127914                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        15989.309751                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            1181667                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           144275                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             8.190379                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 15893.511070                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher    95.798681                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.970063                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.005847                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.975910                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1022           28                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024        16333                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::1            8                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::2            1                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::3           12                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::4            7                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0          136                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1         2736                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2        12138                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3          528                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4          795                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1022     0.001709                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.996887                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         24987971                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        24987971                       # Number of data accesses
system.cpu.l2cache.WritebackDirty_hits::writebacks       259400                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total       259400                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks       468713                       # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total       468713                       # number of WritebackClean hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data            1                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total            1                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       137243                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       137243                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst       313417                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total       313417                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data       300447                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total       300447                       # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst       313417                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data       437690                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total          751107                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst       313417                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data       437690                       # number of overall hits
system.cpu.l2cache.overall_hits::total         751107                       # number of overall hits
system.cpu.l2cache.UpgradeReq_misses::cpu.data           10                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total           10                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data        11329                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total        11329                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        10064                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total        10064                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data        36503                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total        36503                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst        10064                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data        47832                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total         57896                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst        10064                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data        47832                       # number of overall misses
system.cpu.l2cache.overall_misses::total        57896                       # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   1187627500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   1187627500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    761841000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total    761841000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   2998033500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total   2998033500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    761841000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data   4185661000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total   4947502000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    761841000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data   4185661000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total   4947502000                       # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks       259400                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total       259400                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks       468713                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total       468713                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data           11                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total           11                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       148572                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       148572                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst       323481                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total       323481                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       336950                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total       336950                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst       323481                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data       485522                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total       809003                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst       323481                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data       485522                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total       809003                       # number of overall (read+write) accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.909091                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.909091                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.076253                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.076253                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.031112                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.031112                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.108334                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.108334                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.031112                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.098517                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.071565                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.031112                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.098517                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.071565                       # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 104830.744108                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 104830.744108                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75699.622417                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75699.622417                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82131.153604                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82131.153604                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75699.622417                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87507.547249                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 85454.988255                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75699.622417                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87507.547249                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 85454.988255                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        97128                       # number of writebacks
system.cpu.l2cache.writebacks::total            97128                       # number of writebacks
system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data         3171                       # number of ReadExReq MSHR hits
system.cpu.l2cache.ReadExReq_mshr_hits::total         3171                       # number of ReadExReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst           30                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total           30                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data          100                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total          100                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst           30                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data         3271                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total         3301                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst           30                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data         3271                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total         3301                       # number of overall MSHR hits
system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher       112673                       # number of HardPFReq MSHR misses
system.cpu.l2cache.HardPFReq_mshr_misses::total       112673                       # number of HardPFReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           10                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total           10                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         8158                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total         8158                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        10034                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total        10034                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        36403                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total        36403                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        10034                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data        44561                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total        54595                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        10034                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data        44561                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher       112673                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       167268                       # number of overall MSHR misses
system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher  10413466023                       # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_latency::total  10413466023                       # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       149500                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       149500                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    654073000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    654073000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    699673000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    699673000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   2773387500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   2773387500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    699673000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   3427460500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total   4127133500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    699673000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   3427460500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher  10413466023                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  14540599523                       # number of overall MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.909091                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.909091                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.054909                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.054909                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.031019                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.031019                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.108037                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.108037                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.031019                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.091780                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.067484                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.031019                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.091780                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.206758                       # mshr miss rate for overall accesses
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 92422.017901                       # average HardPFReq mshr miss latency
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 92422.017901                       # average HardPFReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        14950                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        14950                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80175.655798                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80175.655798                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69730.217261                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69730.217261                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76185.685246                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76185.685246                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69730.217261                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76916.148650                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75595.448301                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69730.217261                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76916.148650                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 92422.017901                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86929.953864                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.snoop_filter.tot_requests      1617003                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests       808019                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests        79877                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops        65377                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops        56343                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops         9034                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp        660441                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty       356528                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean       548578                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict        77222                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::HardPFReq       142341                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq           11                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp           11                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       148572                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       148572                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq       323492                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq       336950                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       969940                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      1456076                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           2426016                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     41372672                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     62114048                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          103486720                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                      316702                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples      1125716                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        0.137094                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.366537                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0             980421     87.09%     87.09% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1             136261     12.10%     99.20% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2               9034      0.80%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        1125716                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy     1616479500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          4.8                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy     485683604                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          1.4                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy     728543988                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          2.2                       # Layer utilization (%)
system.membus.trans_dist::ReadResp             143003                       # Transaction distribution
system.membus.trans_dist::WritebackDirty        97128                       # Transaction distribution
system.membus.trans_dist::CleanEvict            27951                       # Transaction distribution
system.membus.trans_dist::UpgradeReq               10                       # Transaction distribution
system.membus.trans_dist::ReadExReq              8158                       # Transaction distribution
system.membus.trans_dist::ReadExResp             8158                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        143004                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       427412                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 427412                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15890496                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                15890496                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoop_fanout::samples            276251                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                  276251    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total              276251                       # Request fanout histogram
system.membus.reqLayer0.occupancy           745073302                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               2.2                       # Layer utilization (%)
system.membus.respLayer1.occupancy          789293648                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              2.3                       # Layer utilization (%)

---------- End Simulation Statistics   ----------