path: root/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.026765                       # Number of seconds simulated
sim_ticks                                 26765004500                       # Number of ticks simulated
final_tick                                26765004500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 102307                       # Simulator instruction rate (inst/s)
host_op_rate                                   145187                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               38617115                       # Simulator tick rate (ticks/s)
host_mem_usage                                 251228                       # Number of bytes of host memory used
host_seconds                                   693.09                       # Real time elapsed on the host
sim_insts                                    70907629                       # Number of instructions simulated
sim_ops                                     100626876                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst            297792                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           7944704                       # Number of bytes read from this memory
system.physmem.bytes_read::total              8242496                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       297792                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          297792                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      5372160                       # Number of bytes written to this memory
system.physmem.bytes_written::total           5372160                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst               4653                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             124136                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                128789                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           83940                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                83940                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst             11126170                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data            296831783                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total               307957953                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst        11126170                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total           11126170                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks         200715827                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total              200715827                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks         200715827                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst            11126170                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data           296831783                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              508673780                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        128790                       # Total number of read requests accepted by DRAM controller
system.physmem.writeReqs                        83940                       # Total number of write requests accepted by DRAM controller
system.physmem.readBursts                      128790                       # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
system.physmem.writeBursts                      83940                       # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
system.physmem.bytesRead                      8242496                       # Total number of bytes read from memory
system.physmem.bytesWritten                   5372160                       # Total number of bytes written to memory
system.physmem.bytesConsumedRd                8242496                       # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr                5372160                       # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ                        3                       # Number of DRAM read bursts serviced by write Q
system.physmem.neitherReadNorWrite                321                       # Reqs where no action is needed
system.physmem.perBankRdReqs::0                  8146                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::1                  8397                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::2                  8248                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::3                  8159                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::4                  8298                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::5                  8449                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::6                  8089                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::7                  7961                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::8                  8063                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::9                  7615                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::10                 7784                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::11                 7815                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::12                 7883                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::13                 7888                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::14                 7978                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::15                 8014                       # Track reads on a per bank basis
system.physmem.perBankWrReqs::0                  5181                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::1                  5378                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::2                  5287                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::3                  5156                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::4                  5264                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::5                  5519                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::6                  5206                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::7                  5049                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::8                  5030                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::9                  5091                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::10                 5253                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::11                 5143                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::12                 5342                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::13                 5363                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::14                 5451                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::15                 5227                       # Track writes on a per bank basis
system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
system.physmem.numWrRetry                           0                       # Number of times wr buffer was full causing retry
system.physmem.totGap                     26764988000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
system.physmem.readPktSize::2                       0                       # Categorize read packet sizes
system.physmem.readPktSize::3                       0                       # Categorize read packet sizes
system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
system.physmem.readPktSize::6                  128790                       # Categorize read packet sizes
system.physmem.writePktSize::0                      0                       # Categorize write packet sizes
system.physmem.writePktSize::1                      0                       # Categorize write packet sizes
system.physmem.writePktSize::2                      0                       # Categorize write packet sizes
system.physmem.writePktSize::3                      0                       # Categorize write packet sizes
system.physmem.writePktSize::4                      0                       # Categorize write packet sizes
system.physmem.writePktSize::5                      0                       # Categorize write packet sizes
system.physmem.writePktSize::6                  83940                       # Categorize write packet sizes
system.physmem.rdQLenPdf::0                     76190                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     50560                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                      1965                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                        62                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                        10                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                      3592                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                      3644                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                      3649                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                      3650                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                      3650                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                      3650                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                      3650                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                      3650                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                      3650                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                      3650                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                     3650                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                     3650                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                     3650                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                     3649                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                     3649                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     3649                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     3649                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     3649                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     3649                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     3649                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     3649                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     3649                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     3649                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                       58                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        6                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        34959                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      389.285277                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     179.799947                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     855.459025                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::64-65          13425     38.40%     38.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-129         5427     15.52%     53.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192-193         3113      8.90%     62.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-257         2218      6.34%     69.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320-321         1684      4.82%     73.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-385         1324      3.79%     77.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448-449         1016      2.91%     80.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-513          832      2.38%     83.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576-577          675      1.93%     85.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-641          524      1.50%     86.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704-705          431      1.23%     87.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-769          550      1.57%     89.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832-833          311      0.89%     90.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-897          325      0.93%     91.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960-961          173      0.49%     91.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1025          178      0.51%     92.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088-1089          117      0.33%     92.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152-1153          209      0.60%     93.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216-1217          130      0.37%     93.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280-1281          238      0.68%     94.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344-1345          111      0.32%     94.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408-1409          314      0.90%     95.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472-1473          120      0.34%     95.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536-1537          318      0.91%     96.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600-1601           69      0.20%     96.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664-1665          140      0.40%     97.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728-1729           41      0.12%     97.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1792-1793           97      0.28%     97.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856-1857           29      0.08%     97.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920-1921           65      0.19%     97.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984-1985           25      0.07%     97.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2048-2049           42      0.12%     98.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112-2113           12      0.03%     98.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176-2177           31      0.09%     98.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240-2241           18      0.05%     98.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304-2305           26      0.07%     98.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368-2369            8      0.02%     98.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2432-2433           33      0.09%     98.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496-2497           11      0.03%     98.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2560-2561           15      0.04%     98.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2624-2625           11      0.03%     98.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688-2689           15      0.04%     98.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2752-2753            8      0.02%     98.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816-2817           11      0.03%     98.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880-2881            9      0.03%     98.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2944-2945           15      0.04%     98.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3008-3009            9      0.03%     98.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3072-3073           11      0.03%     98.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3136-3137            6      0.02%     98.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3200-3201            5      0.01%     98.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3264-3265            3      0.01%     98.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3328-3329            7      0.02%     98.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3392-3393            7      0.02%     98.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456-3457            3      0.01%     98.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3520-3521            2      0.01%     98.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3584-3585            4      0.01%     98.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3648-3649            3      0.01%     98.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3712-3713            6      0.02%     98.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3776-3777            3      0.01%     98.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3840-3841            9      0.03%     98.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3904-3905            3      0.01%     98.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3968-3969            3      0.01%     98.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4032-4033            4      0.01%     98.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4096-4097            3      0.01%     98.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4160-4161            4      0.01%     98.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4224-4225            4      0.01%     98.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4288-4289            2      0.01%     98.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4352-4353            3      0.01%     98.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4416-4417            2      0.01%     98.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4480-4481            1      0.00%     98.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4544-4545            5      0.01%     98.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4608-4609            4      0.01%     99.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4672-4673            2      0.01%     99.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4736-4737            5      0.01%     99.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4800-4801            3      0.01%     99.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4864-4865            2      0.01%     99.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4992-4993            2      0.01%     99.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5056-5057            3      0.01%     99.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5120-5121            3      0.01%     99.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5184-5185            2      0.01%     99.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5248-5249            2      0.01%     99.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5312-5313            2      0.01%     99.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5376-5377            1      0.00%     99.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5440-5441            1      0.00%     99.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5504-5505            1      0.00%     99.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5568-5569            4      0.01%     99.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5632-5633            1      0.00%     99.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5696-5697            3      0.01%     99.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5760-5761            3      0.01%     99.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5824-5825            2      0.01%     99.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5888-5889            5      0.01%     99.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5952-5953            2      0.01%     99.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6016-6017            3      0.01%     99.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6080-6081            1      0.00%     99.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6144-6145            3      0.01%     99.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6208-6209            4      0.01%     99.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6400-6401            6      0.02%     99.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6464-6465            1      0.00%     99.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6528-6529            1      0.00%     99.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6592-6593            2      0.01%     99.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6656-6657            2      0.01%     99.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6720-6721            1      0.00%     99.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6784-6785            2      0.01%     99.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6848-6849            3      0.01%     99.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6912-6913            1      0.00%     99.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6976-6977            2      0.01%     99.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7040-7041            1      0.00%     99.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7168-7169            1      0.00%     99.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7296-7297            3      0.01%     99.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7360-7361            1      0.00%     99.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7424-7425            1      0.00%     99.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7488-7489            3      0.01%     99.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7552-7553            1      0.00%     99.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7616-7617            2      0.01%     99.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7680-7681            2      0.01%     99.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7744-7745            2      0.01%     99.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7808-7809            3      0.01%     99.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7872-7873            2      0.01%     99.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7936-7937            1      0.00%     99.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8000-8001            1      0.00%     99.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8064-8065            3      0.01%     99.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8128-8129            2      0.01%     99.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8192-8193          239      0.68%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          34959                       # Bytes accessed per row activation
system.physmem.totQLat                     2852295000                       # Total cycles spent in queuing delays
system.physmem.totMemAccLat                4861110000                       # Sum of mem lat for all requests
system.physmem.totBusLat                    643935000                       # Total cycles spent in databus access
system.physmem.totBankLat                  1364880000                       # Total cycles spent in bank access
system.physmem.avgQLat                       22147.38                       # Average queueing delay per request
system.physmem.avgBankLat                    10597.96                       # Average bank access latency per request
system.physmem.avgBusLat                      5000.00                       # Average bus latency per request
system.physmem.avgMemAccLat                  37745.35                       # Average memory access latency
system.physmem.avgRdBW                         307.96                       # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW                         200.72                       # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW                 307.96                       # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW                 200.72                       # Average consumed write bandwidth in MB/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MB/s
system.physmem.busUtil                           3.97                       # Data bus utilization in percentage
system.physmem.avgRdQLen                         0.18                       # Average read queue length over time
system.physmem.avgWrQLen                        10.24                       # Average write queue length over time
system.physmem.readRowHits                     120249                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     57506                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   93.37                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  68.51                       # Row buffer hit rate for writes
system.physmem.avgGap                       125816.71                       # Average gap between requests
system.membus.throughput                    508673780                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq               26538                       # Transaction distribution
system.membus.trans_dist::ReadResp              26537                       # Transaction distribution
system.membus.trans_dist::Writeback             83940                       # Transaction distribution
system.membus.trans_dist::UpgradeReq              321                       # Transaction distribution
system.membus.trans_dist::UpgradeResp             321                       # Transaction distribution
system.membus.trans_dist::ReadExReq            102252                       # Transaction distribution
system.membus.trans_dist::ReadExResp           102252                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       342161                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 342161                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     13614656                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total            13614656                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus               13614656                       # Total data (bytes)
system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy           935941500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               3.5                       # Layer utilization (%)
system.membus.respLayer1.occupancy         1207011429                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              4.5                       # Layer utilization (%)
system.cpu.branchPred.lookups                16635237                       # Number of BP lookups
system.cpu.branchPred.condPredicted          12768503                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect            604840                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             10652885                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                 7773045                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             72.966572                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 1823659                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect             113448                       # Number of incorrect RAS predictions.
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                 1946                       # Number of system calls
system.cpu.numCycles                         53530010                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles           12549473                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                       85279503                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    16635237                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches            9596704                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                      21206249                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 2379470                       # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles               10773225                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                   64                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles           477                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles           35                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                  11686664                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                178212                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples           46277294                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              2.580240                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.332526                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                 25091643     54.22%     54.22% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  2136768      4.62%     58.84% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                  1963962      4.24%     63.08% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                  2042989      4.41%     67.50% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  1466847      3.17%     70.67% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                  1383026      2.99%     73.65% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                   957932      2.07%     75.72% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                  1190240      2.57%     78.30% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                 10043887     21.70%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total             46277294                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.310765                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        1.593116                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 14640784                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles               9115289                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                  19504792                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               1371825                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                1644604                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved              3334519                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                105037                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts              116943845                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                363315                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                1644604                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 16350397                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                 2675070                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles        1001661                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                  19117578                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles               5487984                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              115077475                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                   183                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                  17134                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents               4627273                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents              285                       # Number of times there has been no free registers
system.cpu.rename.RenamedOperands           115384718                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups             530174580                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups        530166885                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups              7695                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps              99132672                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                 16252046                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts              20256                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts          20253                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  13031784                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             29643166                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            22451729                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           3891559                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores          4392801                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  111618845                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded               35897                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 107291250                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            275974                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        10887740                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined     26073816                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved           2111                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples      46277294                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         2.318443                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.990403                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0            11003161     23.78%     23.78% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1             8115395     17.54%     41.31% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2             7436608     16.07%     57.38% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3             7096880     15.34%     72.72% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4             5407297     11.68%     84.40% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5             3935038      8.50%     92.91% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6             1843993      3.98%     96.89% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7              867713      1.88%     98.77% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8              571209      1.23%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total        46277294                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                  113414      4.57%      4.57% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%      4.57% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%      4.57% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     2      0.00%      4.57% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%      4.57% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%      4.57% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%      4.57% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%      4.57% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      4.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%      4.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      4.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%      4.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%      4.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%      4.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%      4.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%      4.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      4.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%      4.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      4.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      4.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      4.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      4.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      4.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      4.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      4.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      4.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      4.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      4.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      4.57% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                1362149     54.91%     59.48% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite               1005332     40.52%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu              56660345     52.81%     52.81% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                91595      0.09%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                 269      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              7      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             28911335     26.95%     79.84% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite            21627699     20.16%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              107291250                       # Type of FU issued
system.cpu.iq.rate                           2.004320                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                     2480897                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.023123                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads          263615967                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         122570490                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses    105600159                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                 698                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes               1174                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses          216                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              109771796                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                     351                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          2179165                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      2336058                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses         6530                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        30281                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      1895991                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads           33                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked           805                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                1644604                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                 1147402                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                 47438                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           111664541                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            286964                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              29643166                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             22451729                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts              19977                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                   6774                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                  4975                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          30281                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         393124                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       181749                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts               574873                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             106260947                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              28610039                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           1030303                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                          9799                       # number of nop insts executed
system.cpu.iew.exec_refs                     49952901                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 14605114                       # Number of branches executed
system.cpu.iew.exec_stores                   21342862                       # Number of stores executed
system.cpu.iew.exec_rate                     1.985072                       # Inst execution rate
system.cpu.iew.wb_sent                      105821179                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                     105600375                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                  53334269                       # num instructions producing a value
system.cpu.iew.wb_consumers                 103952809                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.972732                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.513062                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts        11033009                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls           33786                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts            501673                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples     44632690                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     2.254680                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.761954                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0     15532654     34.80%     34.80% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     11684135     26.18%     60.98% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2      3462025      7.76%     68.74% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3      2877014      6.45%     75.18% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      1854993      4.16%     79.34% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      1951437      4.37%     83.71% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6       690877      1.55%     85.26% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7       565658      1.27%     86.53% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      6013897     13.47%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total     44632690                       # Number of insts commited each cycle
system.cpu.commit.committedInsts             70913181                       # Number of instructions committed
system.cpu.commit.committedOps              100632428                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       47862846                       # Number of memory references committed
system.cpu.commit.loads                      27307108                       # Number of loads committed
system.cpu.commit.membars                       15920                       # Number of memory barriers committed
system.cpu.commit.branches                   13741485                       # Number of branches committed
system.cpu.commit.fp_insts                         56                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                  91472779                       # Number of committed integer instructions.
system.cpu.commit.function_calls              1679850                       # Number of function calls committed.
system.cpu.commit.bw_lim_events               6013897                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                    150258931                       # The number of ROB reads
system.cpu.rob.rob_writes                   224984633                       # The number of ROB writes
system.cpu.timesIdled                           80350                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                         7252716                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                    70907629                       # Number of Instructions Simulated
system.cpu.committedOps                     100626876                       # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total              70907629                       # Number of Instructions Simulated
system.cpu.cpi                               0.754926                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.754926                       # CPI: Total CPI of All Threads
system.cpu.ipc                               1.324633                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         1.324633                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                511766096                       # number of integer regfile reads
system.cpu.int_regfile_writes               103375635                       # number of integer regfile writes
system.cpu.fp_regfile_reads                      1160                       # number of floating regfile reads
system.cpu.fp_regfile_writes                     1012                       # number of floating regfile writes
system.cpu.misc_regfile_reads                49188390                       # number of misc regfile reads
system.cpu.misc_regfile_writes                  31840                       # number of misc regfile writes
system.cpu.toL2Bus.throughput               771895107                       # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq          86668                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp         86666                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback       129110                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq          336                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp          336                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       107033                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       107033                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        61963                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       454719                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total            516682                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1966784                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     18660992                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total       20627776                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus          20627776                       # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus        32000                       # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy      290686995                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          1.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy      47827231                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.2                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy     262412261                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          1.0                       # Layer utilization (%)
system.cpu.icache.tags.replacements             28871                       # number of replacements
system.cpu.icache.tags.tagsinuse          1809.449271                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs            11651662                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs             30904                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs            377.027634                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst  1809.449271                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.883520                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.883520                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst     11651673                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        11651673                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      11651673                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         11651673                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     11651673                       # number of overall hits
system.cpu.icache.overall_hits::total        11651673                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst        34991                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total         34991                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst        34991                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total          34991                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst        34991                       # number of overall misses
system.cpu.icache.overall_misses::total         34991                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    840169228                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    840169228                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    840169228                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    840169228                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    840169228                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    840169228                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     11686664                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     11686664                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     11686664                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     11686664                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     11686664                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     11686664                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.002994                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.002994                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.002994                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.002994                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.002994                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.002994                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24011.009345                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 24011.009345                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 24011.009345                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 24011.009345                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 24011.009345                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 24011.009345                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs         1080                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                23                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    46.956522                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst         3759                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total         3759                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst         3759                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total         3759                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst         3759                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total         3759                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst        31232                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total        31232                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst        31232                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total        31232                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst        31232                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total        31232                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    684118269                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    684118269                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    684118269                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    684118269                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    684118269                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    684118269                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.002672                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.002672                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.002672                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.002672                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.002672                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.002672                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21904.401543                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21904.401543                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21904.401543                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 21904.401543                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21904.401543                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 21904.401543                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements            95660                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        29916.504006                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs              88398                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           126774                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             0.697288                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 26705.369214                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  1366.053749                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data  1845.081043                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.814983                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.041689                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.056307                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.912979                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst        26062                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data        33492                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total          59554                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks       129110                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total       129110                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data           16                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total           16                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data         4780                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total         4780                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst        26062                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data        38272                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total           64334                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst        26062                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data        38272                       # number of overall hits
system.cpu.l2cache.overall_hits::total          64334                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst         4670                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data        21944                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total        26614                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data          320                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total          320                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       102253                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       102253                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst         4670                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       124197                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        128867                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         4670                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       124197                       # number of overall misses
system.cpu.l2cache.overall_misses::total       128867                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    391521000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data   1869704500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   2261225500                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data        22999                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total        22999                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   8377475499                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   8377475499                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    391521000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  10247179999                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  10638700999                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    391521000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  10247179999                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  10638700999                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst        30732                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data        55436                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total        86168                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks       129110                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total       129110                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data          336                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total          336                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       107033                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       107033                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst        30732                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data       162469                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total       193201                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst        30732                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data       162469                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total       193201                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.151959                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.395844                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.308862                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.952381                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.952381                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.955341                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.955341                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.151959                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.764435                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.667010                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.151959                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.764435                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.667010                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 83837.473233                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 85203.449690                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 84963.759675                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data    71.871875                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total    71.871875                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81928.896942                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81928.896942                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83837.473233                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82507.467966                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 82555.665911                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83837.473233                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82507.467966                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 82555.665911                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        83940                       # number of writebacks
system.cpu.l2cache.writebacks::total            83940                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           17                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           59                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total           76                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst           17                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data           59                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           76                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst           17                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data           59                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           76                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         4653                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        21885                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total        26538                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data          320                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total          320                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       102253                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       102253                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         4653                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       124138                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       128791                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         4653                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       124138                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       128791                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    331760500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1590135750                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1921896250                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data      3200320                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total      3200320                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   7097849501                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7097849501                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    331760500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   8687985251                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total   9019745751                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    331760500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   8687985251                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total   9019745751                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.151406                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.394780                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.307980                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.952381                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.952381                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.955341                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.955341                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.151406                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.764072                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.666617                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.151406                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.764072                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.666617                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 71300.343864                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 72658.704592                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 72420.538473                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        10001                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        10001                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69414.584423                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69414.584423                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71300.343864                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69986.508974                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70033.975596                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71300.343864                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69986.508974                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70033.975596                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements            158372                       # number of replacements
system.cpu.dcache.tags.tagsinuse          4069.400137                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            44374327                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs            162468                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs            273.126566                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle         354003250                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data  4069.400137                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.993506                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.993506                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data     26075013                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        26075013                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     18266800                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       18266800                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data        15987                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total        15987                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data        15919                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total        15919                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      44341813                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         44341813                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     44341813                       # number of overall hits
system.cpu.dcache.overall_hits::total        44341813                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data       125377                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        125377                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      1583101                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      1583101                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data           42                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total           42                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data      1708478                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        1708478                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      1708478                       # number of overall misses
system.cpu.dcache.overall_misses::total       1708478                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data   5199394222                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total   5199394222                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 124981048011                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 124981048011                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       861250                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total       861250                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 130180442233                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 130180442233                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 130180442233                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 130180442233                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     26200390                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     26200390                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     19849901                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     19849901                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data        16029                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total        16029                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data        15919                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total        15919                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     46050291                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     46050291                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     46050291                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     46050291                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.004785                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.004785                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.079754                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.079754                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.002620                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.002620                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.037100                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.037100                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.037100                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.037100                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41470.080015                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 41470.080015                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 78946.983175                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 78946.983175                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 20505.952381                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 20505.952381                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 76196.733135                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 76196.733135                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 76196.733135                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 76196.733135                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs         9105                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets         1249                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs               129                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets              16                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    70.581395                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets    78.062500                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       129110                       # number of writebacks
system.cpu.dcache.writebacks::total            129110                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data        69907                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total        69907                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1475766                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total      1475766                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data           42                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total           42                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      1545673                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      1545673                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      1545673                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      1545673                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data        55470                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total        55470                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       107335                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       107335                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data       162805                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total       162805                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data       162805                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total       162805                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   2262652309                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total   2262652309                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8543267922                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   8543267922                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  10805920231                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  10805920231                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  10805920231                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  10805920231                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002117                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002117                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.005407                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.005407                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.003535                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.003535                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.003535                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.003535                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40790.559023                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40790.559023                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79594.427931                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79594.427931                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66373.392899                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 66373.392899                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66373.392899                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 66373.392899                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------