blob: f26f3a3895348df945bf08895220bffbc9a16110 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
|
---------- Begin Simulation Statistics ----------
sim_seconds 0.024460 # Number of seconds simulated
sim_ticks 24460150500 # Number of ticks simulated
final_tick 24460150500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 167024 # Simulator instruction rate (inst/s)
host_op_rate 237012 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 57603012 # Simulator tick rate (ticks/s)
host_mem_usage 242500 # Number of bytes of host memory used
host_seconds 424.63 # Real time elapsed on the host
sim_insts 70923824 # Number of instructions simulated
sim_ops 100643071 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 326976 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 8028736 # Number of bytes read from this memory
system.physmem.bytes_read::total 8355712 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 326976 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 326976 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 5417152 # Number of bytes written to this memory
system.physmem.bytes_written::total 5417152 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 5109 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 125449 # Number of read requests responded to by this memory
system.physmem.num_reads::total 130558 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 84643 # Number of write requests responded to by this memory
system.physmem.num_writes::total 84643 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 13367702 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 328237392 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 341605094 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 13367702 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 13367702 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 221468466 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 221468466 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 221468466 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 13367702 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 328237392 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 563073559 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 1946 # Number of system calls
system.cpu.numCycles 48920302 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 16960531 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 12985874 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 661473 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 11570513 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 7976664 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 1883015 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 115088 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 12843999 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 87580035 # Number of instructions fetch has processed
system.cpu.fetch.Branches 16960531 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 9859679 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 21787094 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 2782746 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 10982319 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 56 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 606 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 12079139 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 221673 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 47647021 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.582724 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.336366 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 25881368 54.32% 54.32% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 2178299 4.57% 58.89% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 2007274 4.21% 63.10% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 2021463 4.24% 67.35% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 1548956 3.25% 70.60% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 1412983 2.97% 73.56% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 995678 2.09% 75.65% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 1240946 2.60% 78.26% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 10360054 21.74% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 47647021 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.346697 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.790259 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 15031484 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 9298191 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 19969978 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 1421734 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 1925634 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 3462876 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 109476 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 120212842 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 378015 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 1925634 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 16795731 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 2963104 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 805180 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 19544890 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 5612482 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 117675747 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 86 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 12709 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 4780104 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 263 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 117787272 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 541948309 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 541940540 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 7769 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 99158584 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 18628688 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 37002 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 36987 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 13169886 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 30082364 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 22781735 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 3607820 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 4315548 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 113341575 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 51734 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 108469975 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 351751 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 12575588 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 30093615 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 14709 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 47647021 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 2.276532 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.995144 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 11903537 24.98% 24.98% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 8354851 17.53% 42.52% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 7454693 15.65% 58.16% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 7158692 15.02% 73.19% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 5519097 11.58% 84.77% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 3907609 8.20% 92.97% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 1895733 3.98% 96.95% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 881641 1.85% 98.80% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 571168 1.20% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 47647021 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 112989 4.45% 4.45% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 4.45% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 4.45% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 2 0.00% 4.45% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.45% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.45% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 4.45% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.45% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.45% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.45% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.45% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.45% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.45% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.45% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.45% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 4.45% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.45% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 4.45% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.45% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.45% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.45% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.45% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.45% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.45% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.45% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.45% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.45% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.45% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.45% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 1419251 55.85% 60.30% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 1008989 39.70% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 57363382 52.88% 52.88% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 91507 0.08% 52.97% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.97% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 228 0.00% 52.97% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.97% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.97% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.97% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.97% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.97% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.97% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.97% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.97% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.97% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.97% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.97% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.97% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.97% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.97% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.97% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.97% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.97% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.97% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.97% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.97% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.97% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.97% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.97% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.97% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.97% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 29217041 26.94% 79.90% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 21797810 20.10% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 108469975 # Type of FU issued
system.cpu.iq.rate 2.217279 # Inst issue rate
system.cpu.iq.fu_busy_cnt 2541231 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.023428 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 267479180 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 125995514 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 106424512 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 773 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 1272 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 187 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 111010818 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 388 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 2214998 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 2772017 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 7458 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 29087 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 2222758 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 51 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 49 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 1925634 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 929341 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 37355 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 113473181 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 343640 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 30082364 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 22781735 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 35157 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 2560 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 3541 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 29087 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 428613 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 264355 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 692968 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 107247329 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 28841677 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 1222646 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 79872 # number of nop insts executed
system.cpu.iew.exec_refs 50315882 # number of memory reference insts executed
system.cpu.iew.exec_branches 14663606 # Number of branches executed
system.cpu.iew.exec_stores 21474205 # Number of stores executed
system.cpu.iew.exec_rate 2.192287 # Inst execution rate
system.cpu.iew.wb_sent 106761196 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 106424699 # cumulative count of insts written-back
system.cpu.iew.wb_producers 53424049 # num instructions producing a value
system.cpu.iew.wb_consumers 103788661 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 2.175471 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.514739 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 70929376 # The number of committed instructions
system.cpu.commit.commitCommittedOps 100648623 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 12825262 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 37025 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 616891 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 45721388 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 2.201347 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.733819 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 16264410 35.57% 35.57% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 11914734 26.06% 61.63% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 3626051 7.93% 69.56% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 2926022 6.40% 75.96% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 1880797 4.11% 80.08% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 1911030 4.18% 84.26% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 689200 1.51% 85.76% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 582969 1.28% 87.04% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 5926175 12.96% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 45721388 # Number of insts commited each cycle
system.cpu.commit.committedInsts 70929376 # Number of instructions committed
system.cpu.commit.committedOps 100648623 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 47869324 # Number of memory references committed
system.cpu.commit.loads 27310347 # Number of loads committed
system.cpu.commit.membars 15920 # Number of memory barriers committed
system.cpu.commit.branches 13671866 # Number of branches committed
system.cpu.commit.fp_insts 56 # Number of committed floating point instructions.
system.cpu.commit.int_insts 91485735 # Number of committed integer instructions.
system.cpu.commit.function_calls 1679850 # Number of function calls committed.
system.cpu.commit.bw_lim_events 5926175 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 153243799 # The number of ROB reads
system.cpu.rob.rob_writes 228884039 # The number of ROB writes
system.cpu.timesIdled 52429 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 1273281 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 70923824 # Number of Instructions Simulated
system.cpu.committedOps 100643071 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 70923824 # Number of Instructions Simulated
system.cpu.cpi 0.689758 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.689758 # CPI: Total CPI of All Threads
system.cpu.ipc 1.449783 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.449783 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 516242048 # number of integer regfile reads
system.cpu.int_regfile_writes 104369908 # number of integer regfile writes
system.cpu.fp_regfile_reads 886 # number of floating regfile reads
system.cpu.fp_regfile_writes 750 # number of floating regfile writes
system.cpu.misc_regfile_reads 146091713 # number of misc regfile reads
system.cpu.misc_regfile_writes 38318 # number of misc regfile writes
system.cpu.icache.replacements 30244 # number of replacements
system.cpu.icache.tagsinuse 1815.033473 # Cycle average of tags in use
system.cpu.icache.total_refs 12045499 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 32282 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 373.133604 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 1815.033473 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.886247 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.886247 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 12045501 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 12045501 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 12045501 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 12045501 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 12045501 # number of overall hits
system.cpu.icache.overall_hits::total 12045501 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 33638 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 33638 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 33638 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 33638 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 33638 # number of overall misses
system.cpu.icache.overall_misses::total 33638 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 406685000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 406685000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 406685000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 406685000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 406685000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 406685000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 12079139 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 12079139 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 12079139 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 12079139 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 12079139 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 12079139 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002785 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.002785 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.002785 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.002785 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.002785 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.002785 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 12090.046971 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 12090.046971 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 12090.046971 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 12090.046971 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 12090.046971 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 12090.046971 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1313 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 1313 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 1313 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 1313 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 1313 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 1313 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 32325 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 32325 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 32325 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 32325 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 32325 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 32325 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 274223500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 274223500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 274223500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 274223500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 274223500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 274223500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002676 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002676 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002676 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.002676 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002676 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.002676 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8483.325599 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 8483.325599 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8483.325599 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 8483.325599 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8483.325599 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 8483.325599 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 158501 # number of replacements
system.cpu.dcache.tagsinuse 4071.855185 # Cycle average of tags in use
system.cpu.dcache.total_refs 44605412 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 162597 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 274.331089 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 272454000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4071.855185 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.994105 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.994105 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 26278291 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 26278291 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 18287500 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 18287500 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 20317 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 20317 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 19158 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 19158 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 44565791 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 44565791 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 44565791 # number of overall hits
system.cpu.dcache.overall_hits::total 44565791 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 106674 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 106674 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1562401 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 1562401 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 43 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 43 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 1669075 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 1669075 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 1669075 # number of overall misses
system.cpu.dcache.overall_misses::total 1669075 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 2574319000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 2574319000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 63349260500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 63349260500 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 629500 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 629500 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 65923579500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 65923579500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 65923579500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 65923579500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 26384965 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 26384965 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 20360 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 20360 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 19158 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 19158 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 46234866 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 46234866 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 46234866 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 46234866 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004043 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.004043 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.078711 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.078711 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002112 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002112 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.036100 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.036100 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.036100 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.036100 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24132.581510 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 24132.581510 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40546.095721 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 40546.095721 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14639.534884 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14639.534884 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 39497.074427 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 39497.074427 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 39497.074427 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 39497.074427 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 202500 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 18409.090909 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 128059 # number of writebacks
system.cpu.dcache.writebacks::total 128059 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 51068 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 51068 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1455366 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 1455366 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 43 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 43 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 1506434 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 1506434 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 1506434 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 1506434 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55606 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 55606 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107035 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 107035 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 162641 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 162641 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 162641 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 162641 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 982100000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 982100000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3836030000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3836030000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4818130000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 4818130000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4818130000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 4818130000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002107 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002107 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003518 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.003518 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003518 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.003518 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17661.763119 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17661.763119 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35839.024618 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35839.024618 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29624.325969 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 29624.325969 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29624.325969 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 29624.325969 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 97988 # number of replacements
system.cpu.l2cache.tagsinuse 28616.670846 # Cycle average of tags in use
system.cpu.l2cache.total_refs 87010 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 128775 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.675675 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 25808.135877 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 1157.314936 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 1651.220033 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.787602 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.035318 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.050391 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.873311 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 27137 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 32372 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 59509 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 128059 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 128059 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 7 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 7 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 4712 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 4712 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 27137 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 37084 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 64221 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 27137 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 37084 # number of overall hits
system.cpu.l2cache.overall_hits::total 64221 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 5137 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 23202 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 28339 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 37 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 37 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 102311 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 102311 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 5137 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 125513 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 130650 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 5137 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 125513 # number of overall misses
system.cpu.l2cache.overall_misses::total 130650 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 180597500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 827692000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 1008289500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3557345000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 3557345000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 180597500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 4385037000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 4565634500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 180597500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 4385037000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 4565634500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 32274 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 55574 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 87848 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 128059 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 128059 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 44 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 44 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 107023 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 107023 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 32274 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 162597 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 194871 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 32274 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 162597 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 194871 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.159168 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.417497 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.322591 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.840909 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.840909 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955972 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.955972 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.159168 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.771927 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.670444 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.159168 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.771927 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.670444 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35156.219583 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 35673.304026 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 35579.572321 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34769.917213 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34769.917213 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35156.219583 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34936.914901 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 34945.537696 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35156.219583 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34936.914901 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 34945.537696 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 84643 # number of writebacks
system.cpu.l2cache.writebacks::total 84643 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 28 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 64 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total 92 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 28 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 64 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 92 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 28 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 64 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 92 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 5109 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 23138 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 28247 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 37 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 37 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102311 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 102311 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 5109 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 125449 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 130558 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 5109 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 125449 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 130558 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 163941000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 752838000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 916779000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1147000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1147000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3241185000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3241185000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 163941000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3994023000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 4157964000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 163941000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3994023000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 4157964000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.158301 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.416346 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.321544 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.840909 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.840909 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955972 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955972 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.158301 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771533 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.669971 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.158301 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771533 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.669971 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32088.667058 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32536.865762 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32455.800616 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31679.731407 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31679.731407 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32088.667058 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31837.822541 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31847.638597 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32088.667058 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31837.822541 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31847.638597 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
|