blob: a9b05e877de93314a162afbd71c0abaab658b89d (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
|
---------- Begin Simulation Statistics ----------
sim_seconds 0.030747 # Number of seconds simulated
sim_ticks 30746529500 # Number of ticks simulated
final_tick 30746529500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 146131 # Simulator instruction rate (inst/s)
host_op_rate 207370 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 63356016 # Simulator tick rate (ticks/s)
host_mem_usage 232084 # Number of bytes of host memory used
host_seconds 485.30 # Real time elapsed on the host
sim_insts 70917047 # Number of instructions simulated
sim_ops 100636295 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 8680064 # Number of bytes read from this memory
system.physmem.bytes_inst_read 363776 # Number of instructions bytes read from this memory
system.physmem.bytes_written 5661120 # Number of bytes written to this memory
system.physmem.num_reads 135626 # Number of read requests responded to by this memory
system.physmem.num_writes 88455 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
system.physmem.bw_read 282310366 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 11831449 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write 184122244 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total 466432610 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 1946 # Number of system calls
system.cpu.numCycles 61493060 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 17207683 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 11124675 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 739996 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 12413226 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 8258713 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 1860363 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 182681 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 13006035 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 87629176 # Number of instructions fetch has processed
system.cpu.fetch.Branches 17207683 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 10119076 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 21952285 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 2766047 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 23185818 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 39 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 2820 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 12232999 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 233597 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 60095316 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.044969 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.137732 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 38160956 63.50% 63.50% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 2271093 3.78% 67.28% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 1990023 3.31% 70.59% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 2119724 3.53% 74.12% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 1647401 2.74% 76.86% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 1441763 2.40% 79.26% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 1000150 1.66% 80.92% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 1230223 2.05% 82.97% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 10233983 17.03% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 60095316 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.279831 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.425025 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 14817180 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 21950690 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 20398412 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 1086428 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 1842606 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 3463605 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 108661 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 119794628 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 354485 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 1842606 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 16634867 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 1966833 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 15615217 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 19642472 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 4393321 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 116600703 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 16 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 4194 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 3033361 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 70 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 116869923 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 536821347 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 536814358 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 6989 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 99147741 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 17722182 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 787670 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 786973 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 12493394 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 29971388 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 22471181 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 2503550 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 3551864 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 111668104 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 780017 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 107789312 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 331076 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 11606029 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 28797672 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 76559 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 60095316 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.793639 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.921516 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 21617080 35.97% 35.97% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 11242625 18.71% 54.68% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 8368043 13.92% 68.60% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 7334755 12.21% 80.81% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 4853612 8.08% 88.89% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 3598814 5.99% 94.87% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 1699571 2.83% 97.70% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 846136 1.41% 99.11% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 534680 0.89% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 60095316 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 104237 3.89% 3.89% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 3.89% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 3.89% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 1 0.00% 3.89% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.89% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.89% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 3.89% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.89% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 3.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 3.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.89% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 1507488 56.31% 60.20% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 1065632 39.80% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 56897133 52.79% 52.79% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 88643 0.08% 52.87% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.87% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 206 0.00% 52.87% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.87% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.87% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.87% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.87% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.87% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.87% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.87% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.87% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.87% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.87% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.87% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.87% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.87% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.87% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.87% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.87% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.87% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.87% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.87% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.87% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.87% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.87% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.87% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.87% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.87% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 29161823 27.05% 79.92% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 21641500 20.08% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 107789312 # Type of FU issued
system.cpu.iq.rate 1.752870 # Inst issue rate
system.cpu.iq.fu_busy_cnt 2677358 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.024839 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 278681648 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 124068735 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 105618069 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 726 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 1184 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 180 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 110466305 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 365 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 1905391 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 2662397 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 4708 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 16942 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 1913561 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 60 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 56 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 1842606 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 954066 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 28419 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 112530590 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 448477 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 29971388 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 22471181 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 763809 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 1185 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 1150 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 16942 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 525308 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 249263 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 774571 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 106544172 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 28789537 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 1245140 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 82469 # number of nop insts executed
system.cpu.iew.exec_refs 50119660 # number of memory reference insts executed
system.cpu.iew.exec_branches 14611553 # Number of branches executed
system.cpu.iew.exec_stores 21330123 # Number of stores executed
system.cpu.iew.exec_rate 1.732621 # Inst execution rate
system.cpu.iew.wb_sent 105962456 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 105618249 # cumulative count of insts written-back
system.cpu.iew.wb_producers 52610922 # num instructions producing a value
system.cpu.iew.wb_consumers 101691142 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.717564 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.517360 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 70922599 # The number of committed instructions
system.cpu.commit.commitCommittedOps 100641847 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 11889102 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 703458 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 696794 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 58252711 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.727677 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.445395 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 25477544 43.74% 43.74% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 14542293 24.96% 68.70% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 4151131 7.13% 75.83% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 3607676 6.19% 82.02% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 2313094 3.97% 85.99% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 1905802 3.27% 89.26% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 675667 1.16% 90.42% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 497156 0.85% 91.28% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 5082348 8.72% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 58252711 # Number of insts commited each cycle
system.cpu.commit.committedInsts 70922599 # Number of instructions committed
system.cpu.commit.committedOps 100641847 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 47866611 # Number of memory references committed
system.cpu.commit.loads 27308991 # Number of loads committed
system.cpu.commit.membars 15920 # Number of memory barriers committed
system.cpu.commit.branches 13670510 # Number of branches committed
system.cpu.commit.fp_insts 56 # Number of committed floating point instructions.
system.cpu.commit.int_insts 91480315 # Number of committed integer instructions.
system.cpu.commit.function_calls 1679850 # Number of function calls committed.
system.cpu.commit.bw_lim_events 5082348 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 165676013 # The number of ROB reads
system.cpu.rob.rob_writes 226913156 # The number of ROB writes
system.cpu.timesIdled 61654 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 1397744 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 70917047 # Number of Instructions Simulated
system.cpu.committedOps 100636295 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 70917047 # Number of Instructions Simulated
system.cpu.cpi 0.867113 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.867113 # CPI: Total CPI of All Threads
system.cpu.ipc 1.153253 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.153253 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 512941825 # number of integer regfile reads
system.cpu.int_regfile_writes 103506893 # number of integer regfile writes
system.cpu.fp_regfile_reads 822 # number of floating regfile reads
system.cpu.fp_regfile_writes 678 # number of floating regfile writes
system.cpu.misc_regfile_reads 145707136 # number of misc regfile reads
system.cpu.misc_regfile_writes 35604 # number of misc regfile writes
system.cpu.icache.replacements 30139 # number of replacements
system.cpu.icache.tagsinuse 1825.169858 # Cycle average of tags in use
system.cpu.icache.total_refs 12199552 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 32178 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 379.127105 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 1825.169858 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.891196 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.891196 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 12199556 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 12199556 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 12199556 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 12199556 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 12199556 # number of overall hits
system.cpu.icache.overall_hits::total 12199556 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 33443 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 33443 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 33443 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 33443 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 33443 # number of overall misses
system.cpu.icache.overall_misses::total 33443 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 390329000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 390329000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 390329000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 390329000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 390329000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 390329000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 12232999 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 12232999 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 12232999 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 12232999 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 12232999 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 12232999 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002734 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.002734 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.002734 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 11671.470861 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 11671.470861 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 11671.470861 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1227 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 1227 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 1227 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 1227 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 1227 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 1227 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 32216 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 32216 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 32216 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 32216 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 32216 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 32216 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 262568000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 262568000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 262568000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 262568000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 262568000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 262568000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002634 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002634 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002634 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8150.235908 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8150.235908 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8150.235908 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 158787 # number of replacements
system.cpu.dcache.tagsinuse 4071.855025 # Cycle average of tags in use
system.cpu.dcache.total_refs 44862936 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 162883 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 275.430438 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 309114000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4071.855025 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.994105 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.994105 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 26515454 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 26515454 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 18310363 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 18310363 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 19173 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 19173 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 17801 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 17801 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 44825817 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 44825817 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 44825817 # number of overall hits
system.cpu.dcache.overall_hits::total 44825817 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 110570 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 110570 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1539538 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 1539538 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 35 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 35 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 1650108 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 1650108 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 1650108 # number of overall misses
system.cpu.dcache.overall_misses::total 1650108 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 2444111000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 2444111000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 52524497000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 52524497000 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 460000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 460000 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 54968608000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 54968608000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 54968608000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 54968608000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 26626024 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 26626024 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 19208 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 19208 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 17801 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 17801 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 46475925 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 46475925 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 46475925 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 46475925 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004153 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.077559 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001822 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.035505 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.035505 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22104.648639 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34117.051349 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13142.857143 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 33312.127449 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 33312.127449 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 210500 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 19136.363636 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 123777 # number of writebacks
system.cpu.dcache.writebacks::total 123777 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 54544 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 54544 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1432641 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 1432641 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 35 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 35 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 1487185 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 1487185 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 1487185 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 1487185 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 56026 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 56026 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 106897 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 106897 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 162923 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 162923 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 162923 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 162923 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1045999000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 1045999000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3665143000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3665143000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4711142000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 4711142000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4711142000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 4711142000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002104 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005385 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003506 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003506 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18669.885410 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34286.677830 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28916.371537 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28916.371537 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 115366 # number of replacements
system.cpu.l2cache.tagsinuse 18380.056703 # Cycle average of tags in use
system.cpu.l2cache.total_refs 77246 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 134234 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.575458 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 15926.417770 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 869.276792 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 1584.362140 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.486036 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.026528 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.048351 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.560915 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 26467 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 28565 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 55032 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 123777 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 123777 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 11 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 11 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 4312 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 4312 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 26467 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 32877 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 59344 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 26467 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 32877 # number of overall hits
system.cpu.l2cache.overall_hits::total 59344 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 5707 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 27425 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 33132 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 29 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 29 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 102581 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 102581 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 5707 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 130006 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 135713 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 5707 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 130006 # number of overall misses
system.cpu.l2cache.overall_misses::total 135713 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 195425500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 938664000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 1134089500 # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 34000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 34000 # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3518121500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 3518121500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 195425500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 4456785500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 4652211000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 195425500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 4456785500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 4652211000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 32174 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 55990 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 88164 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 123777 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 123777 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 40 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 40 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 106893 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 106893 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 32174 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 162883 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 195057 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 32174 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 162883 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 195057 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.177379 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.489820 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.725000 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.959661 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.177379 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.798156 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.177379 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.798156 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34243.122481 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34226.581586 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 1172.413793 # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34296.034353 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34243.122481 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34281.383167 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34243.122481 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34281.383167 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 88455 # number of writebacks
system.cpu.l2cache.writebacks::total 88455 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 23 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 64 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total 87 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 23 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 64 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 87 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 23 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 64 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 87 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 5684 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27361 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 33045 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 29 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 29 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102581 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 102581 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 5684 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 129942 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 135626 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 5684 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 129942 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 135626 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 176568000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 850424500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1026992500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 901000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 901000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3193612500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3193612500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 176568000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4044037000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 4220605000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 176568000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4044037000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 4220605000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.176664 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.488677 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.725000 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.959661 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.176664 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.797763 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.176664 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.797763 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31064.039409 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31081.630788 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31068.965517 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31132.592780 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31064.039409 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31121.862062 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31064.039409 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31121.862062 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
|