path: root/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.025535                       # Number of seconds simulated
sim_ticks                                 25534556000                       # Number of ticks simulated
final_tick                                25534556000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  42425                       # Simulator instruction rate (inst/s)
host_op_rate                                    60207                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               15277801                       # Simulator tick rate (ticks/s)
host_mem_usage                                 296924                       # Number of bytes of host memory used
host_seconds                                  1671.35                       # Real time elapsed on the host
sim_insts                                    70907629                       # Number of instructions simulated
sim_ops                                     100626876                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst            297536                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           7943424                       # Number of bytes read from this memory
system.physmem.bytes_read::total              8240960                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       297536                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          297536                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      5372480                       # Number of bytes written to this memory
system.physmem.bytes_written::total           5372480                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst               4649                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             124116                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                128765                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           83945                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                83945                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst             11652288                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data            311085260                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total               322737548                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst        11652288                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total           11652288                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks         210400369                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total              210400369                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks         210400369                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst            11652288                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data           311085260                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              533137917                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        128766                       # Total number of read requests seen
system.physmem.writeReqs                        83945                       # Total number of write requests seen
system.physmem.cpureqs                         213036                       # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead                      8240960                       # Total number of bytes read from memory
system.physmem.bytesWritten                   5372480                       # Total number of bytes written to memory
system.physmem.bytesConsumedRd                8240960                       # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr                5372480                       # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ                        2                       # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite                325                       # Reqs where no action is needed
system.physmem.perBankRdReqs::0                  7974                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::1                  8181                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::2                  8060                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::3                  8163                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::4                  8166                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::5                  8116                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::6                  8007                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::7                  8045                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::8                  8002                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::9                  7985                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::10                 7994                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::11                 8125                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::12                 8030                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::13                 7980                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::14                 7988                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::15                 7948                       # Track reads on a per bank basis
system.physmem.perBankWrReqs::0                  5143                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::1                  5260                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::2                  5208                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::3                  5207                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::4                  5324                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::5                  5374                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::6                  5324                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::7                  5328                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::8                  5262                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::9                  5276                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::10                 5312                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::11                 5351                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::12                 5167                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::13                 5124                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::14                 5132                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::15                 5153                       # Track writes on a per bank basis
system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
system.physmem.numWrRetry                           0                       # Number of times wr buffer was full causing retry
system.physmem.totGap                     25534539500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
system.physmem.readPktSize::2                       0                       # Categorize read packet sizes
system.physmem.readPktSize::3                       0                       # Categorize read packet sizes
system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
system.physmem.readPktSize::6                  128766                       # Categorize read packet sizes
system.physmem.writePktSize::0                      0                       # Categorize write packet sizes
system.physmem.writePktSize::1                      0                       # Categorize write packet sizes
system.physmem.writePktSize::2                      0                       # Categorize write packet sizes
system.physmem.writePktSize::3                      0                       # Categorize write packet sizes
system.physmem.writePktSize::4                      0                       # Categorize write packet sizes
system.physmem.writePktSize::5                      0                       # Categorize write packet sizes
system.physmem.writePktSize::6                  83945                       # Categorize write packet sizes
system.physmem.rdQLenPdf::0                     70151                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     56460                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                      2075                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                        64                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                        14                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                      3544                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                      3638                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                      3647                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                      3649                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                      3650                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                      3650                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                      3650                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                      3650                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                      3650                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                      3650                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                     3650                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                     3650                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                     3650                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                     3650                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                     3650                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     3650                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     3650                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     3650                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     3649                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     3649                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     3649                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     3649                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     3649                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                      106                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                       12                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        3                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.totQLat                     3209266500                       # Total cycles spent in queuing delays
system.physmem.totMemAccLat                5253345250                       # Sum of mem lat for all requests
system.physmem.totBusLat                    643820000                       # Total cycles spent in databus access
system.physmem.totBankLat                  1400258750                       # Total cycles spent in bank access
system.physmem.avgQLat                       24923.63                       # Average queueing delay per request
system.physmem.avgBankLat                    10874.61                       # Average bank access latency per request
system.physmem.avgBusLat                      5000.00                       # Average bus latency per request
system.physmem.avgMemAccLat                  40798.25                       # Average memory access latency
system.physmem.avgRdBW                         322.74                       # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW                         210.40                       # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW                 322.74                       # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW                 210.40                       # Average consumed write bandwidth in MB/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MB/s
system.physmem.busUtil                           4.17                       # Data bus utilization in percentage
system.physmem.avgRdQLen                         0.21                       # Average read queue length over time
system.physmem.avgWrQLen                         9.90                       # Average write queue length over time
system.physmem.readRowHits                     116738                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     52892                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   90.66                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  63.01                       # Row buffer hit rate for writes
system.physmem.avgGap                       120043.34                       # Average gap between requests
system.cpu.branchPred.lookups                16612549                       # Number of BP lookups
system.cpu.branchPred.condPredicted          12751503                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect            599939                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             10534593                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                 7757405                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             73.637444                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 1822464                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect             113740                       # Number of incorrect RAS predictions.
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                 1946                       # Number of system calls
system.cpu.numCycles                         51069113                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles           12514698                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                       85141272                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    16612549                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches            9579869                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                      21174766                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 2353264                       # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles               10532726                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                   68                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles           498                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles           40                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                  11663165                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                178973                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples           45949088                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              2.594403                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.336122                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                 24794811     53.96%     53.96% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  2137100      4.65%     58.61% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                  1960912      4.27%     62.88% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                  2040333      4.44%     67.32% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  1467005      3.19%     70.51% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                  1375299      2.99%     73.51% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                   957293      2.08%     75.59% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                  1188429      2.59%     78.18% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                 10027906     21.82%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total             45949088                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.325295                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        1.667177                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 14598305                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles               8880724                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                  19456140                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               1390682                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                1623237                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved              3327841                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                105063                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts              116768795                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                361627                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                1623237                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 16304725                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                 2541710                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles         873067                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                  19090805                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles               5515544                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              114897326                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                   145                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                  17204                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents               4661371                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents              307                       # Number of times there has been no free registers
system.cpu.rename.RenamedOperands           115217977                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups             529361609                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups        529355204                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups              6405                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps              99132672                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                 16085305                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts              20097                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts          20095                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  13032825                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             29592002                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            22430174                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           3871274                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores          4372916                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  111465960                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded               35763                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 107205683                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            272681                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        10729594                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined     25689486                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved           1977                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples      45949088                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         2.333141                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.988541                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0            10727081     23.35%     23.35% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1             8071190     17.57%     40.91% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2             7423915     16.16%     57.07% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3             7121409     15.50%     72.57% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4             5405073     11.76%     84.33% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5             3914653      8.52%     92.85% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6             1842463      4.01%     96.86% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7              872331      1.90%     98.76% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8              570973      1.24%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total        45949088                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                  112030      4.53%      4.53% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%      4.53% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%      4.53% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     2      0.00%      4.53% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%      4.53% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%      4.53% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%      4.53% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%      4.53% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      4.53% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%      4.53% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      4.53% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%      4.53% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%      4.53% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%      4.53% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%      4.53% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%      4.53% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      4.53% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%      4.53% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      4.53% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      4.53% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      4.53% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      4.53% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      4.53% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      4.53% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      4.53% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      4.53% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      4.53% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      4.53% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      4.53% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                1365116     55.14%     59.67% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                998484     40.33%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu              56613299     52.81%     52.81% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                91558      0.09%     52.89% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     52.89% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                 214      0.00%     52.89% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     52.89% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     52.89% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     52.89% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     52.89% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     52.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     52.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     52.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     52.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     52.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     52.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     52.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     52.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     52.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     52.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     52.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     52.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     52.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     52.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     52.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     52.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     52.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              7      0.00%     52.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     52.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     52.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     52.89% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             28880685     26.94%     79.83% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite            21619920     20.17%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              107205683                       # Type of FU issued
system.cpu.iq.rate                           2.099227                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                     2475632                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.023092                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads          263108179                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         122259769                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses    105531184                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                 588                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes                948                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses          171                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              109681022                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                     293                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          2183832                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      2284894                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses         6284                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        30581                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      1874436                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads           30                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked           495                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                1623237                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                 1048241                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                 45255                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           111511491                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            294294                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              29592002                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             22430174                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts              19843                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                   6298                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                  5233                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          30581                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         389128                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       180293                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts               569421                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             106181677                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              28584422                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           1024006                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                          9768                       # number of nop insts executed
system.cpu.iew.exec_refs                     49919694                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 14596236                       # Number of branches executed
system.cpu.iew.exec_stores                   21335272                       # Number of stores executed
system.cpu.iew.exec_rate                     2.079176                       # Inst execution rate
system.cpu.iew.wb_sent                      105750985                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                     105531355                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                  53247115                       # num instructions producing a value
system.cpu.iew.wb_consumers                 103478593                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       2.066442                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.514571                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts        10879947                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls           33786                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts            496884                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples     44325851                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     2.270288                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.765576                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0     15270109     34.45%     34.45% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     11622337     26.22%     60.67% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2      3461272      7.81%     68.48% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3      2876318      6.49%     74.97% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      1875937      4.23%     79.20% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      1955484      4.41%     83.61% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6       687541      1.55%     85.16% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7       562645      1.27%     86.43% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      6014208     13.57%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total     44325851                       # Number of insts commited each cycle
system.cpu.commit.committedInsts             70913181                       # Number of instructions committed
system.cpu.commit.committedOps              100632428                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       47862846                       # Number of memory references committed
system.cpu.commit.loads                      27307108                       # Number of loads committed
system.cpu.commit.membars                       15920                       # Number of memory barriers committed
system.cpu.commit.branches                   13741485                       # Number of branches committed
system.cpu.commit.fp_insts                         56                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                  91472779                       # Number of committed integer instructions.
system.cpu.commit.function_calls              1679850                       # Number of function calls committed.
system.cpu.commit.bw_lim_events               6014208                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                    149798719                       # The number of ROB reads
system.cpu.rob.rob_writes                   224657070                       # The number of ROB writes
system.cpu.timesIdled                           74104                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                         5120025                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                    70907629                       # Number of Instructions Simulated
system.cpu.committedOps                     100626876                       # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total              70907629                       # Number of Instructions Simulated
system.cpu.cpi                               0.720220                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.720220                       # CPI: Total CPI of All Threads
system.cpu.ipc                               1.388464                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         1.388464                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                511419514                       # number of integer regfile reads
system.cpu.int_regfile_writes               103305187                       # number of integer regfile writes
system.cpu.fp_regfile_reads                       846                       # number of floating regfile reads
system.cpu.fp_regfile_writes                      738                       # number of floating regfile writes
system.cpu.misc_regfile_reads                49163804                       # number of misc regfile reads
system.cpu.misc_regfile_writes                  31840                       # number of misc regfile writes
system.cpu.icache.replacements                  28595                       # number of replacements
system.cpu.icache.tagsinuse               1814.564534                       # Cycle average of tags in use
system.cpu.icache.total_refs                 11628419                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                  30629                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs                 379.653890                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst    1814.564534                       # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst      0.886018                       # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total         0.886018                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst     11628429                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        11628429                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      11628429                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         11628429                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     11628429                       # number of overall hits
system.cpu.icache.overall_hits::total        11628429                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst        34736                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total         34736                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst        34736                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total          34736                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst        34736                       # number of overall misses
system.cpu.icache.overall_misses::total         34736                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    739851499                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    739851499                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    739851499                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    739851499                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    739851499                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    739851499                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     11663165                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     11663165                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     11663165                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     11663165                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     11663165                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     11663165                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.002978                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.002978                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.002978                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.002978                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.002978                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.002978                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21299.271620                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 21299.271620                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 21299.271620                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 21299.271620                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 21299.271620                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 21299.271620                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs         1371                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                21                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    65.285714                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst         3776                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total         3776                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst         3776                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total         3776                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst         3776                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total         3776                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst        30960                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total        30960                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst        30960                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total        30960                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst        30960                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total        30960                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    598675999                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    598675999                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    598675999                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    598675999                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    598675999                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    598675999                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.002655                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.002655                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.002655                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.002655                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.002655                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.002655                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19337.080071                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19337.080071                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19337.080071                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 19337.080071                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19337.080071                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 19337.080071                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.replacements                 95631                       # number of replacements
system.cpu.l2cache.tagsinuse             30087.682209                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                   88021                       # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs                126746                       # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs                  0.694468                       # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 26926.189378                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst   1374.986838                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data   1786.505993                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks     0.821722                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst     0.041961                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data     0.054520                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total        0.918203                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst        25771                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data        33436                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total          59207                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks       129075                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total       129075                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data           18                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total           18                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data         4783                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total         4783                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst        25771                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data        38219                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total           63990                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst        25771                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data        38219                       # number of overall hits
system.cpu.l2cache.overall_hits::total          63990                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst         4664                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data        21926                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total        26590                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data          324                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total          324                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       102251                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       102251                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst         4664                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       124177                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        128841                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         4664                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       124177                       # number of overall misses
system.cpu.l2cache.overall_misses::total       128841                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    309051000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data   1483283000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   1792334000                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data        23000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total        23000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   6646928500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   6646928500                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    309051000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data   8130211500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total   8439262500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    309051000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data   8130211500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total   8439262500                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst        30435                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data        55362                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total        85797                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks       129075                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total       129075                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data          342                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total          342                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       107034                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       107034                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst        30435                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data       162396                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total       192831                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst        30435                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data       162396                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total       192831                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.153245                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.396048                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.309918                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.947368                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.947368                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.955313                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.955313                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.153245                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.764656                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.668155                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.153245                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.764656                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.668155                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66263.078902                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 67649.502873                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 67406.318165                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data    70.987654                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total    70.987654                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 65005.999941                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65005.999941                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66263.078902                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65472.764683                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 65501.373786                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66263.078902                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65472.764683                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 65501.373786                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        83945                       # number of writebacks
system.cpu.l2cache.writebacks::total            83945                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           15                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           59                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total           74                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst           15                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data           59                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           74                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst           15                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data           59                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           74                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         4649                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        21867                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total        26516                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data          324                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total          324                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       102251                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       102251                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         4649                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       124118                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       128767                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         4649                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       124118                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       128767                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    250601778                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1209164905                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1459766683                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data      3249822                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total      3249822                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   5391078264                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   5391078264                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    250601778                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   6600243169                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total   6850844947                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    250601778                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   6600243169                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total   6850844947                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.152752                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.394982                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.309055                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.947368                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.947368                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.955313                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.955313                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.152752                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.764292                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.667771                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.152752                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.764292                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.667771                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53904.447838                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 55296.332602                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55052.296085                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10030.314815                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10030.314815                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52723.966162                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52723.966162                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53904.447838                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53177.163417                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53203.421273                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53904.447838                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53177.163417                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53203.421273                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                 158299                       # number of replacements
system.cpu.dcache.tagsinuse               4072.272113                       # Cycle average of tags in use
system.cpu.dcache.total_refs                 44344927                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                 162395                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs                 273.068303                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle              284501000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data    4072.272113                       # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data      0.994207                       # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total         0.994207                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data     26045311                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        26045311                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     18267055                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       18267055                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data        15985                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total        15985                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data        15919                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total        15919                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      44312366                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         44312366                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     44312366                       # number of overall hits
system.cpu.dcache.overall_hits::total        44312366                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data       124674                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        124674                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      1582846                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      1582846                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data           42                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total           42                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data      1707520                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        1707520                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      1707520                       # number of overall misses
system.cpu.dcache.overall_misses::total       1707520                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data   4256897000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total   4256897000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  98390757481                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  98390757481                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       860000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total       860000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 102647654481                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 102647654481                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 102647654481                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 102647654481                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     26169985                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     26169985                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     19849901                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     19849901                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data        16027                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total        16027                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data        15919                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total        15919                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     46019886                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     46019886                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     46019886                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     46019886                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.004764                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.004764                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.079741                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.079741                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.002621                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.002621                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.037104                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.037104                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.037104                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.037104                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34144.224137                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 34144.224137                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62160.663439                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 62160.663439                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 20476.190476                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 20476.190476                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 60115.052521                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 60115.052521                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 60115.052521                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 60115.052521                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs         3743                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets          661                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs               131                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets              15                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    28.572519                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets    44.066667                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       129075                       # number of writebacks
system.cpu.dcache.writebacks::total            129075                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data        69278                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total        69278                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1475504                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total      1475504                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data           42                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total           42                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      1544782                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      1544782                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      1544782                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      1544782                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data        55396                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total        55396                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       107342                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       107342                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data       162738                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total       162738                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data       162738                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total       162738                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   1878391000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total   1878391000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   6809216990                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   6809216990                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data   8687607990                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total   8687607990                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data   8687607990                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total   8687607990                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002117                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002117                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.005408                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.005408                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.003536                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.003536                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.003536                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.003536                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33908.422991                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33908.422991                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63434.787781                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63434.787781                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53384.015964                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 53384.015964                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53384.015964                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 53384.015964                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------