path: root/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.037982                       # Number of seconds simulated
sim_ticks                                 37982056000                       # Number of ticks simulated
final_tick                                37982056000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 105525                       # Simulator instruction rate (inst/s)
host_op_rate                                   134954                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               56525025                       # Simulator tick rate (ticks/s)
host_mem_usage                                 282344                       # Number of bytes of host memory used
host_seconds                                   671.95                       # Real time elapsed on the host
sim_insts                                    70907652                       # Number of instructions simulated
sim_ops                                      90682607                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED  37982056000                       # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst           2372544                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           5696640                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.l2cache.prefetcher      6178368                       # Number of bytes read from this memory
system.physmem.bytes_read::total             14247552                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst      2372544                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         2372544                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      6227072                       # Number of bytes written to this memory
system.physmem.bytes_written::total           6227072                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst              37071                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data              89010                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.l2cache.prefetcher        96537                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                222618                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           97298                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                97298                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst             62464865                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data            149982402                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.l2cache.prefetcher    162665444                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total               375112711                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst        62464865                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total           62464865                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks         163947734                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total              163947734                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks         163947734                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst            62464865                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data           149982402                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.l2cache.prefetcher    162665444                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              539060445                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        222619                       # Number of read requests accepted
system.physmem.writeReqs                        97298                       # Number of write requests accepted
system.physmem.readBursts                      222619                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                      97298                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 14237568                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     10048                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   6225984                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  14247616                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                6227072                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      157                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                9655                       # Per bank write bursts
system.physmem.perBankRdBursts::1                9974                       # Per bank write bursts
system.physmem.perBankRdBursts::2               12579                       # Per bank write bursts
system.physmem.perBankRdBursts::3               25363                       # Per bank write bursts
system.physmem.perBankRdBursts::4               17343                       # Per bank write bursts
system.physmem.perBankRdBursts::5               22132                       # Per bank write bursts
system.physmem.perBankRdBursts::6               11760                       # Per bank write bursts
system.physmem.perBankRdBursts::7               14137                       # Per bank write bursts
system.physmem.perBankRdBursts::8               11660                       # Per bank write bursts
system.physmem.perBankRdBursts::9               15453                       # Per bank write bursts
system.physmem.perBankRdBursts::10              11698                       # Per bank write bursts
system.physmem.perBankRdBursts::11              11338                       # Per bank write bursts
system.physmem.perBankRdBursts::12               9437                       # Per bank write bursts
system.physmem.perBankRdBursts::13               9564                       # Per bank write bursts
system.physmem.perBankRdBursts::14               9858                       # Per bank write bursts
system.physmem.perBankRdBursts::15              20511                       # Per bank write bursts
system.physmem.perBankWrBursts::0                5992                       # Per bank write bursts
system.physmem.perBankWrBursts::1                6239                       # Per bank write bursts
system.physmem.perBankWrBursts::2                6121                       # Per bank write bursts
system.physmem.perBankWrBursts::3                6129                       # Per bank write bursts
system.physmem.perBankWrBursts::4                6098                       # Per bank write bursts
system.physmem.perBankWrBursts::5                6229                       # Per bank write bursts
system.physmem.perBankWrBursts::6                6018                       # Per bank write bursts
system.physmem.perBankWrBursts::7                5980                       # Per bank write bursts
system.physmem.perBankWrBursts::8                5938                       # Per bank write bursts
system.physmem.perBankWrBursts::9                6095                       # Per bank write bursts
system.physmem.perBankWrBursts::10               6202                       # Per bank write bursts
system.physmem.perBankWrBursts::11               5916                       # Per bank write bursts
system.physmem.perBankWrBursts::12               6046                       # Per bank write bursts
system.physmem.perBankWrBursts::13               6090                       # Per bank write bursts
system.physmem.perBankWrBursts::14               6173                       # Per bank write bursts
system.physmem.perBankWrBursts::15               6015                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                     37982044500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  222619                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                  97298                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    111989                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     59707                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     15764                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                     10925                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      6262                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      5252                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      4622                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      4266                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      3549                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                        76                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                       38                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                       10                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     1089                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     1151                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     1856                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     2518                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     3246                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     4053                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     4935                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     5530                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     6006                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     6447                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     6796                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     7367                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     7813                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     8377                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     8639                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     7998                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     6745                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     6258                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      207                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                       95                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                       63                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                       35                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                       25                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                       18                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                       12                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        3                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       132891                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      153.980270                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     102.520664                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     209.589027                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          82855     62.35%     62.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        32511     24.46%     86.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         6209      4.67%     91.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         2728      2.05%     93.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         1195      0.90%     94.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767          994      0.75%     95.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895          885      0.67%     95.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023          776      0.58%     96.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         4738      3.57%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         132891                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          5883                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        37.813870                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      211.295819                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-511            5876     99.88%     99.88% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::512-1023            6      0.10%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::15360-15871            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            5883                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          5883                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        16.535951                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       16.496117                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        1.216118                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16               4707     80.01%     80.01% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17                 47      0.80%     80.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18                703     11.95%     92.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19                205      3.48%     96.24% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20                109      1.85%     98.10% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21                 61      1.04%     99.13% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22                 33      0.56%     99.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23                 11      0.19%     99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24                  1      0.02%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::25                  1      0.02%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26                  4      0.07%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28                  1      0.02%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            5883                       # Writes before turning the bus around for reads
system.physmem.totQLat                     8417974819                       # Total ticks spent queuing
system.physmem.totMemAccLat               12589137319                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   1112310000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       37840.06                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  56590.06                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                         374.85                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                         163.92                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                      375.11                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                      163.95                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           4.21                       # Data bus utilization in percentage
system.physmem.busUtilRead                       2.93                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      1.28                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.38                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        24.49                       # Average write queue length when enqueuing
system.physmem.readRowHits                     157076                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     29766                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   70.61                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  30.59                       # Row buffer hit rate for writes
system.physmem.avgGap                       118724.68                       # Average gap between requests
system.physmem.pageHitRate                      58.43                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  508332300                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  270162255                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 877813020                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                254767320                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           3007433520.000000                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy             2937544590                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy               74566560                       # Energy for precharge background per rank (pJ)
system.physmem_0.actPowerDownEnergy       13007568150                       # Energy for active power-down per rank (pJ)
system.physmem_0.prePowerDownEnergy        1007588640                       # Energy for precharge power-down per rank (pJ)
system.physmem_0.selfRefreshEnergy           71626485                       # Energy for self refresh per rank (pJ)
system.physmem_0.totalEnergy              22017862440                       # Total energy per rank (pJ)
system.physmem_0.averagePower              579.691165                       # Core power per rank (mW)
system.physmem_0.totalIdleTime            31344656336                       # Total Idle time Per DRAM Rank
system.physmem_0.memoryStateTime::IDLE       41004063                       # Time in different power states
system.physmem_0.memoryStateTime::REF      1272480000                       # Time in different power states
system.physmem_0.memoryStateTime::SREF      195565250                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN   2624595348                       # Time in different power states
system.physmem_0.memoryStateTime::ACT      5323818601                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN  28524592738                       # Time in different power states
system.physmem_1.actEnergy                  440580840                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  234159090                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 710558520                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                253039500                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           2889422640.000000                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy             2771748120                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy               73304160                       # Energy for precharge background per rank (pJ)
system.physmem_1.actPowerDownEnergy       11932439280                       # Energy for active power-down per rank (pJ)
system.physmem_1.prePowerDownEnergy        1384694400                       # Energy for precharge power-down per rank (pJ)
system.physmem_1.selfRefreshEnergy          508589940                       # Energy for self refresh per rank (pJ)
system.physmem_1.totalEnergy              21198847170                       # Total energy per rank (pJ)
system.physmem_1.averagePower              558.127949                       # Core power per rank (mW)
system.physmem_1.totalIdleTime            31712588164                       # Total Idle time Per DRAM Rank
system.physmem_1.memoryStateTime::IDLE       50452548                       # Time in different power states
system.physmem_1.memoryStateTime::REF      1222746000                       # Time in different power states
system.physmem_1.memoryStateTime::SREF     1938473750                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN   3605935527                       # Time in different power states
system.physmem_1.memoryStateTime::ACT      4996269288                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN  26168178887                       # Time in different power states
system.pwrStateResidencyTicks::UNDEFINED  37982056000                       # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups                17071043                       # Number of BP lookups
system.cpu.branchPred.condPredicted          11458506                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect            598065                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups              9277652                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                 7374059                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             79.481953                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 1854771                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect             101571                       # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups          233347                       # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits             194967                       # Number of indirect target hits.
system.cpu.branchPred.indirectMisses            38380                       # Number of indirect misses.
system.cpu.branchPredindirectMispredicted        22266                       # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED  37982056000                       # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED  37982056000                       # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED  37982056000                       # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED  37982056000                       # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks                         0                       # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                 1946                       # Number of system calls
system.cpu.pwrStateResidencyTicks::ON     37982056000                       # Cumulative time (in ticks) in various power states
system.cpu.numCycles                         75964113                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles            5537723                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                       87105546                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    17071043                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches            9423797                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                      66074321                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 1222765                       # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles                12043                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles            60                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles        33616                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                  22433583                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                 69302                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples           72269145                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              1.523281                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             1.330897                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                 27092588     37.49%     37.49% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  8164913     11.30%     48.79% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                  9113637     12.61%     61.40% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                 27898007     38.60%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total             72269145                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.224725                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        1.146667                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                  8914938                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              26268747                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                  30971085                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               5669704                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                 444671                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved              3134143                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                168562                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts              100303161                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts               2799230                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                 444671                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 13550474                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                11467047                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles         876029                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                  31784130                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              14146794                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts               98330583                       # Number of instructions processed by rename
system.cpu.rename.SquashedInsts                860090                       # Number of squashed instructions processed by rename
system.cpu.rename.ROBFullEvents               4210253                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                  70388                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents                4670257                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents                5435231                       # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands           103259286                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups             453553071                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups        114279094                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups               706                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps              93629369                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                  9629917                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts              18998                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts          19022                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  12803731                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             24155645                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            21760500                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           1435489                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores          2293932                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                   97400499                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded               34856                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                  94484787                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            595355                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined         6752748                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined     17957034                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved           1070                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples      72269145                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         1.307401                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.171287                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0            24146655     33.41%     33.41% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            17449315     24.14%     57.56% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2            17027031     23.56%     81.12% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3            11604628     16.06%     97.18% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4             2040054      2.82%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5                1462      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total        72269145                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                 6736684     22.63%     22.63% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                     37      0.00%     22.63% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     22.63% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     22.63% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     22.63% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     22.63% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     22.63% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     22.63% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     22.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     22.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     22.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     22.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     22.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     22.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     22.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     22.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     22.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     22.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     22.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     22.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     22.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     22.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     22.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     22.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     22.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     22.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     22.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     22.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     22.63% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead               11088474     37.25%     59.89% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite              11940322     40.11%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu              49305598     52.18%     52.18% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                86530      0.09%     52.28% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     52.28% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                  32      0.00%     52.28% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     52.28% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     52.28% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     52.28% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     52.28% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     52.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     52.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     52.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     52.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     52.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     52.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     52.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     52.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     52.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     52.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     52.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     52.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     52.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     52.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp              11      0.00%     52.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     52.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     52.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc             18      0.00%     52.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     52.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     52.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     52.28% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             23958877     25.36%     77.63% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite            21133721     22.37%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total               94484787                       # Type of FU issued
system.cpu.iq.rate                           1.243808                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                    29765517                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.315030                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads          291599265                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         104199326                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses     93203450                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                 326                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes                598                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses           92                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              124250121                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                     183                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          1368397                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      1289383                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses         2091                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        11973                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      1204762                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads       147075                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked        188044                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                 444671                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                  622988                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles               1195662                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts            97449431                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              24155645                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             21760500                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts              18936                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                   1589                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents               1191442                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          11973                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         249986                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       222081                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts               472067                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts              93691189                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              23695668                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts            793598                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                         14076                       # number of nop insts executed
system.cpu.iew.exec_refs                     44621004                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 14207535                       # Number of branches executed
system.cpu.iew.exec_stores                   20925336                       # Number of stores executed
system.cpu.iew.exec_rate                     1.233361                       # Inst execution rate
system.cpu.iew.wb_sent                       93310594                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                      93203542                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                  44951761                       # num instructions producing a value
system.cpu.iew.wb_consumers                  76639550                       # num instructions consuming a value
system.cpu.iew.wb_rate                       1.226942                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.586535                       # average fanout of values written-back
system.cpu.commit.commitSquashedInsts         5895620                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls           33786                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts            431354                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples     71312758                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.271696                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.107515                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0     37859507     53.09%     53.09% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     16683603     23.39%     76.48% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2      4297164      6.03%     82.51% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3      4156384      5.83%     88.34% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      1956005      2.74%     91.08% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      1240140      1.74%     92.82% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6       732437      1.03%     93.85% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7       578410      0.81%     94.66% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      3809108      5.34%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total     71312758                       # Number of insts commited each cycle
system.cpu.commit.committedInsts             70913204                       # Number of instructions committed
system.cpu.commit.committedOps               90688159                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       43422000                       # Number of memory references committed
system.cpu.commit.loads                      22866262                       # Number of loads committed
system.cpu.commit.membars                       15920                       # Number of memory barriers committed
system.cpu.commit.branches                   13741468                       # Number of branches committed
system.cpu.commit.fp_insts                         56                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                  81528527                       # Number of committed integer instructions.
system.cpu.commit.function_calls              1679850                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu         47186033     52.03%     52.03% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult           80119      0.09%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv                0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd              0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp              0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt              0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv              0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc            7      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead        22866262     25.21%     77.33% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite       20555738     22.67%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total          90688159                       # Class of committed instruction
system.cpu.commit.bw_lim_events               3809108                       # number cycles where commit BW limit reached
system.cpu.rob.rob_reads                    164062130                       # The number of ROB reads
system.cpu.rob.rob_writes                   194125448                       # The number of ROB writes
system.cpu.timesIdled                           54252                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                         3694968                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                    70907652                       # Number of Instructions Simulated
system.cpu.committedOps                      90682607                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               1.071311                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         1.071311                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.933436                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.933436                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                101982930                       # number of integer regfile reads
system.cpu.int_regfile_writes                56612163                       # number of integer regfile writes
system.cpu.fp_regfile_reads                        58                       # number of floating regfile reads
system.cpu.fp_regfile_writes                       45                       # number of floating regfile writes
system.cpu.cc_regfile_reads                 345107562                       # number of cc regfile reads
system.cpu.cc_regfile_writes                 38759661                       # number of cc regfile writes
system.cpu.misc_regfile_reads                44102170                       # number of misc regfile reads
system.cpu.misc_regfile_writes                  31840                       # number of misc regfile writes
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED  37982056000                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements            484814                       # number of replacements
system.cpu.dcache.tags.tagsinuse           510.868965                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            40339815                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs            485326                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             83.119007                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle         154595500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   510.868965                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.997791                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.997791                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           56                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          456                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses          84466838                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses         84466838                       # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED  37982056000                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data     21417711                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        21417711                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     18830642                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       18830642                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data        60188                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total         60188                       # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data        15309                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total        15309                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data        15919                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total        15919                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      40248353                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         40248353                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     40308541                       # number of overall hits
system.cpu.dcache.overall_hits::total        40308541                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data       562442                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        562442                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      1019259                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      1019259                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data        68672                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total        68672                       # number of SoftPFReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data          614                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total          614                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data      1581701                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        1581701                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      1650373                       # number of overall misses
system.cpu.dcache.overall_misses::total       1650373                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  14412910000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  14412910000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  14258561428                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  14258561428                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data      5705500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total      5705500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  28671471428                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  28671471428                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  28671471428                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  28671471428                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     21980153                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     21980153                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     19849901                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     19849901                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data       128860                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total       128860                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data        15923                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total        15923                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data        15919                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total        15919                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     41830054                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     41830054                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     41958914                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     41958914                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.025589                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.025589                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.051348                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.051348                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.532919                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.532919                       # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.038561                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.038561                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.037813                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.037813                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.039333                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.039333                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25625.593395                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 25625.593395                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 13989.144494                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 13989.144494                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data  9292.345277                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total  9292.345277                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 18126.985712                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 18126.985712                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 17372.722062                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 17372.722062                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs          115                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets      2956958                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                15                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets          131265                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs     7.666667                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets    22.526629                       # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks       484814                       # number of writebacks
system.cpu.dcache.writebacks::total            484814                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       263368                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       263368                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data       870698                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total       870698                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data          614                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total          614                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      1134066                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      1134066                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      1134066                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      1134066                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       299074                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       299074                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       148561                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       148561                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data        37704                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total        37704                       # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data       447635                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total       447635                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data       485339                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total       485339                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   7124794500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total   7124794500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   2343478471                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   2343478471                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1981400500                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1981400500                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data   9468272971                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total   9468272971                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  11449673471                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  11449673471                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.013607                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.013607                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.007484                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.007484                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.292597                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.292597                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.010701                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.010701                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.011567                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.011567                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23822.848191                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23822.848191                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15774.520036                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15774.520036                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 52551.466688                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 52551.466688                       # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21151.770909                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 21151.770909                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23591.084728                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 23591.084728                       # average overall mshr miss latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED  37982056000                       # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements            325639                       # number of replacements
system.cpu.icache.tags.tagsinuse           510.373274                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs            22095836                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs            326151                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs             67.747258                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle        1176670500                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   510.373274                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.996823                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.996823                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           84                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1           67                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2           26                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3          328                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4            7                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses          45192862                       # Number of tag accesses
system.cpu.icache.tags.data_accesses         45192862                       # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED  37982056000                       # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst     22095836                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        22095836                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      22095836                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         22095836                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     22095836                       # number of overall hits
system.cpu.icache.overall_hits::total        22095836                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst       337513                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total        337513                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst       337513                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total         337513                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst       337513                       # number of overall misses
system.cpu.icache.overall_misses::total        337513                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst   5817859355                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total   5817859355                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst   5817859355                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total   5817859355                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst   5817859355                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total   5817859355                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     22433349                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     22433349                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     22433349                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     22433349                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     22433349                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     22433349                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.015045                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.015045                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.015045                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.015045                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.015045                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.015045                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17237.437832                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 17237.437832                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 17237.437832                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 17237.437832                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 17237.437832                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 17237.437832                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs       562602                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets           94                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs             26054                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               2                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    21.593690                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets           47                       # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks       325639                       # number of writebacks
system.cpu.icache.writebacks::total            325639                       # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst        11348                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total        11348                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst        11348                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total        11348                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst        11348                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total        11348                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst       326165                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total       326165                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst       326165                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total       326165                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst       326165                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total       326165                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   5383419413                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total   5383419413                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst   5383419413                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total   5383419413                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst   5383419413                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total   5383419413                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.014539                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.014539                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.014539                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.014539                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.014539                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.014539                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16505.202621                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16505.202621                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16505.202621                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 16505.202621                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16505.202621                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 16505.202621                       # average overall mshr miss latency
system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED  37982056000                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.prefetcher.num_hwpf_issued       823055                       # number of hwpf issued
system.cpu.l2cache.prefetcher.pfIdentified       826389                       # number of prefetch candidates identified
system.cpu.l2cache.prefetcher.pfBufferHit         2921                       # number of redundant prefetches already in prefetch queue
system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu.l2cache.prefetcher.pfSpanPage        78691                       # number of prefetches not generated due to page crossing
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED  37982056000                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements           125520                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        15698.936659                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs             681800                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           141835                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             4.806994                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 15629.036475                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher    69.900184                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.953921                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.004266                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.958187                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1022           27                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024        16288                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::1            8                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::2            1                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::3           14                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::4            4                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0          136                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1         2543                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2        12218                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3          510                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4          881                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1022     0.001648                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.994141                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         25499859                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        25499859                       # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED  37982056000                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks       257633                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total       257633                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks       472926                       # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total       472926                       # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       137172                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       137172                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst       289056                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total       289056                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data       255940                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total       255940                       # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst       289056                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data       393112                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total          682168                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst       289056                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data       393112                       # number of overall hits
system.cpu.l2cache.overall_hits::total         682168                       # number of overall hits
system.cpu.l2cache.UpgradeReq_misses::cpu.data           13                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total           13                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data        11425                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total        11425                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        37095                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total        37095                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data        80789                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total        80789                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst        37095                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data        92214                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        129309                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst        37095                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data        92214                       # number of overall misses
system.cpu.l2cache.overall_misses::total       129309                       # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   1226064500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   1226064500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   3155473000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total   3155473000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   6910815500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total   6910815500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst   3155473000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data   8136880000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  11292353000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst   3155473000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data   8136880000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  11292353000                       # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks       257633                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total       257633                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks       472926                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total       472926                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data           13                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total           13                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       148597                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       148597                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst       326151                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total       326151                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       336729                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total       336729                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst       326151                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data       485326                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total       811477                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst       326151                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data       485326                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total       811477                       # number of overall (read+write) accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data            1                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.076886                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.076886                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.113736                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.113736                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.239923                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.239923                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.113736                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.190004                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.159350                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.113736                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.190004                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.159350                       # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 107314.179431                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 107314.179431                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 85064.644831                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 85064.644831                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85541.540309                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85541.540309                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 85064.644831                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 88239.096016                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 87328.438082                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 85064.644831                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88239.096016                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 87328.438082                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.unused_prefetches              452                       # number of HardPF blocks evicted w/o reference
system.cpu.l2cache.writebacks::writebacks        97298                       # number of writebacks
system.cpu.l2cache.writebacks::total            97298                       # number of writebacks
system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data         3085                       # number of ReadExReq MSHR hits
system.cpu.l2cache.ReadExReq_mshr_hits::total         3085                       # number of ReadExReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst           23                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total           23                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data          119                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total          119                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst           23                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data         3204                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total         3227                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst           23                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data         3204                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total         3227                       # number of overall MSHR hits
system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher       115310                       # number of HardPFReq MSHR misses
system.cpu.l2cache.HardPFReq_mshr_misses::total       115310                       # number of HardPFReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           13                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total           13                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         8340                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total         8340                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        37072                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total        37072                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        80670                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total        80670                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        37072                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data        89010                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       126082                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        37072                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data        89010                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher       115310                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       241392                       # number of overall MSHR misses
system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher  10321796922                       # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_latency::total  10321796922                       # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       201500                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       201500                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    722790000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    722790000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   2931479000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   2931479000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   6418843000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   6418843000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   2931479000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   7141633000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  10073112000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   2931479000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   7141633000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher  10321796922                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  20394908922                       # number of overall MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.056125                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.056125                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.113665                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.113665                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.239570                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.239570                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.113665                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.183402                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.155373                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.113665                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.183402                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.297472                       # mshr miss rate for overall accesses
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 89513.458694                       # average HardPFReq mshr miss latency
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 89513.458694                       # average HardPFReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        15500                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        15500                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86665.467626                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86665.467626                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 79075.285930                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 79075.285930                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79569.145903                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79569.145903                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 79075.285930                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80234.052354                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 79893.339255                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 79075.285930                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80234.052354                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 89513.458694                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84488.752411                       # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests      1621957                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests       810494                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests        79908                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops        18773                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops        18772                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            1                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED  37982056000                       # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp        662893                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty       354931                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean       552820                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict        28222                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::HardPFReq       146565                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq           13                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp           13                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       148597                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       148597                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq       326165                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq       336729                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       977954                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      1455492                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           2433446                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     41714496                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     62088960                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          103803456                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                      272099                       # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic               6227968                       # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples      1083589                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        0.091107                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.287765                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0             984867     90.89%     90.89% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1              98721      9.11%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  1      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        1083589                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy     1621431500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          4.3                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy     489373744                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          1.3                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy     728066857                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          1.9                       # Layer utilization (%)
system.membus.snoop_filter.tot_requests        348152                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests       205320                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED  37982056000                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp             214278                       # Transaction distribution
system.membus.trans_dist::WritebackDirty        97298                       # Transaction distribution
system.membus.trans_dist::CleanEvict            28222                       # Transaction distribution
system.membus.trans_dist::UpgradeReq               13                       # Transaction distribution
system.membus.trans_dist::ReadExReq              8340                       # Transaction distribution
system.membus.trans_dist::ReadExResp             8340                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        214279                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       570770                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 570770                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     20474624                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                20474624                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples            222632                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                  222632    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total              222632                       # Request fanout histogram
system.membus.reqLayer0.occupancy           835899979                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               2.2                       # Layer utilization (%)
system.membus.respLayer1.occupancy         1175524166                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              3.1                       # Layer utilization (%)

---------- End Simulation Statistics   ----------