path: root/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.026649                       # Number of seconds simulated
sim_ticks                                 26649062500                       # Number of ticks simulated
final_tick                                26649062500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  95593                       # Simulator instruction rate (inst/s)
host_op_rate                                   135659                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               35926621                       # Simulator tick rate (ticks/s)
host_mem_usage                                 255136                       # Number of bytes of host memory used
host_seconds                                   741.76                       # Real time elapsed on the host
sim_insts                                    70907629                       # Number of instructions simulated
sim_ops                                     100626876                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst            298304                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           7942464                       # Number of bytes read from this memory
system.physmem.bytes_read::total              8240768                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       298304                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          298304                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      5372800                       # Number of bytes written to this memory
system.physmem.bytes_written::total           5372800                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst               4661                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             124101                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                128762                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           83950                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                83950                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst             11193790                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data            298039152                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total               309232942                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst        11193790                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total           11193790                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks         201613096                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total              201613096                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks         201613096                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst            11193790                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data           298039152                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              510846038                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        128763                       # Total number of read requests seen
system.physmem.writeReqs                        83950                       # Total number of write requests seen
system.physmem.cpureqs                         213025                       # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead                      8240768                       # Total number of bytes read from memory
system.physmem.bytesWritten                   5372800                       # Total number of bytes written to memory
system.physmem.bytesConsumedRd                8240768                       # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr                5372800                       # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ                        2                       # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite                312                       # Reqs where no action is needed
system.physmem.perBankRdReqs::0                  8141                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::1                  8383                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::2                  8250                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::3                  8168                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::4                  8300                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::5                  8450                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::6                  8090                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::7                  7962                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::8                  8062                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::9                  7609                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::10                 7789                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::11                 7813                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::12                 7880                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::13                 7885                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::14                 7974                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::15                 8005                       # Track reads on a per bank basis
system.physmem.perBankWrReqs::0                  5180                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::1                  5377                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::2                  5289                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::3                  5158                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::4                  5268                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::5                  5519                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::6                  5208                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::7                  5049                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::8                  5031                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::9                  5089                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::10                 5253                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::11                 5145                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::12                 5343                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::13                 5363                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::14                 5451                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::15                 5227                       # Track writes on a per bank basis
system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
system.physmem.numWrRetry                           0                       # Number of times wr buffer was full causing retry
system.physmem.totGap                     26649044000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
system.physmem.readPktSize::2                       0                       # Categorize read packet sizes
system.physmem.readPktSize::3                       0                       # Categorize read packet sizes
system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
system.physmem.readPktSize::6                  128763                       # Categorize read packet sizes
system.physmem.writePktSize::0                      0                       # Categorize write packet sizes
system.physmem.writePktSize::1                      0                       # Categorize write packet sizes
system.physmem.writePktSize::2                      0                       # Categorize write packet sizes
system.physmem.writePktSize::3                      0                       # Categorize write packet sizes
system.physmem.writePktSize::4                      0                       # Categorize write packet sizes
system.physmem.writePktSize::5                      0                       # Categorize write packet sizes
system.physmem.writePktSize::6                  83950                       # Categorize write packet sizes
system.physmem.rdQLenPdf::0                     75538                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     51656                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                      1500                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                        60                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         7                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                      3572                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                      3647                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                      3648                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                      3649                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                      3649                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                      3650                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                      3650                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                      3650                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                      3650                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                      3650                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                     3650                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                     3650                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                     3650                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                     3650                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                     3650                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     3650                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     3650                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     3650                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     3650                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     3650                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     3650                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     3650                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     3650                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                       78                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        3                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        34891                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      390.104497                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     179.978164                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     858.430673                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::64-65          13421     38.47%     38.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-129         5383     15.43%     53.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192-193         3065      8.78%     62.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-257         2226      6.38%     69.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320-321         1625      4.66%     73.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-385         1388      3.98%     77.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448-449         1071      3.07%     80.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-513          870      2.49%     83.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576-577          590      1.69%     84.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-641          488      1.40%     86.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704-705          448      1.28%     87.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-769          588      1.69%     89.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832-833          296      0.85%     90.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-897          306      0.88%     91.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960-961          186      0.53%     91.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1025          205      0.59%     92.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088-1089          126      0.36%     92.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152-1153          210      0.60%     93.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216-1217          103      0.30%     93.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280-1281          233      0.67%     94.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344-1345          114      0.33%     94.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408-1409          336      0.96%     95.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472-1473          140      0.40%     95.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536-1537          305      0.87%     96.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600-1601           63      0.18%     96.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664-1665          139      0.40%     97.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728-1729           46      0.13%     97.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1792-1793           83      0.24%     97.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856-1857           24      0.07%     97.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920-1921           56      0.16%     97.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984-1985           22      0.06%     97.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2048-2049           58      0.17%     98.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112-2113           11      0.03%     98.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176-2177           27      0.08%     98.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240-2241           19      0.05%     98.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304-2305           23      0.07%     98.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368-2369           10      0.03%     98.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2432-2433           17      0.05%     98.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496-2497            8      0.02%     98.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2560-2561           14      0.04%     98.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2624-2625           16      0.05%     98.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688-2689           16      0.05%     98.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2752-2753            9      0.03%     98.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816-2817           15      0.04%     98.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880-2881            9      0.03%     98.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2944-2945            7      0.02%     98.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3008-3009            7      0.02%     98.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3072-3073           12      0.03%     98.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3136-3137            4      0.01%     98.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3200-3201           11      0.03%     98.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3264-3265            7      0.02%     98.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3328-3329            7      0.02%     98.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3392-3393            3      0.01%     98.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456-3457            9      0.03%     98.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3520-3521            3      0.01%     98.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3584-3585            7      0.02%     98.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3648-3649            3      0.01%     98.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3712-3713            3      0.01%     98.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3776-3777            2      0.01%     98.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3840-3841            7      0.02%     98.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3904-3905            2      0.01%     98.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3968-3969            5      0.01%     98.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4032-4033            2      0.01%     98.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4096-4097            4      0.01%     98.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4160-4161            1      0.00%     98.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4224-4225            3      0.01%     98.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4288-4289            2      0.01%     98.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4352-4353            7      0.02%     98.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4416-4417            2      0.01%     98.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4480-4481            4      0.01%     98.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4544-4545            1      0.00%     98.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4608-4609            3      0.01%     98.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4672-4673            1      0.00%     98.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4736-4737            3      0.01%     98.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4800-4801            4      0.01%     99.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4864-4865            4      0.01%     99.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4992-4993            4      0.01%     99.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5056-5057            1      0.00%     99.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5120-5121            3      0.01%     99.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5184-5185            4      0.01%     99.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5248-5249            2      0.01%     99.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5312-5313            2      0.01%     99.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5376-5377            4      0.01%     99.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5440-5441            1      0.00%     99.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5504-5505            1      0.00%     99.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5568-5569            7      0.02%     99.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5632-5633            1      0.00%     99.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5696-5697            2      0.01%     99.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5760-5761            2      0.01%     99.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5888-5889            3      0.01%     99.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6016-6017            2      0.01%     99.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6080-6081            1      0.00%     99.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6144-6145            3      0.01%     99.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6208-6209            4      0.01%     99.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6272-6273            2      0.01%     99.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6336-6337            2      0.01%     99.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6400-6401            3      0.01%     99.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6464-6465            3      0.01%     99.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6528-6529            3      0.01%     99.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6592-6593            3      0.01%     99.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6656-6657            3      0.01%     99.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6784-6785            2      0.01%     99.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6848-6849            1      0.00%     99.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6912-6913            2      0.01%     99.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6976-6977            2      0.01%     99.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7040-7041            1      0.00%     99.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7168-7169            1      0.00%     99.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7232-7233            2      0.01%     99.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7296-7297            2      0.01%     99.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7360-7361            1      0.00%     99.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7424-7425            1      0.00%     99.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7488-7489            3      0.01%     99.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7552-7553            2      0.01%     99.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7616-7617            4      0.01%     99.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7680-7681            1      0.00%     99.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7744-7745            1      0.00%     99.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7808-7809            2      0.01%     99.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7872-7873            2      0.01%     99.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7936-7937            2      0.01%     99.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8000-8001            1      0.00%     99.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8064-8065            3      0.01%     99.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8128-8129            3      0.01%     99.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8192-8193          238      0.68%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          34891                       # Bytes accessed per row activation
system.physmem.totQLat                     2799338750                       # Total cycles spent in queuing delays
system.physmem.totMemAccLat                4801886250                       # Sum of mem lat for all requests
system.physmem.totBusLat                    643800000                       # Total cycles spent in databus access
system.physmem.totBankLat                  1358747500                       # Total cycles spent in bank access
system.physmem.avgQLat                       21740.58                       # Average queueing delay per request
system.physmem.avgBankLat                    10552.48                       # Average bank access latency per request
system.physmem.avgBusLat                      4999.96                       # Average bus latency per request
system.physmem.avgMemAccLat                  37293.02                       # Average memory access latency
system.physmem.avgRdBW                         309.23                       # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW                         201.61                       # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW                 309.23                       # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW                 201.61                       # Average consumed write bandwidth in MB/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MB/s
system.physmem.busUtil                           3.99                       # Data bus utilization in percentage
system.physmem.avgRdQLen                         0.18                       # Average read queue length over time
system.physmem.avgWrQLen                        10.01                       # Average write queue length over time
system.physmem.readRowHits                     120254                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     57565                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   93.39                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  68.57                       # Row buffer hit rate for writes
system.physmem.avgGap                       125281.69                       # Average gap between requests
system.membus.throughput                    510846038                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq               26509                       # Transaction distribution
system.membus.trans_dist::ReadResp              26508                       # Transaction distribution
system.membus.trans_dist::Writeback             83950                       # Transaction distribution
system.membus.trans_dist::UpgradeReq              312                       # Transaction distribution
system.membus.trans_dist::UpgradeResp             312                       # Transaction distribution
system.membus.trans_dist::ReadExReq            102254                       # Transaction distribution
system.membus.trans_dist::ReadExResp           102254                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side       342099                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count                        342099                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side     13613568                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size                   13613568                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus               13613568                       # Total data (bytes)
system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy           926784500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               3.5                       # Layer utilization (%)
system.membus.respLayer1.occupancy         1200135938                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              4.5                       # Layer utilization (%)
system.cpu.branchPred.lookups                16620839                       # Number of BP lookups
system.cpu.branchPred.condPredicted          12757336                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect            602395                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             10635009                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                 7765773                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             73.020841                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 1824331                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect             113161                       # Number of incorrect RAS predictions.
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                 1946                       # Number of system calls
system.cpu.numCycles                         53298126                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles           12535190                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                       85154971                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    16620839                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches            9590104                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                      21184086                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 2355794                       # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles               10829442                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                   84                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles           551                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles           63                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                  11674707                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                181091                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples           46276167                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              2.576733                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.331391                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                 25111993     54.27%     54.27% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  2139332      4.62%     58.89% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                  1963886      4.24%     63.13% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                  2043329      4.42%     67.55% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  1467358      3.17%     70.72% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                  1375070      2.97%     73.69% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                   956833      2.07%     75.76% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                  1188482      2.57%     78.33% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                 10029884     21.67%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total             46276167                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.311847                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        1.597710                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 14619512                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles               9177970                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                  19466340                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               1388431                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                1623914                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved              3328977                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                104776                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts              116789336                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                361687                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                1623914                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 16330804                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                 2680643                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles        1000847                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                  19093672                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles               5546287                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              114905556                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                   219                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                  17136                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents               4693151                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents             1312                       # Number of times there has been no free registers
system.cpu.rename.RenamedOperands           115218637                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups             529387920                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups        529379803                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups              8117                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps              99132672                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                 16085965                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts              20302                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts          20297                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  13065620                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             29609265                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            22417131                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           3885027                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores          4397806                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  111472584                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded               35916                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 107208843                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            271699                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        10738438                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined     25737967                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved           2130                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples      46276167                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         2.316718                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.989507                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0            11020528     23.81%     23.81% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1             8094858     17.49%     41.31% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2             7429249     16.05%     57.36% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3             7154901     15.46%     72.82% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4             5386733     11.64%     84.46% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5             3906460      8.44%     92.90% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6             1842144      3.98%     96.89% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7              871664      1.88%     98.77% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8              569630      1.23%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total        46276167                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                  112593      4.57%      4.57% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%      4.57% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%      4.57% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     2      0.00%      4.57% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%      4.57% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%      4.57% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%      4.57% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%      4.57% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      4.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%      4.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      4.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%      4.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%      4.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%      4.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%      4.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%      4.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      4.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%      4.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      4.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      4.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      4.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      4.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      4.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      4.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      4.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      4.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      4.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      4.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      4.57% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                1348878     54.73%     59.30% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite               1003122     40.70%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu              56608598     52.80%     52.80% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                91438      0.09%     52.89% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     52.89% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                 251      0.00%     52.89% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     52.89% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     52.89% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     52.89% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     52.89% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     52.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     52.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     52.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     52.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     52.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     52.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     52.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     52.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     52.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     52.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     52.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     52.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     52.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     52.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     52.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     52.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     52.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              7      0.00%     52.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     52.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     52.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     52.89% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             28894537     26.95%     79.84% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite            21614012     20.16%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              107208843                       # Type of FU issued
system.cpu.iq.rate                           2.011494                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                     2464595                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.022989                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads          263429476                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         122274650                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses    105524045                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                 671                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes               1168                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses          196                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              109673111                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                     327                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          2189921                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      2302157                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses         6684                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        29801                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      1861393                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads           27                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked           724                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                1623914                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                 1145014                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                 48197                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           111518283                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            295309                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              29609265                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             22417131                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts              19996                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                   6449                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                  5406                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          29801                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         392238                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       181031                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts               573269                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             106181942                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              28595303                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           1026901                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                          9783                       # number of nop insts executed
system.cpu.iew.exec_refs                     49924361                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 14597950                       # Number of branches executed
system.cpu.iew.exec_stores                   21329058                       # Number of stores executed
system.cpu.iew.exec_rate                     1.992227                       # Inst execution rate
system.cpu.iew.wb_sent                      105744224                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                     105524241                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                  53247487                       # num instructions producing a value
system.cpu.iew.wb_consumers                 103444790                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.979887                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.514743                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts        10886753                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls           33786                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts            499558                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples     44652253                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     2.253692                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.763005                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0     15559873     34.85%     34.85% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     11688259     26.18%     61.02% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2      3454288      7.74%     68.76% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3      2872185      6.43%     75.19% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      1868727      4.19%     79.38% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      1932277      4.33%     83.70% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6       683931      1.53%     85.24% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7       562545      1.26%     86.50% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      6030168     13.50%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total     44652253                       # Number of insts commited each cycle
system.cpu.commit.committedInsts             70913181                       # Number of instructions committed
system.cpu.commit.committedOps              100632428                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       47862846                       # Number of memory references committed
system.cpu.commit.loads                      27307108                       # Number of loads committed
system.cpu.commit.membars                       15920                       # Number of memory barriers committed
system.cpu.commit.branches                   13741485                       # Number of branches committed
system.cpu.commit.fp_insts                         56                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                  91472779                       # Number of committed integer instructions.
system.cpu.commit.function_calls              1679850                       # Number of function calls committed.
system.cpu.commit.bw_lim_events               6030168                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                    150115967                       # The number of ROB reads
system.cpu.rob.rob_writes                   224671489                       # The number of ROB writes
system.cpu.timesIdled                           79206                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                         7021959                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                    70907629                       # Number of Instructions Simulated
system.cpu.committedOps                     100626876                       # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total              70907629                       # Number of Instructions Simulated
system.cpu.cpi                               0.751656                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.751656                       # CPI: Total CPI of All Threads
system.cpu.ipc                               1.330396                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         1.330396                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                511415343                       # number of integer regfile reads
system.cpu.int_regfile_writes               103300902                       # number of integer regfile writes
system.cpu.fp_regfile_reads                      1012                       # number of floating regfile reads
system.cpu.fp_regfile_writes                      876                       # number of floating regfile writes
system.cpu.misc_regfile_reads                49160884                       # number of misc regfile reads
system.cpu.misc_regfile_writes                  31840                       # number of misc regfile writes
system.cpu.toL2Bus.throughput               776266857                       # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq          87116                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp         87115                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback       129077                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq          326                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp          326                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       107039                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       107039                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side        62962                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side       454559                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count                   517521                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side      1998208                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side     18655488                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size              20653696                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus          20653696                       # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus        33088                       # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy      290859995                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          1.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy      47617981                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.2                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy     243817935                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.9                       # Layer utilization (%)
system.cpu.icache.replacements                  29381                       # number of replacements
system.cpu.icache.tagsinuse               1810.408207                       # Cycle average of tags in use
system.cpu.icache.total_refs                 11639182                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                  31418                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs                 370.462219                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst    1810.408207                       # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst      0.883988                       # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total         0.883988                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst     11639193                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        11639193                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      11639193                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         11639193                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     11639193                       # number of overall hits
system.cpu.icache.overall_hits::total        11639193                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst        35513                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total         35513                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst        35513                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total          35513                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst        35513                       # number of overall misses
system.cpu.icache.overall_misses::total         35513                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    845054999                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    845054999                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    845054999                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    845054999                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    845054999                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    845054999                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     11674706                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     11674706                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     11674706                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     11674706                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     11674706                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     11674706                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.003042                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.003042                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.003042                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.003042                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.003042                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.003042                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23795.652268                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 23795.652268                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 23795.652268                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 23795.652268                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 23795.652268                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 23795.652268                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs         1082                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                27                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    40.074074                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst         3773                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total         3773                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst         3773                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total         3773                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst         3773                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total         3773                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst        31740                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total        31740                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst        31740                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total        31740                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst        31740                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total        31740                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    686303518                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    686303518                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    686303518                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    686303518                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    686303518                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    686303518                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.002719                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.002719                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.002719                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.002719                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.002719                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.002719                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21622.669124                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21622.669124                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21622.669124                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 21622.669124                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21622.669124                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 21622.669124                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.replacements                 95633                       # number of replacements
system.cpu.l2cache.tagsinuse             29922.978563                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                   88824                       # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs                126744                       # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs                  0.700814                       # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 26721.791186                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst   1373.170594                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data   1828.016782                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks     0.815484                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst     0.041906                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data     0.055787                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total        0.913177                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst        26545                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data        33468                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total          60013                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks       129077                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total       129077                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data           14                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total           14                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data         4785                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total         4785                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst        26545                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data        38253                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total           64798                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst        26545                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data        38253                       # number of overall hits
system.cpu.l2cache.overall_hits::total          64798                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst         4678                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data        21908                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total        26586                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data          312                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total          312                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       102254                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       102254                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst         4678                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       124162                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        128840                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         4678                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       124162                       # number of overall misses
system.cpu.l2cache.overall_misses::total       128840                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    388339000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data   1848175500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   2236514500                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data        22500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total        22500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   8303975500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   8303975500                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    388339000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  10152151000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  10540490000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    388339000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  10152151000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  10540490000                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst        31223                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data        55376                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total        86599                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks       129077                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total       129077                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data          326                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total          326                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       107039                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       107039                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst        31223                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data       162415                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total       193638                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst        31223                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data       162415                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total       193638                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.149825                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.395623                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.307001                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.957055                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.957055                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.955297                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.955297                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.149825                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.764474                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.665365                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.149825                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.764474                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.665365                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 83013.894827                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 84360.758627                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 84123.768149                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data    72.115385                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total    72.115385                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81209.297436                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81209.297436                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83013.894827                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81765.362994                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 81810.695436                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83013.894827                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81765.362994                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 81810.695436                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        83950                       # number of writebacks
system.cpu.l2cache.writebacks::total            83950                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           16                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           61                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total           77                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst           16                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data           61                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           77                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst           16                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data           61                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           77                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         4662                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        21847                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total        26509                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data          312                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total          312                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       102254                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       102254                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         4662                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       124101                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       128763                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         4662                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       124101                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       128763                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    329021750                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1573055250                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1902077000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data      3120312                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total      3120312                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   7046523750                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7046523750                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    329021750                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   8619579000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total   8948600750                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    329021750                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   8619579000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total   8948600750                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.149313                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.394521                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.306112                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.957055                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.957055                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.955297                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.955297                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.149313                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.764098                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.664968                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.149313                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.764098                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.664968                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 70575.235950                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 72003.261317                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71752.121921                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        10001                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        10001                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68911.961879                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68911.961879                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70575.235950                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69456.160708                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69496.678005                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70575.235950                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69456.160708                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69496.678005                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                 158319                       # number of replacements
system.cpu.dcache.tagsinuse               4069.477080                       # Cycle average of tags in use
system.cpu.dcache.total_refs                 44347755                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                 162415                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs                 273.052089                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle              350225000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data    4069.477080                       # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data      0.993525                       # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total         0.993525                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data     26048553                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        26048553                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     18266688                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       18266688                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data        15980                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total        15980                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data        15919                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total        15919                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      44315241                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         44315241                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     44315241                       # number of overall hits
system.cpu.dcache.overall_hits::total        44315241                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data       125407                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        125407                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      1583213                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      1583213                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data           44                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total           44                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data      1708620                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        1708620                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      1708620                       # number of overall misses
system.cpu.dcache.overall_misses::total       1708620                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data   5134620500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total   5134620500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 123147327479                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 123147327479                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       951500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total       951500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 128281947979                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 128281947979                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 128281947979                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 128281947979                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     26173960                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     26173960                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     19849901                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     19849901                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data        16024                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total        16024                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data        15919                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total        15919                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     46023861                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     46023861                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     46023861                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     46023861                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.004791                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.004791                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.079759                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.079759                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.002746                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.002746                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.037125                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.037125                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.037125                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.037125                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40943.651471                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 40943.651471                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77783.170981                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 77783.170981                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        21625                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        21625                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 75079.273319                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 75079.273319                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 75079.273319                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 75079.273319                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs         5184                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets         1288                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs               145                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets              16                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    35.751724                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets    80.500000                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       129077                       # number of writebacks
system.cpu.dcache.writebacks::total            129077                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data        69998                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total        69998                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1475881                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total      1475881                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data           44                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total           44                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      1545879                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      1545879                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      1545879                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      1545879                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data        55409                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total        55409                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       107332                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       107332                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data       162741                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total       162741                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data       162741                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total       162741                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   2243387065                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total   2243387065                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8465944990                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   8465944990                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  10709332055                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  10709332055                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  10709332055                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  10709332055                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002117                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002117                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.005407                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.005407                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.003536                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.003536                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.003536                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.003536                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40487.773918                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40487.773918                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78876.243711                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78876.243711                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65805.986537                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 65805.986537                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65805.986537                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 65805.986537                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------