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|
---------- Begin Simulation Statistics ----------
sim_seconds 0.031183 # Number of seconds simulated
sim_ticks 31183407000 # Number of ticks simulated
final_tick 31183407000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 157932 # Simulator instruction rate (inst/s)
host_tick_rate 48938242 # Simulator tick rate (ticks/s)
host_mem_usage 229072 # Number of bytes of host memory used
host_seconds 637.20 # Real time elapsed on the host
sim_insts 100634165 # Number of instructions simulated
system.physmem.bytes_read 8651648 # Number of bytes read from this memory
system.physmem.bytes_inst_read 350016 # Number of instructions bytes read from this memory
system.physmem.bytes_written 5661184 # Number of bytes written to this memory
system.physmem.num_reads 135182 # Number of read requests responded to by this memory
system.physmem.num_writes 88456 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
system.physmem.bw_read 277443962 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 11224431 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write 181544756 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total 458988718 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 1946 # Number of system calls
system.cpu.numCycles 62366815 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 17631068 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 11525225 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 822451 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 15041021 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 9743390 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 1887340 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 176888 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 12968459 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 88523933 # Number of instructions fetch has processed
system.cpu.fetch.Branches 17631068 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 11630730 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 22984896 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 2898005 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 23107334 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 15 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 525 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 12208408 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 230644 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 61059715 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.021356 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.077680 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 38090584 62.38% 62.38% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 2437224 3.99% 66.37% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 2605062 4.27% 70.64% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 2470326 4.05% 74.69% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 1717744 2.81% 77.50% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 1704134 2.79% 80.29% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 1004081 1.64% 81.93% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 1295541 2.12% 84.06% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 9735019 15.94% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 61059715 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.282700 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.419408 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 14872380 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 21838408 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 21376813 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 1070090 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 1902024 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 3467429 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 98061 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 120316029 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 332599 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 1902024 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 16801594 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 2005674 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 15516104 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 20489827 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 4344492 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 117017437 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 7 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 3607 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 2996198 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 60 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 118959985 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 538237718 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 538236225 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 1493 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 99144333 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 19815652 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 778147 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 778546 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 12135199 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 29749057 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 22305499 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 2463618 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 3436887 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 111737256 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 774255 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 107616850 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 306406 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 11658627 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 29328565 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 71223 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 61059715 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.762485 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.902924 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 22160160 36.29% 36.29% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 11614525 19.02% 55.31% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 8577298 14.05% 69.36% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 7396039 12.11% 81.47% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 4782616 7.83% 89.31% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 3521695 5.77% 95.07% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 1664317 2.73% 97.80% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 809749 1.33% 99.13% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 533316 0.87% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 61059715 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 88066 3.33% 3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 1488278 56.33% 59.66% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 1065734 40.34% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 57002654 52.97% 52.97% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 87399 0.08% 53.05% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 53.05% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 39 0.00% 53.05% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 53.05% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 53.05% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 53.05% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 53.05% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 53.05% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 53.05% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 53.05% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 53.05% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 53.05% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 53.05% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 53.05% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 53.05% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 53.05% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 53.05% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 53.05% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 53.05% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 53.05% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 53.05% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 53.05% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 53.05% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 53.05% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 53.05% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 53.05% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 53.05% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 53.05% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 28992824 26.94% 79.99% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 21533927 20.01% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 107616850 # Type of FU issued
system.cpu.iq.rate 1.725547 # Inst issue rate
system.cpu.iq.fu_busy_cnt 2642078 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.024551 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 279241693 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 124185257 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 105412682 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 206 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 204 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 76 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 110258821 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 107 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 1870348 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 2440492 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 3482 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 15956 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 1748305 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 52 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 53 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 1902024 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 953128 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 28578 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 112587966 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 618611 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 29749057 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 22305499 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 756996 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 1135 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 1192 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 15956 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 682416 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 198748 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 881164 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 106274273 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 28622040 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 1342577 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 76455 # number of nop insts executed
system.cpu.iew.exec_refs 49853649 # number of memory reference insts executed
system.cpu.iew.exec_branches 14601408 # Number of branches executed
system.cpu.iew.exec_stores 21231609 # Number of stores executed
system.cpu.iew.exec_rate 1.704020 # Inst execution rate
system.cpu.iew.wb_sent 105725224 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 105412758 # cumulative count of insts written-back
system.cpu.iew.wb_producers 52507879 # num instructions producing a value
system.cpu.iew.wb_consumers 101154765 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.690206 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.519085 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 100639717 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 11948697 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 703032 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 788200 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 59157692 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.701211 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.430896 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 26246617 44.37% 44.37% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 14635662 24.74% 69.11% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 4223894 7.14% 76.25% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 3641491 6.16% 82.40% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 2268632 3.83% 86.24% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 1889350 3.19% 89.43% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 703853 1.19% 90.62% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 498146 0.84% 91.46% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 5050047 8.54% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 59157692 # Number of insts commited each cycle
system.cpu.commit.count 100639717 # Number of instructions committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 47865759 # Number of memory references committed
system.cpu.commit.loads 27308565 # Number of loads committed
system.cpu.commit.membars 15920 # Number of memory barriers committed
system.cpu.commit.branches 13670084 # Number of branches committed
system.cpu.commit.fp_insts 56 # Number of committed floating point instructions.
system.cpu.commit.int_insts 91478611 # Number of committed integer instructions.
system.cpu.commit.function_calls 1679850 # Number of function calls committed.
system.cpu.commit.bw_lim_events 5050047 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 166670760 # The number of ROB reads
system.cpu.rob.rob_writes 227084538 # The number of ROB writes
system.cpu.timesIdled 61622 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 1307100 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 100634165 # Number of Instructions Simulated
system.cpu.committedInsts_total 100634165 # Number of Instructions Simulated
system.cpu.cpi 0.619738 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.619738 # CPI: Total CPI of All Threads
system.cpu.ipc 1.613585 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.613585 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 511657086 # number of integer regfile reads
system.cpu.int_regfile_writes 103892124 # number of integer regfile writes
system.cpu.fp_regfile_reads 166 # number of floating regfile reads
system.cpu.fp_regfile_writes 126 # number of floating regfile writes
system.cpu.misc_regfile_reads 146210782 # number of misc regfile reads
system.cpu.misc_regfile_writes 34752 # number of misc regfile writes
system.cpu.icache.replacements 26083 # number of replacements
system.cpu.icache.tagsinuse 1805.405384 # Cycle average of tags in use
system.cpu.icache.total_refs 12179175 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 28115 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 433.191357 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::0 1805.405384 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.881546 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 12179178 # number of ReadReq hits
system.cpu.icache.demand_hits 12179178 # number of demand (read+write) hits
system.cpu.icache.overall_hits 12179178 # number of overall hits
system.cpu.icache.ReadReq_misses 29230 # number of ReadReq misses
system.cpu.icache.demand_misses 29230 # number of demand (read+write) misses
system.cpu.icache.overall_misses 29230 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 357885000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 357885000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 357885000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 12208408 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 12208408 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 12208408 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.002394 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.002394 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.002394 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 12243.756415 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 12243.756415 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 12243.756415 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks 1 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits 1069 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 1069 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 1069 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 28161 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 28161 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 28161 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency 246973000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 246973000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 246973000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.002307 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.002307 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.002307 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 8770.036575 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 8770.036575 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 8770.036575 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 157879 # number of replacements
system.cpu.dcache.tagsinuse 4072.329363 # Cycle average of tags in use
system.cpu.dcache.total_refs 44742203 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 161975 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 276.229066 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 306596000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 4072.329363 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.994221 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 26395464 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 18310275 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits 18919 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits 17375 # number of StoreCondReq hits
system.cpu.dcache.demand_hits 44705739 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 44705739 # number of overall hits
system.cpu.dcache.ReadReq_misses 108834 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 1539626 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses 27 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses 1648460 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 1648460 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 2418698500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 52283649500 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency 386000 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency 54702348000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 54702348000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 26504298 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses 19849901 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses 18946 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses 17375 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses 46354199 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 46354199 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.004106 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.077563 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate 0.001425 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate 0.035562 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.035562 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 22223.739824 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 33958.668859 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency 14296.296296 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency 33183.909831 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 33183.909831 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 190500 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 10 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 19050 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks 123472 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits 53734 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 1432703 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits 27 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits 1486437 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 1486437 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 55100 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 106923 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses 162023 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 162023 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency 1035726000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 3662471000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 4698197000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 4698197000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.002079 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate 0.005387 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate 0.003495 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.003495 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18797.205082 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34253.350542 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 28997.099177 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 28997.099177 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 114920 # number of replacements
system.cpu.l2cache.tagsinuse 18304.700184 # Cycle average of tags in use
system.cpu.l2cache.total_refs 72415 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 133774 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.541323 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::0 2370.650310 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 15934.049874 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.072347 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.486269 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 50510 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits 123473 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits 16 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits 4309 # number of ReadExReq hits
system.cpu.l2cache.demand_hits 54819 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 54819 # number of overall hits
system.cpu.l2cache.ReadReq_misses 32664 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses 31 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses 102598 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 135262 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 135262 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 1118309000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 3526121000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 4644430000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 4644430000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 83174 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 123473 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses 47 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 106907 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 190081 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 190081 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.392719 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate 0.659574 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate 0.959694 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.711602 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.711602 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 34236.743816 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 34368.321020 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 34336.546850 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 34336.546850 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks 88456 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits 80 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits 80 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits 80 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses 32584 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses 31 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses 102598 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses 135182 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 135182 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 1012754000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 962000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 3197891500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 4210645500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 4210645500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.391757 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.659574 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.959694 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.711181 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.711181 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31081.328259 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31032.258065 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31169.140724 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31147.974582 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31147.974582 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
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