path: root/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.025431                       # Number of seconds simulated
sim_ticks                                 25431292500                       # Number of ticks simulated
final_tick                                25431292500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 123125                       # Simulator instruction rate (inst/s)
host_op_rate                                   174730                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               44159257                       # Simulator tick rate (ticks/s)
host_mem_usage                                 270444                       # Number of bytes of host memory used
host_seconds                                   575.90                       # Real time elapsed on the host
sim_insts                                    70907629                       # Number of instructions simulated
sim_ops                                     100626876                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst            300416                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           7942976                       # Number of bytes read from this memory
system.physmem.bytes_read::total              8243392                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       300416                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          300416                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      5372352                       # Number of bytes written to this memory
system.physmem.bytes_written::total           5372352                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst               4694                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             124109                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                128803                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           83943                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                83943                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst             11812848                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data            312330803                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total               324143651                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst        11812848                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total           11812848                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks         211249664                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total              211249664                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks         211249664                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst            11812848                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data           312330803                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              535393315                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        128804                       # Number of read requests accepted
system.physmem.writeReqs                        83943                       # Number of write requests accepted
system.physmem.readBursts                      128804                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                      83943                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                  8243072                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                       384                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   5371136                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                   8243456                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                5372352                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                        6                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs            342                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                8140                       # Per bank write bursts
system.physmem.perBankRdBursts::1                8383                       # Per bank write bursts
system.physmem.perBankRdBursts::2                8248                       # Per bank write bursts
system.physmem.perBankRdBursts::3                8172                       # Per bank write bursts
system.physmem.perBankRdBursts::4                8304                       # Per bank write bursts
system.physmem.perBankRdBursts::5                8450                       # Per bank write bursts
system.physmem.perBankRdBursts::6                8104                       # Per bank write bursts
system.physmem.perBankRdBursts::7                7960                       # Per bank write bursts
system.physmem.perBankRdBursts::8                8081                       # Per bank write bursts
system.physmem.perBankRdBursts::9                7608                       # Per bank write bursts
system.physmem.perBankRdBursts::10               7787                       # Per bank write bursts
system.physmem.perBankRdBursts::11               7813                       # Per bank write bursts
system.physmem.perBankRdBursts::12               7882                       # Per bank write bursts
system.physmem.perBankRdBursts::13               7882                       # Per bank write bursts
system.physmem.perBankRdBursts::14               7972                       # Per bank write bursts
system.physmem.perBankRdBursts::15               8012                       # Per bank write bursts
system.physmem.perBankWrBursts::0                5177                       # Per bank write bursts
system.physmem.perBankWrBursts::1                5376                       # Per bank write bursts
system.physmem.perBankWrBursts::2                5291                       # Per bank write bursts
system.physmem.perBankWrBursts::3                5156                       # Per bank write bursts
system.physmem.perBankWrBursts::4                5265                       # Per bank write bursts
system.physmem.perBankWrBursts::5                5517                       # Per bank write bursts
system.physmem.perBankWrBursts::6                5200                       # Per bank write bursts
system.physmem.perBankWrBursts::7                5050                       # Per bank write bursts
system.physmem.perBankWrBursts::8                5030                       # Per bank write bursts
system.physmem.perBankWrBursts::9                5089                       # Per bank write bursts
system.physmem.perBankWrBursts::10               5251                       # Per bank write bursts
system.physmem.perBankWrBursts::11               5142                       # Per bank write bursts
system.physmem.perBankWrBursts::12               5343                       # Per bank write bursts
system.physmem.perBankWrBursts::13               5363                       # Per bank write bursts
system.physmem.perBankWrBursts::14               5451                       # Per bank write bursts
system.physmem.perBankWrBursts::15               5223                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                     25431274000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  128804                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                  83943                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                     74268                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     52779                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                      1686                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                        57                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         7                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                      634                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                      658                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     2213                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     3968                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     4721                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     5105                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     5202                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     5223                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     5297                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     5379                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     5443                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     5403                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     5565                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     5914                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     5677                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     6138                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     6027                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     5293                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                       56                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                       12                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        37764                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      360.466900                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     216.757090                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     343.203142                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          11986     31.74%     31.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255         7964     21.09%     52.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         3753      9.94%     62.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         2738      7.25%     70.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2422      6.41%     76.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1565      4.14%     80.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1215      3.22%     83.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1119      2.96%     86.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         5002     13.25%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          37764                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          5143                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        25.040249                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      360.430137                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023           5140     99.94%     99.94% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047            1      0.02%     99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-3071            1      0.02%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::24576-25599            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            5143                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          5143                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        16.318102                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       16.295777                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        0.900493                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16               4492     87.34%     87.34% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17                  9      0.17%     87.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18                404      7.86%     95.37% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19                175      3.40%     98.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20                 41      0.80%     99.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21                 14      0.27%     99.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22                  4      0.08%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23                  2      0.04%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::27                  2      0.04%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            5143                       # Writes before turning the bus around for reads
system.physmem.totQLat                     2477042500                       # Total ticks spent queuing
system.physmem.totMemAccLat                4892005000                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    643990000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       19232.00                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  37982.00                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                         324.13                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                         211.20                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                      324.15                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                      211.25                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           4.18                       # Data bus utilization in percentage
system.physmem.busUtilRead                       2.53                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      1.65                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.36                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        23.78                       # Average write queue length when enqueuing
system.physmem.readRowHits                     112907                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     62042                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   87.66                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  73.91                       # Row buffer hit rate for writes
system.physmem.avgGap                       119537.64                       # Average gap between requests
system.physmem.pageHitRate                      82.24                       # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE      10352020250                       # Time in different power states
system.physmem.memoryStateTime::REF         849160000                       # Time in different power states
system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
system.physmem.memoryStateTime::ACT       14228986000                       # Time in different power states
system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
system.membus.throughput                    535393315                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq               26553                       # Transaction distribution
system.membus.trans_dist::ReadResp              26552                       # Transaction distribution
system.membus.trans_dist::Writeback             83943                       # Transaction distribution
system.membus.trans_dist::UpgradeReq              342                       # Transaction distribution
system.membus.trans_dist::UpgradeResp             342                       # Transaction distribution
system.membus.trans_dist::ReadExReq            102251                       # Transaction distribution
system.membus.trans_dist::ReadExResp           102251                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       342234                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 342234                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     13615744                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total            13615744                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus               13615744                       # Total data (bytes)
system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy           901934500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               3.5                       # Layer utilization (%)
system.membus.respLayer1.occupancy         1187807158                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              4.7                       # Layer utilization (%)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.branchPred.lookups                17001662                       # Number of BP lookups
system.cpu.branchPred.condPredicted          13020210                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect            614898                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             10708539                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                 7958691                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             74.320979                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 1855518                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect             113838                       # Number of incorrect RAS predictions.
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                 1946                       # Number of system calls
system.cpu.numCycles                         50862586                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles           12841579                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                       87379296                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    17001662                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches            9814209                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                      21679126                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 2704202                       # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles                6435967                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                   67                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles           392                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles           76                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                  11938705                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                201875                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples           43012606                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              2.839331                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.389146                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                 21356489     49.65%     49.65% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  2172665      5.05%     54.70% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                  2009321      4.67%     59.37% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                  2081413      4.84%     64.21% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  1500240      3.49%     67.70% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                  1419840      3.30%     71.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                   985272      2.29%     73.29% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                  1219233      2.83%     76.13% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                 10268133     23.87%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total             43012606                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.334267                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        1.717948                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 13769056                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles               5959303                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                  20895341                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles                441693                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                1947213                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved              3430949                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                110387                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts              119589480                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                395300                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                1947213                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 14636498                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                  284865                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles        1020852                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                  20468957                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles               4654221                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              117623188                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                   544                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                 181856                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents                2734092                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents                1628680                       # Number of times rename has blocked due to SQ full
system.cpu.rename.FullRegisterEvents             1673                       # Number of times there has been no free registers
system.cpu.rename.RenamedOperands           117928367                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups             541896046                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups        487330730                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups              3427                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps              99132672                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                 18795695                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts              20563                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts          20550                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                   5392644                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             30100241                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            22927452                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           5590192                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores          5698921                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  113818479                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded               36102                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 108240105                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            379531                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        13068972                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined     32214297                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved           2316                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples      43012606                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         2.516474                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        2.084237                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0             9996470     23.24%     23.24% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1             6251950     14.54%     37.78% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2             6474591     15.05%     52.83% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3             6613067     15.37%     68.20% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4             5424130     12.61%     80.81% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5             4356381     10.13%     90.94% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6             2112627      4.91%     95.85% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7             1221535      2.84%     98.69% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8              561855      1.31%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total        43012606                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                  131486      5.24%      5.24% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      1      0.00%      5.24% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%      5.24% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%      5.24% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%      5.24% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%      5.24% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%      5.24% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%      5.24% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      5.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%      5.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      5.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%      5.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%      5.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%      5.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%      5.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%      5.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      5.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%      5.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      5.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      5.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      5.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      5.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      5.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      5.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      5.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      5.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      5.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      5.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      5.24% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                1416079     56.44%     61.68% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                961652     38.32%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu              57280619     52.92%     52.92% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                91502      0.08%     53.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     53.00% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                 249      0.00%     53.00% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     53.00% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     53.00% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     53.00% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     53.00% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     53.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     53.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     53.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     53.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     53.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     53.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     53.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     53.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     53.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     53.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     53.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     53.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     53.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     53.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     53.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     53.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     53.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              7      0.00%     53.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     53.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     53.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     53.00% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             29070055     26.86%     79.86% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite            21797673     20.14%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              108240105                       # Type of FU issued
system.cpu.iq.rate                           2.128089                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                     2509218                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.023182                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads          262380760                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         126960554                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses    106504533                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                 805                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes               1416                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses          198                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              110748938                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                     385                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          2726538                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      2793133                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses         5994                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        39986                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      2371714                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads           30                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked           777                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                1947213                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                   83242                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                154560                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           113864521                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            271261                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              30100241                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             22927452                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts              20182                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                  11127                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                139253                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          39986                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         397706                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       183440                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts               581146                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             107196907                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              28742416                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           1043198                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                          9940                       # number of nop insts executed
system.cpu.iew.exec_refs                     50252614                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 14716112                       # Number of branches executed
system.cpu.iew.exec_stores                   21510198                       # Number of stores executed
system.cpu.iew.exec_rate                     2.107579                       # Inst execution rate
system.cpu.iew.wb_sent                      106740577                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                     106504731                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                  57038202                       # num instructions producing a value
system.cpu.iew.wb_consumers                 114479064                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       2.093970                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.498241                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts        13236328                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls           33786                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts            506712                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples     41065393                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     2.450541                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.921831                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0     14078032     34.28%     34.28% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     10319124     25.13%     59.41% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2      2761047      6.72%     66.13% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3      2619650      6.38%     72.51% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      1508272      3.67%     76.19% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      1822351      4.44%     80.62% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6       663911      1.62%     82.24% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7       540097      1.32%     83.56% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      6752909     16.44%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total     41065393                       # Number of insts commited each cycle
system.cpu.commit.committedInsts             70913181                       # Number of instructions committed
system.cpu.commit.committedOps              100632428                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       47862846                       # Number of memory references committed
system.cpu.commit.loads                      27307108                       # Number of loads committed
system.cpu.commit.membars                       15920                       # Number of memory barriers committed
system.cpu.commit.branches                   13741485                       # Number of branches committed
system.cpu.commit.fp_insts                         56                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                  91472779                       # Number of committed integer instructions.
system.cpu.commit.function_calls              1679850                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu         52689456     52.36%     52.36% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult           80119      0.08%     52.44% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv                0      0.00%     52.44% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd              0      0.00%     52.44% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp              0      0.00%     52.44% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt              0      0.00%     52.44% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             0      0.00%     52.44% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv              0      0.00%     52.44% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     52.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     52.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     52.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     52.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     52.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     52.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     52.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     52.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     52.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     52.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     52.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     52.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     52.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     52.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     52.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     52.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     52.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc            7      0.00%     52.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     52.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     52.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     52.44% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead        27307108     27.14%     79.57% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite       20555738     20.43%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total         100632428                       # Class of committed instruction
system.cpu.commit.bw_lim_events               6752909                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                    148155941                       # The number of ROB reads
system.cpu.rob.rob_writes                   229697127                       # The number of ROB writes
system.cpu.timesIdled                           83826                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                         7849980                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                    70907629                       # Number of Instructions Simulated
system.cpu.committedOps                     100626876                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               0.717308                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.717308                       # CPI: Total CPI of All Threads
system.cpu.ipc                               1.394102                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         1.394102                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                515806241                       # number of integer regfile reads
system.cpu.int_regfile_writes               104262317                       # number of integer regfile writes
system.cpu.fp_regfile_reads                      1054                       # number of floating regfile reads
system.cpu.fp_regfile_writes                      938                       # number of floating regfile writes
system.cpu.misc_regfile_reads                49641533                       # number of misc regfile reads
system.cpu.misc_regfile_writes                  31840                       # number of misc regfile writes
system.cpu.toL2Bus.throughput               820945141                       # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq          90021                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp         90020                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback       129157                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq          357                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp          357                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       107037                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       107037                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        68737                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       454707                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total            523444                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2182208                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     18660800                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total       20843008                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus          20843008                       # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus        34688                       # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy      292444997                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          1.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy      52710982                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.2                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy     261104274                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          1.0                       # Layer utilization (%)
system.cpu.icache.tags.replacements             32259                       # number of replacements
system.cpu.icache.tags.tagsinuse          1808.767041                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs            11900174                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs             34296                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs            346.984313                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst  1808.767041                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.883187                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.883187                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024         2037                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           84                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1           24                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3         1255                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4          674                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.994629                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses          23912047                       # Number of tag accesses
system.cpu.icache.tags.data_accesses         23912047                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst     11900181                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        11900181                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      11900181                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         11900181                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     11900181                       # number of overall hits
system.cpu.icache.overall_hits::total        11900181                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst        38523                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total         38523                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst        38523                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total          38523                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst        38523                       # number of overall misses
system.cpu.icache.overall_misses::total         38523                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    840683730                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    840683730                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    840683730                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    840683730                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    840683730                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    840683730                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     11938704                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     11938704                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     11938704                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     11938704                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     11938704                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     11938704                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.003227                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.003227                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.003227                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.003227                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.003227                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.003227                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21822.903979                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 21822.903979                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 21822.903979                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 21822.903979                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 21822.903979                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 21822.903979                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs         1168                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                29                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    40.275862                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst         3883                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total         3883                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst         3883                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total         3883                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst         3883                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total         3883                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst        34640                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total        34640                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst        34640                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total        34640                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst        34640                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total        34640                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    683348518                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    683348518                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    683348518                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    683348518                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    683348518                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    683348518                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.002901                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.002901                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.002901                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.002901                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.002901                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.002901                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19727.151212                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19727.151212                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19727.151212                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 19727.151212                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19727.151212                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 19727.151212                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements            95674                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        29835.516778                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs              91740                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           126786                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             0.723581                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 26618.880266                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  1380.164406                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data  1836.472106                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.812344                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.042119                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.056045                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.910508                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        31112                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0          138                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1         1913                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2        20923                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         7751                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4          387                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.949463                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses          2842080                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses         2842080                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst        29388                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data        33459                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total          62847                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks       129157                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total       129157                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data           15                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total           15                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data         4786                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total         4786                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst        29388                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data        38245                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total           67633                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst        29388                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data        38245                       # number of overall hits
system.cpu.l2cache.overall_hits::total          67633                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst         4710                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data        21922                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total        26632                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data          342                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total          342                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       102251                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       102251                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst         4710                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       124173                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        128883                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         4710                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       124173                       # number of overall misses
system.cpu.l2cache.overall_misses::total       128883                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    353854250                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data   1815685750                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   2169540000                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data        46498                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total        46498                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   8365864000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   8365864000                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    353854250                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  10181549750                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  10535404000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    353854250                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  10181549750                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  10535404000                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst        34098                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data        55381                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total        89479                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks       129157                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total       129157                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data          357                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total          357                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       107037                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       107037                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst        34098                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data       162418                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total       196516                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst        34098                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data       162418                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total       196516                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.138131                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.395840                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.297634                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.957983                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.957983                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.955286                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.955286                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.138131                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.764527                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.655840                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.138131                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.764527                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.655840                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75128.290870                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82824.822097                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 81463.652749                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data   135.959064                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total   135.959064                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81816.940666                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81816.940666                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75128.290870                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81994.876100                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 81743.938301                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75128.290870                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81994.876100                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 81743.938301                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        83943                       # number of writebacks
system.cpu.l2cache.writebacks::total            83943                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           15                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           64                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total           79                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst           15                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data           64                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           79                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst           15                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data           64                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           79                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         4695                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        21858                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total        26553                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data          342                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total          342                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       102251                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       102251                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         4695                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       124109                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       128804                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         4695                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       124109                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       128804                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    294197750                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1539385750                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1833583500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data      3432342                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total      3432342                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   7104890000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7104890000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    294197750                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   8644275750                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total   8938473500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    294197750                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   8644275750                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total   8938473500                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.137691                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.394684                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.296751                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.957983                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.957983                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.955286                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.955286                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.137691                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.764133                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.655438                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.137691                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.764133                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.655438                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62661.927583                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70426.651569                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69053.722743                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10036.087719                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10036.087719                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69484.797215                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69484.797215                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62661.927583                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69650.676019                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69395.931027                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62661.927583                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69650.676019                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69395.931027                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements            158322                       # number of replacements
system.cpu.dcache.tags.tagsinuse          4067.859586                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            43957323                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs            162418                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs            270.643174                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle         358577250                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data  4067.859586                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.993130                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.993130                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           65                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1         1830                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2         2201                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses          91492426                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses         91492426                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data     25658218                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        25658218                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     18266460                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       18266460                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data        16005                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total        16005                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data        15919                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total        15919                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      43924678                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         43924678                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     43924678                       # number of overall hits
system.cpu.dcache.overall_hits::total        43924678                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data       124918                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        124918                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      1583441                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      1583441                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data           43                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total           43                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data      1708359                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        1708359                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      1708359                       # number of overall misses
system.cpu.dcache.overall_misses::total       1708359                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data   5184955254                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total   5184955254                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 125206065525                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 125206065525                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       993000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total       993000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 130391020779                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 130391020779                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 130391020779                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 130391020779                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     25783136                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     25783136                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     19849901                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     19849901                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data        16048                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total        16048                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data        15919                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total        15919                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     45633037                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     45633037                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     45633037                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     45633037                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.004845                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.004845                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.079771                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.079771                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.002679                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.002679                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.037437                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.037437                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.037437                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.037437                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41506.870539                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 41506.870539                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 79072.138163                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 79072.138163                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 23093.023256                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 23093.023256                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 76325.304447                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 76325.304447                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 76325.304447                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 76325.304447                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs         4253                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets         1744                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs               139                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets              22                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    30.597122                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets    79.272727                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       129157                       # number of writebacks
system.cpu.dcache.writebacks::total            129157                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data        69501                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total        69501                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1476084                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total      1476084                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data           42                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total           42                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      1545585                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      1545585                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      1545585                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      1545585                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data        55417                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total        55417                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       107357                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       107357                       # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data            1                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total            1                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data       162774                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total       162774                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data       162774                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total       162774                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   2210443817                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total   2210443817                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8528691900                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   8528691900                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data        11000                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total        11000                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  10739135717                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  10739135717                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  10739135717                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  10739135717                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002149                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002149                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.005408                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.005408                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.000062                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.000062                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.003567                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.003567                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.003567                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.003567                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39887.468051                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39887.468051                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79442.345632                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79442.345632                       # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data        11000                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total        11000                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65975.743774                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 65975.743774                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65975.743774                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 65975.743774                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------