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|
---------- Begin Simulation Statistics ----------
sim_seconds 0.132689 # Number of seconds simulated
sim_ticks 132689045000 # Number of ticks simulated
final_tick 132689045000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 796611 # Simulator instruction rate (inst/s)
host_op_rate 1129615 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1502004709 # Simulator tick rate (ticks/s)
host_mem_usage 239164 # Number of bytes of host memory used
host_seconds 88.34 # Real time elapsed on the host
sim_insts 70373628 # Number of instructions simulated
sim_ops 99791654 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 255488 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 7924480 # Number of bytes read from this memory
system.physmem.bytes_read::total 8179968 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 255488 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 255488 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 5370176 # Number of bytes written to this memory
system.physmem.bytes_written::total 5370176 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 3992 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 123820 # Number of read requests responded to by this memory
system.physmem.num_reads::total 127812 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 83909 # Number of write requests responded to by this memory
system.physmem.num_writes::total 83909 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 1925464 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 59722187 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 61647651 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1925464 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1925464 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 40471887 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 40471887 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 40471887 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1925464 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 59722187 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 102119538 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 1946 # Number of system calls
system.cpu.numCycles 265378090 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 70373628 # Number of instructions committed
system.cpu.committedOps 99791654 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 91472780 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses
system.cpu.num_func_calls 3311620 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 10748863 # number of instructions that are conditional controls
system.cpu.num_int_insts 91472780 # number of integer instructions
system.cpu.num_fp_insts 56 # number of float instructions
system.cpu.num_int_register_reads 533542872 # number of times the integer registers were read
system.cpu.num_int_register_writes 96252285 # number of times the integer registers were written
system.cpu.num_fp_register_reads 36 # number of times the floating registers were read
system.cpu.num_fp_register_writes 20 # number of times the floating registers were written
system.cpu.num_mem_refs 47862847 # number of memory refs
system.cpu.num_load_insts 27307108 # Number of load instructions
system.cpu.num_store_insts 20555739 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 265378090 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 16890 # number of replacements
system.cpu.icache.tagsinuse 1736.497265 # Cycle average of tags in use
system.cpu.icache.total_refs 78126161 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 18908 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 4131.910355 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 1736.497265 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.847899 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.847899 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 78126161 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 78126161 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 78126161 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 78126161 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 78126161 # number of overall hits
system.cpu.icache.overall_hits::total 78126161 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 18908 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 18908 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 18908 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 18908 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 18908 # number of overall misses
system.cpu.icache.overall_misses::total 18908 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 413722000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 413722000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 413722000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 413722000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 413722000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 413722000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 78145069 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 78145069 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 78145069 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 78145069 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 78145069 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 78145069 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000242 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000242 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000242 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000242 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000242 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000242 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21880.791199 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 21880.791199 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 21880.791199 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 21880.791199 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 21880.791199 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 21880.791199 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 18908 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 18908 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 18908 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 18908 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 18908 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 18908 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 375906000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 375906000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 375906000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 375906000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 375906000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 375906000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000242 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000242 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000242 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19880.791199 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19880.791199 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19880.791199 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 19880.791199 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19880.791199 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 19880.791199 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 155902 # number of replacements
system.cpu.dcache.tagsinuse 4076.954355 # Cycle average of tags in use
system.cpu.dcache.total_refs 46862074 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 159998 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 292.891624 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 1072595000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4076.954355 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.995350 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.995350 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 27087367 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 27087367 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 19742869 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 19742869 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 46830236 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 46830236 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 46830236 # number of overall hits
system.cpu.dcache.overall_hits::total 46830236 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 52966 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 52966 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 107032 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 107032 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 159998 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 159998 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 159998 # number of overall misses
system.cpu.dcache.overall_misses::total 159998 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 1599899000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 1599899000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 5687190000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 5687190000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 7287089000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 7287089000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 7287089000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 7287089000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 27140333 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 27140333 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 46990234 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 46990234 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 46990234 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 46990234 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001952 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.001952 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005392 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.005392 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.003405 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.003405 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.003405 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.003405 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30206.151116 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 30206.151116 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53135.417445 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 53135.417445 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 45544.875561 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 45544.875561 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 45544.875561 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 45544.875561 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 128239 # number of writebacks
system.cpu.dcache.writebacks::total 128239 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 52966 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 52966 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107032 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 107032 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 159998 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 159998 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 159998 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 159998 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1493967000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 1493967000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5473126000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5473126000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6967093000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 6967093000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6967093000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 6967093000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001952 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001952 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003405 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.003405 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003405 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.003405 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28206.151116 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28206.151116 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51135.417445 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51135.417445 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43544.875561 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 43544.875561 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43544.875561 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 43544.875561 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 94693 # number of replacements
system.cpu.l2cache.tagsinuse 30368.194893 # Cycle average of tags in use
system.cpu.l2cache.total_refs 74295 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 125788 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.590637 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 27745.868937 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 1154.037281 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 1468.288674 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.846737 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.035218 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.044809 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.926764 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 14916 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 31426 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 46342 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 128239 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 128239 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 4752 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 4752 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 14916 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 36178 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 51094 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 14916 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 36178 # number of overall hits
system.cpu.l2cache.overall_hits::total 51094 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 3992 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 21540 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 25532 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 102280 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 102280 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 3992 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 123820 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 127812 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 3992 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 123820 # number of overall misses
system.cpu.l2cache.overall_misses::total 127812 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 207838000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1126741000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 1334579000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5318574000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 5318574000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 207838000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 6445315000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 6653153000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 207838000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 6445315000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 6653153000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 18908 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 52966 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 71874 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 128239 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 128239 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 107032 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 107032 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 18908 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 159998 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 178906 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 18908 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 159998 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 178906 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.211128 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.406676 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.355233 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955602 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.955602 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.211128 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.773885 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.714409 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.211128 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.773885 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.714409 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52063.627255 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52309.238626 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52270.836597 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.136879 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.136879 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52063.627255 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52053.908900 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52054.212437 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52063.627255 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52053.908900 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52054.212437 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 83909 # number of writebacks
system.cpu.l2cache.writebacks::total 83909 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3992 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21540 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 25532 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102280 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 102280 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3992 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 123820 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 127812 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3992 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 123820 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 127812 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 159934000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 868261000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1028195000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4091214000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4091214000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 159934000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4959475000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 5119409000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 159934000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4959475000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 5119409000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.211128 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.406676 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.355233 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955602 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955602 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.211128 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.773885 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.714409 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.211128 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.773885 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.714409 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40063.627255 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40309.238626 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40270.836597 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.136879 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.136879 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40063.627255 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40053.908900 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40054.212437 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40063.627255 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40053.908900 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40054.212437 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
|
