path: root/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  1.005768                       # Number of seconds simulated
sim_ticks                                1005767806500                       # Number of ticks simulated
final_tick                               1005767806500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 106626                       # Simulator instruction rate (inst/s)
host_op_rate                                   106626                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               58930745                       # Simulator tick rate (ticks/s)
host_mem_usage                                 266468                       # Number of bytes of host memory used
host_seconds                                 17066.95                       # Real time elapsed on the host
sim_insts                                  1819780127                       # Number of instructions simulated
sim_ops                                    1819780127                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst             54976                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data         125365120                       # Number of bytes read from this memory
system.physmem.bytes_read::total            125420096                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst        54976                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           54976                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     65155584                       # Number of bytes written to this memory
system.physmem.bytes_written::total          65155584                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst                859                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data            1958830                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               1959689                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1018056                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1018056                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst                54661                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data            124646185                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total               124700846                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst           54661                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total              54661                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks          64781934                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total               64781934                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks          64781934                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst               54661                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data           124646185                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              189482780                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                       1959689                       # Number of read requests accepted
system.physmem.writeReqs                      1018056                       # Number of write requests accepted
system.physmem.readBursts                     1959689                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                    1018056                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                125339392                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     80704                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  65154112                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                 125420096                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               65155584                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                     1261                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0              118688                       # Per bank write bursts
system.physmem.perBankRdBursts::1              114039                       # Per bank write bursts
system.physmem.perBankRdBursts::2              116164                       # Per bank write bursts
system.physmem.perBankRdBursts::3              117666                       # Per bank write bursts
system.physmem.perBankRdBursts::4              117733                       # Per bank write bursts
system.physmem.perBankRdBursts::5              117466                       # Per bank write bursts
system.physmem.perBankRdBursts::6              119809                       # Per bank write bursts
system.physmem.perBankRdBursts::7              124448                       # Per bank write bursts
system.physmem.perBankRdBursts::8              126913                       # Per bank write bursts
system.physmem.perBankRdBursts::9              130015                       # Per bank write bursts
system.physmem.perBankRdBursts::10             128579                       # Per bank write bursts
system.physmem.perBankRdBursts::11             130223                       # Per bank write bursts
system.physmem.perBankRdBursts::12             125906                       # Per bank write bursts
system.physmem.perBankRdBursts::13             125163                       # Per bank write bursts
system.physmem.perBankRdBursts::14             122509                       # Per bank write bursts
system.physmem.perBankRdBursts::15             123107                       # Per bank write bursts
system.physmem.perBankWrBursts::0               61223                       # Per bank write bursts
system.physmem.perBankWrBursts::1               61467                       # Per bank write bursts
system.physmem.perBankWrBursts::2               60558                       # Per bank write bursts
system.physmem.perBankWrBursts::3               61216                       # Per bank write bursts
system.physmem.perBankWrBursts::4               61647                       # Per bank write bursts
system.physmem.perBankWrBursts::5               63085                       # Per bank write bursts
system.physmem.perBankWrBursts::6               64137                       # Per bank write bursts
system.physmem.perBankWrBursts::7               65614                       # Per bank write bursts
system.physmem.perBankWrBursts::8               65332                       # Per bank write bursts
system.physmem.perBankWrBursts::9               65770                       # Per bank write bursts
system.physmem.perBankWrBursts::10              65297                       # Per bank write bursts
system.physmem.perBankWrBursts::11              65611                       # Per bank write bursts
system.physmem.perBankWrBursts::12              64139                       # Per bank write bursts
system.physmem.perBankWrBursts::13              64200                       # Per bank write bursts
system.physmem.perBankWrBursts::14              64551                       # Per bank write bursts
system.physmem.perBankWrBursts::15              64186                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    1005767733500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                 1959689                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                1018056                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                   1667897                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    193105                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     75870                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                     21555                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    29926                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    31516                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    51008                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    56043                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    59405                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    60493                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    60664                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    60587                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    60540                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    60592                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    60684                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    60779                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    62031                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    62029                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    60742                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    61437                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    59898                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                    59460                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      159                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                       42                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        6                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples      1810756                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      105.200206                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean      81.912098                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     131.997170                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127        1417049     78.26%     78.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255       275870     15.24%     93.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        50109      2.77%     96.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511        20785      1.15%     97.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639        12643      0.70%     98.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         6844      0.38%     98.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         5544      0.31%     98.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         3818      0.21%     99.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        18094      1.00%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total        1810756                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         59345                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        32.999023                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      160.520477                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023          59305     99.93%     99.93% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047           12      0.02%     99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-3071            9      0.02%     99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::3072-4095            9      0.02%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::4096-5119            3      0.01%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::5120-6143            1      0.00%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::6144-7167            1      0.00%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::8192-9215            1      0.00%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::9216-10239            1      0.00%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::12288-13311            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::16384-17407            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::19456-20479            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           59345                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         59345                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        17.154486                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       17.116028                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        1.157894                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16              27533     46.39%     46.39% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17               1478      2.49%     48.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18              25288     42.61%     91.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19               4106      6.92%     98.42% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20                708      1.19%     99.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21                151      0.25%     99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22                 51      0.09%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23                 15      0.03%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24                  6      0.01%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::25                  2      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26                  4      0.01%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28                  2      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::29                  1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           59345                       # Writes before turning the bus around for reads
system.physmem.totQLat                    39644301500                       # Total ticks spent queuing
system.physmem.totMemAccLat               76364826500                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   9792140000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       20242.92                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  38992.92                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                         124.62                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                          64.78                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                      124.70                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                       64.78                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           1.48                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.97                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.51                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.04                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        24.55                       # Average write queue length when enqueuing
system.physmem.readRowHits                     749188                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    416511                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   38.25                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  40.91                       # Row buffer hit rate for writes
system.physmem.avgGap                       337761.54                       # Average gap between requests
system.physmem.pageHitRate                      39.16                       # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE     297166155500                       # Time in different power states
system.physmem.memoryStateTime::REF       33584720000                       # Time in different power states
system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
system.physmem.memoryStateTime::ACT      675014883250                       # Time in different power states
system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
system.membus.throughput                    189482780                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq             1178393                       # Transaction distribution
system.membus.trans_dist::ReadResp            1178393                       # Transaction distribution
system.membus.trans_dist::Writeback           1018056                       # Transaction distribution
system.membus.trans_dist::ReadExReq            781296                       # Transaction distribution
system.membus.trans_dist::ReadExResp           781296                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      4937434                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                4937434                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    190575680                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total           190575680                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus              190575680                       # Total data (bytes)
system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy         11779296500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               1.2                       # Layer utilization (%)
system.membus.respLayer1.occupancy        18345408000                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              1.8                       # Layer utilization (%)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.branchPred.lookups               326515024                       # Number of BP lookups
system.cpu.branchPred.condPredicted         252570896                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect         138240520                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups            220728385                       # Number of BTB lookups
system.cpu.branchPred.BTBHits               135412850                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             61.348181                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                16767439                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect                  6                       # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits                           0                       # ITB hits
system.cpu.dtb.fetch_misses                         0                       # ITB misses
system.cpu.dtb.fetch_acv                            0                       # ITB acv
system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
system.cpu.dtb.read_hits                    444825863                       # DTB read hits
system.cpu.dtb.read_misses                    4897078                       # DTB read misses
system.cpu.dtb.read_acv                             0                       # DTB read access violations
system.cpu.dtb.read_accesses                449722941                       # DTB read accesses
system.cpu.dtb.write_hits                   160844247                       # DTB write hits
system.cpu.dtb.write_misses                   1701304                       # DTB write misses
system.cpu.dtb.write_acv                            0                       # DTB write access violations
system.cpu.dtb.write_accesses               162545551                       # DTB write accesses
system.cpu.dtb.data_hits                    605670110                       # DTB hits
system.cpu.dtb.data_misses                    6598382                       # DTB misses
system.cpu.dtb.data_acv                             0                       # DTB access violations
system.cpu.dtb.data_accesses                612268492                       # DTB accesses
system.cpu.itb.fetch_hits                   231919747                       # ITB hits
system.cpu.itb.fetch_misses                        22                       # ITB misses
system.cpu.itb.fetch_acv                            0                       # ITB acv
system.cpu.itb.fetch_accesses               231919769                       # ITB accesses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.read_acv                             0                       # DTB read access violations
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.write_acv                            0                       # DTB write access violations
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.data_hits                            0                       # DTB hits
system.cpu.itb.data_misses                          0                       # DTB misses
system.cpu.itb.data_acv                             0                       # DTB access violations
system.cpu.itb.data_accesses                        0                       # DTB accesses
system.cpu.workload.num_syscalls                   29                       # Number of system calls
system.cpu.numCycles                       2011535614                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.branch_predictor.predictedTaken    172226277                       # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken    154288747                       # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads   1667639381                       # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites   1376202617                       # Number of Writes to Int. Register File
system.cpu.regfile_manager.intRegFileAccesses   3043841998                       # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads          229                       # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites          345                       # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses          574                       # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards      651725578                       # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens                  617883712                       # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect    120527925                       # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect     11114137                       # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted      131642062                       # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted          83557916                       # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct     61.171968                       # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions       1139358188                       # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies                75                       # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides                    0                       # Number of Divide Operations Executed
system.cpu.contextSwitches                          1                       # Number of context switches
system.cpu.threadCycles                    1742007028                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled                         7502506                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                       439794636                       # Number of cycles cpu's stages were not processed
system.cpu.runCycles                       1571740978                       # Number of cycles cpu stages are processed.
system.cpu.activity                         78.136373                       # Percentage of cycles cpu is active
system.cpu.comLoads                         444595663                       # Number of Load instructions committed
system.cpu.comStores                        160728502                       # Number of Store instructions committed
system.cpu.comBranches                      214632552                       # Number of Branches instructions committed
system.cpu.comNops                           83736345                       # Number of Nop instructions committed
system.cpu.comNonSpec                              29                       # Number of Non-Speculative instructions committed
system.cpu.comInts                          916086844                       # Number of Integer instructions committed
system.cpu.comFloats                              190                       # Number of Floating Point instructions committed
system.cpu.committedInsts                  1819780127                       # Number of Instructions committed (Per-Thread)
system.cpu.committedOps                    1819780127                       # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total            1819780127                       # Number of Instructions committed (Total)
system.cpu.cpi                               1.105373                       # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi                                nan                       # CPI: Total SMT-CPI
system.cpu.cpi_total                         1.105373                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.904672                       # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc                                nan                       # IPC: Total SMT-IPC
system.cpu.ipc_total                         0.904672                       # IPC: Total IPC of All Threads
system.cpu.stage0.idleCycles                824896841                       # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles                1186638773                       # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization               58.991686                       # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles               1077691733                       # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles                 933843881                       # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization               46.424427                       # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles               1039140389                       # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles                 972395225                       # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization               48.340940                       # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles               1601912902                       # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles                 409622712                       # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization               20.363682                       # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles                990187341                       # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles                1021348273                       # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization               50.774556                       # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.tags.replacements                 1                       # number of replacements
system.cpu.icache.tags.tagsinuse           668.237280                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           231918592                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs               859                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs          269986.719441                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   668.237280                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.326288                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.326288                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          858                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           73                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4          785                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.418945                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         463840351                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        463840351                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst    231918592                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       231918592                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     231918592                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        231918592                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    231918592                       # number of overall hits
system.cpu.icache.overall_hits::total       231918592                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst         1154                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total          1154                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst         1154                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total           1154                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst         1154                       # number of overall misses
system.cpu.icache.overall_misses::total          1154                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst     83508500                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total     83508500                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst     83508500                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total     83508500                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst     83508500                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total     83508500                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    231919746                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    231919746                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    231919746                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    231919746                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    231919746                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    231919746                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000005                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000005                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000005                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000005                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000005                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000005                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72364.384749                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 72364.384749                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 72364.384749                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 72364.384749                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 72364.384749                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 72364.384749                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs          162                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets          418                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 1                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               1                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          162                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          418                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst          295                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total          295                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst          295                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total          295                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst          295                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total          295                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst          859                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total          859                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst          859                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total          859                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst          859                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total          859                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     61831500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total     61831500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst     61831500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total     61831500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst     61831500                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total     61831500                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000004                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000004                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000004                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000004                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000004                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000004                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71980.791618                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71980.791618                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71980.791618                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 71980.791618                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71980.791618                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 71980.791618                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.throughput               814858454                       # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq        7222692                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       7222692                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback      3693285                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq      1889623                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp      1889623                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1718                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     21916197                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total          21917915                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        54976                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    819503424                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total      819558400                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus         819558400                       # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy    10096085000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          1.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy       1445000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy   13977776250                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          1.4                       # Layer utilization (%)
system.cpu.l2cache.tags.replacements          1926959                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        30915.615811                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            8958694                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs          1956752                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             4.578349                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle      67887905750                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 14928.983043                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst    34.785512                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 15951.847256                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.455596                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.001062                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.486812                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.943470                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        29793                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0          158                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          592                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2          746                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3        12815                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        15482                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.909210                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses        106291175                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses       106291175                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.data      6044299                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        6044299                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks      3693285                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      3693285                       # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data      1108327                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total      1108327                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.data      7152626                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         7152626                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.data      7152626                       # number of overall hits
system.cpu.l2cache.overall_hits::total        7152626                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst          859                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data      1177534                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total      1178393                       # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       781296                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       781296                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst          859                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data      1958830                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total       1959689                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst          859                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data      1958830                       # number of overall misses
system.cpu.l2cache.overall_misses::total      1959689                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     60968500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data  94791357750                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total  94852326250                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  65779017750                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  65779017750                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst     60968500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 160570375500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 160631344000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst     60968500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 160570375500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 160631344000                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst          859                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data      7221833                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      7222692                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks      3693285                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      3693285                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data      1889623                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total      1889623                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst          859                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      9111456                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      9112315                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst          859                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      9111456                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      9112315                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst            1                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.163052                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.163151                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.413467                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.413467                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst            1                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.214985                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.215059                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst            1                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.214985                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.215059                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70976.135041                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80499.890237                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 80492.947811                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 84192.185484                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 84192.185484                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70976.135041                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81972.593589                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 81967.773458                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70976.135041                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81972.593589                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 81967.773458                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks      1018056                       # number of writebacks
system.cpu.l2cache.writebacks::total          1018056                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          859                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data      1177534                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total      1178393                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       781296                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       781296                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst          859                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data      1958830                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total      1959689                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst          859                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data      1958830                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total      1959689                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     50186500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  80032548250                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total  80082734750                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  56010972750                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  56010972750                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     50186500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 136043521000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 136093707500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     50186500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 136043521000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 136093707500                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.163052                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.163151                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.413467                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.413467                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.214985                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.215059                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.214985                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.215059                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58424.330617                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67966.231336                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67959.275683                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71689.824023                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71689.824023                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58424.330617                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69451.417938                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69446.584382                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58424.330617                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69451.417938                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69446.584382                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements           9107360                       # number of replacements
system.cpu.dcache.tags.tagsinuse          4082.305318                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           593299863                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           9111456                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             65.115813                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle       12706320250                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data  4082.305318                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.996657                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.996657                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0          574                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1         2872                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2          612                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3           38                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses        1219759786                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses       1219759786                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data    437268763                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       437268763                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data    156031100                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total      156031100                       # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data     593299863                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        593299863                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    593299863                       # number of overall hits
system.cpu.dcache.overall_hits::total       593299863                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      7326900                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       7326900                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      4697402                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      4697402                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data     12024302                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total       12024302                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data     12024302                       # number of overall misses
system.cpu.dcache.overall_misses::total      12024302                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 179720219500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 179720219500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 246249534250                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 246249534250                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 425969753750                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 425969753750                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 425969753750                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 425969753750                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    444595663                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    444595663                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data    160728502                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total    160728502                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    605324165                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    605324165                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    605324165                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    605324165                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.016480                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.016480                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.029226                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.029226                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.019864                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.019864                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.019864                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.019864                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24528.821125                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 24528.821125                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52422.495296                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 52422.495296                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 35425.736459                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 35425.736459                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 35425.736459                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 35425.736459                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs     10235273                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets      7848261                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs            412771                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets           73432                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    24.796492                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets   106.877941                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      3693285                       # number of writebacks
system.cpu.dcache.writebacks::total           3693285                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       104626                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       104626                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data      2808220                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total      2808220                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      2912846                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      2912846                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      2912846                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      2912846                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7222274                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      7222274                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1889182                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total      1889182                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      9111456                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      9111456                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      9111456                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      9111456                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 162584714500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 162584714500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  78915202250                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  78915202250                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 241499916750                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 241499916750                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 241499916750                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 241499916750                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.016245                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.016245                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.011754                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.011754                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.015052                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.015052                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.015052                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.015052                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22511.568309                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22511.568309                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41772.154430                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41772.154430                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26505.085109                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 26505.085109                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26505.085109                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 26505.085109                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------