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|
---------- Begin Simulation Statistics ----------
sim_seconds 0.987579 # Number of seconds simulated
sim_ticks 987579062500 # Number of ticks simulated
final_tick 987579062500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 79028 # Simulator instruction rate (inst/s)
host_op_rate 79028 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 42888030 # Simulator tick rate (ticks/s)
host_mem_usage 458304 # Number of bytes of host memory used
host_seconds 23026.92 # Real time elapsed on the host
sim_insts 1819780127 # Number of instructions simulated
sim_ops 1819780127 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 54976 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 125364928 # Number of bytes read from this memory
system.physmem.bytes_read::total 125419904 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 54976 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 54976 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 65155520 # Number of bytes written to this memory
system.physmem.bytes_written::total 65155520 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 859 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1958827 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1959686 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1018055 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1018055 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 55667 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 126941662 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 126997330 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 55667 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 55667 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 65974991 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 65974991 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 65974991 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 55667 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 126941662 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 192972321 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 1959686 # Total number of read requests seen
system.physmem.writeReqs 1018055 # Total number of write requests seen
system.physmem.cpureqs 2977741 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 125419904 # Total number of bytes read from memory
system.physmem.bytesWritten 65155520 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 125419904 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 65155520 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 577 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 122432 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 123238 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 122861 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 121276 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 122601 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 122224 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 124477 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 123481 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 121547 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 122168 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 122611 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 120103 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 120483 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 121941 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 124488 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 123178 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 63120 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 63437 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 63830 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 63407 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 63139 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 62716 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 63395 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 63432 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 62525 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 63278 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 63961 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 63327 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 63976 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 64713 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 65307 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 64492 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
system.physmem.totGap 987579010500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 1959686 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.writePktSize::1 0 # categorize write packet sizes
system.physmem.writePktSize::2 0 # categorize write packet sizes
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
system.physmem.writePktSize::6 1018055 # categorize write packet sizes
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
system.physmem.rdQLenPdf::0 1651837 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 192315 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 82006 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 32950 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 42531 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 44116 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 44251 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 44263 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 44264 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 44264 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 44263 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 44263 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 44263 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 44263 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 44263 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 44263 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 44263 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 44263 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 44263 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 44263 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 44263 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 44263 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 44263 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 44263 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 44263 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 44263 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 44263 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 1733 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 148 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 13 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.totQLat 19599583947 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 85189869947 # Sum of mem lat for all requests
system.physmem.totBusLat 7836436000 # Total cycles spent in databus access
system.physmem.totBankLat 57753850000 # Total cycles spent in bank access
system.physmem.avgQLat 10004.34 # Average queueing delay per request
system.physmem.avgBankLat 29479.65 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
system.physmem.avgMemAccLat 43483.99 # Average memory access latency
system.physmem.avgRdBW 127.00 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 65.97 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 127.00 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 65.97 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 1.21 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.09 # Average read queue length over time
system.physmem.avgWrQLen 10.28 # Average write queue length over time
system.physmem.readRowHits 834542 # Number of row buffer hits during reads
system.physmem.writeRowHits 194109 # Number of row buffer hits during writes
system.physmem.readRowHitRate 42.60 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 19.07 # Row buffer hit rate for writes
system.physmem.avgGap 331653.76 # Average gap between requests
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 444784364 # DTB read hits
system.cpu.dtb.read_misses 4897078 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 449681442 # DTB read accesses
system.cpu.dtb.write_hits 160833165 # DTB write hits
system.cpu.dtb.write_misses 1701304 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 162534469 # DTB write accesses
system.cpu.dtb.data_hits 605617529 # DTB hits
system.cpu.dtb.data_misses 6598382 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 612215911 # DTB accesses
system.cpu.itb.fetch_hits 232120860 # ITB hits
system.cpu.itb.fetch_misses 22 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 232120882 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 29 # Number of system calls
system.cpu.numCycles 1975158126 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.branch_predictor.lookups 328916009 # Number of BP lookups
system.cpu.branch_predictor.condPredicted 253846257 # Number of conditional branches predicted
system.cpu.branch_predictor.condIncorrect 140045817 # Number of conditional branches incorrect
system.cpu.branch_predictor.BTBLookups 232481413 # Number of BTB lookups
system.cpu.branch_predictor.BTBHits 138136467 # Number of BTB hits
system.cpu.branch_predictor.usedRAS 16767439 # Number of times the RAS was used to get a target.
system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions.
system.cpu.branch_predictor.BTBHitPct 59.418284 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 175138589 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 153777420 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 1669811898 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 1376202617 # Number of Writes to Int. Register File
system.cpu.regfile_manager.intRegFileAccesses 3046014515 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 237 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 345 # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses 582 # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards 650984890 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 617988746 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 121313944 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 12133415 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted 133447359 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted 81752917 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct 62.010775 # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions 1139622793 # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies 75 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches
system.cpu.threadCycles 1746581569 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled 7474420 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 398305853 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 1576852273 # Number of cycles cpu stages are processed.
system.cpu.activity 79.834230 # Percentage of cycles cpu is active
system.cpu.comLoads 444595663 # Number of Load instructions committed
system.cpu.comStores 160728502 # Number of Store instructions committed
system.cpu.comBranches 214632552 # Number of Branches instructions committed
system.cpu.comNops 83736345 # Number of Nop instructions committed
system.cpu.comNonSpec 29 # Number of Non-Speculative instructions committed
system.cpu.comInts 916086844 # Number of Integer instructions committed
system.cpu.comFloats 190 # Number of Floating Point instructions committed
system.cpu.committedInsts 1819780127 # Number of Instructions committed (Per-Thread)
system.cpu.committedOps 1819780127 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 1819780127 # Number of Instructions committed (Total)
system.cpu.cpi 1.085383 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
system.cpu.cpi_total 1.085383 # CPI: Total CPI of All Threads
system.cpu.ipc 0.921334 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
system.cpu.ipc_total 0.921334 # IPC: Total IPC of All Threads
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system.cpu.stage0.runCycles 1190773940 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 60.287525 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage1.runCycles 932337703 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 47.203193 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 1001198544 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 973959582 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 49.310461 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 1565492748 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 409665378 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 20.740890 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 952315389 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 1022842737 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 51.785360 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 1 # number of replacements
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system.cpu.icache.ReadReq_hits::total 232119756 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 232119756 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 232119756 # number of demand (read+write) hits
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system.cpu.icache.overall_hits::total 232119756 # number of overall hits
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system.cpu.icache.ReadReq_misses::total 1104 # number of ReadReq misses
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system.cpu.icache.demand_misses::total 1104 # number of demand (read+write) misses
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system.cpu.icache.overall_misses::total 1104 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 58767000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 58767000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 58767000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 58767000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 58767000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 58767000 # number of overall miss cycles
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system.cpu.icache.ReadReq_accesses::total 232120860 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.demand_accesses::total 232120860 # number of demand (read+write) accesses
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system.cpu.icache.overall_accesses::total 232120860 # number of overall (read+write) accesses
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system.cpu.icache.overall_miss_rate::total 0.000005 # miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_miss_latency::total 53230.978261 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 53230.978261 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 53230.978261 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 53230.978261 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 53230.978261 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 63 # number of cycles access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.icache.overall_mshr_hits::total 245 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 859 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 859 # number of ReadReq MSHR misses
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system.cpu.icache.demand_mshr_misses::total 859 # number of demand (read+write) MSHR misses
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system.cpu.icache.ReadReq_mshr_miss_latency::total 46993000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46993000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 46993000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46993000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 46993000 # number of overall MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses
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system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54706.635623 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54706.635623 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54706.635623 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 54706.635623 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54706.635623 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 54706.635623 # average overall mshr miss latency
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system.cpu.dcache.WriteReq_misses::total 4458190 # number of WriteReq misses
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system.cpu.dcache.ReadReq_miss_latency::total 160313092500 # number of ReadReq miss cycles
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system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.overall_accesses::total 605324165 # number of overall (read+write) accesses
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system.cpu.dcache.ReadReq_avg_miss_latency::total 21880.047149 # average ReadReq miss latency
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system.cpu.dcache.overall_mshr_miss_latency::total 211950829500 # number of overall MSHR miss cycles
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35964.187165 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35964.187165 # average WriteReq mshr miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23261.971967 # average overall mshr miss latency
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system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889639 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 1889639 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 859 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 9111473 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 9112332 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 859 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 9111473 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 9112332 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.163052 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.163151 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.413463 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.413463 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.214985 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.215059 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.214985 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.215059 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53701.979045 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 64721.293112 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 64713.260466 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70143.270284 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70143.270284 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53701.979045 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66883.898119 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 66878.120015 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53701.979045 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66883.898119 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 66878.120015 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 1018055 # number of writebacks
system.cpu.l2cache.writebacks::total 1018055 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 859 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1177531 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 1178390 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 781296 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 781296 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 859 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 1958827 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 1959686 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 1958827 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 1959686 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35264420 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 61190782598 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 61226047018 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 44920930070 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 44920930070 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35264420 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 106111712668 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 106146977088 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35264420 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 106111712668 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 106146977088 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163052 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163151 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413463 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413463 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214985 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.215059 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214985 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.215059 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41052.875437 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 51965.326261 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 51957.371514 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57495.405160 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57495.405160 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41052.875437 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 54171.048627 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54165.298465 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41052.875437 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 54171.048627 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54165.298465 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
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