blob: 0ddfc2b1c10ce2913190c4a7d616c6a4da3c0bf5 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
|
---------- Begin Simulation Statistics ----------
sim_seconds 1.009999 # Number of seconds simulated
sim_ticks 1009998808500 # Number of ticks simulated
final_tick 1009998808500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 98665 # Simulator instruction rate (inst/s)
host_op_rate 98665 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 54760444 # Simulator tick rate (ticks/s)
host_mem_usage 215204 # Number of bytes of host memory used
host_seconds 18443.95 # Real time elapsed on the host
sim_insts 1819780127 # Number of instructions simulated
sim_ops 1819780127 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 54976 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 172563072 # Number of bytes read from this memory
system.physmem.bytes_read::total 172618048 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 54976 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 54976 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 74938304 # Number of bytes written to this memory
system.physmem.bytes_written::total 74938304 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 859 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 2696298 # Number of read requests responded to by this memory
system.physmem.num_reads::total 2697157 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1170911 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1170911 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 54432 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 170854728 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 170909160 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 54432 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 54432 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 74196428 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 74196428 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 74196428 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 54432 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 170854728 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 245105588 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 444614444 # DTB read hits
system.cpu.dtb.read_misses 4897078 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 449511522 # DTB read accesses
system.cpu.dtb.write_hits 160920906 # DTB write hits
system.cpu.dtb.write_misses 1701304 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 162622210 # DTB write accesses
system.cpu.dtb.data_hits 605535350 # DTB hits
system.cpu.dtb.data_misses 6598382 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 612133732 # DTB accesses
system.cpu.itb.fetch_hits 231980230 # ITB hits
system.cpu.itb.fetch_misses 22 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 231980252 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 29 # Number of system calls
system.cpu.numCycles 2019997618 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.branch_predictor.lookups 328891112 # Number of BP lookups
system.cpu.branch_predictor.condPredicted 253883187 # Number of conditional branches predicted
system.cpu.branch_predictor.condIncorrect 140042357 # Number of conditional branches incorrect
system.cpu.branch_predictor.BTBLookups 232477361 # Number of BTB lookups
system.cpu.branch_predictor.BTBHits 138151285 # Number of BTB hits
system.cpu.branch_predictor.usedRAS 16767439 # Number of times the RAS was used to get a target.
system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions.
system.cpu.branch_predictor.BTBHitPct 59.425694 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 175108073 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 153783039 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 1669728742 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 1376202617 # Number of Writes to Int. Register File
system.cpu.regfile_manager.intRegFileAccesses 3045931359 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 235 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 345 # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses 580 # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards 651109695 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 617989652 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 121368305 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 12075594 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted 133443899 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted 81756170 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct 62.009227 # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions 1139611303 # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies 75 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches
system.cpu.threadCycles 1746428176 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled 7533729 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 443112454 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 1576885164 # Number of cycles cpu stages are processed.
system.cpu.activity 78.063714 # Percentage of cycles cpu is active
system.cpu.comLoads 444595663 # Number of Load instructions committed
system.cpu.comStores 160728502 # Number of Store instructions committed
system.cpu.comBranches 214632552 # Number of Branches instructions committed
system.cpu.comNops 83736345 # Number of Nop instructions committed
system.cpu.comNonSpec 29 # Number of Non-Speculative instructions committed
system.cpu.comInts 916086844 # Number of Integer instructions committed
system.cpu.comFloats 190 # Number of Floating Point instructions committed
system.cpu.committedInsts 1819780127 # Number of Instructions committed (Per-Thread)
system.cpu.committedOps 1819780127 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 1819780127 # Number of Instructions committed (Total)
system.cpu.cpi 1.110023 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
system.cpu.cpi_total 1.110023 # CPI: Total CPI of All Threads
system.cpu.ipc 0.900882 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
system.cpu.ipc_total 0.900882 # IPC: Total IPC of All Threads
system.cpu.stage0.idleCycles 829317091 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 1190680527 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 58.944650 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 1087591326 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 932406292 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 46.158782 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 1046003601 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 973994017 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 48.217582 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 1610294122 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 409703496 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 20.282375 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 997062989 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 1022934629 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 50.640388 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 1 # number of replacements
system.cpu.icache.tagsinuse 666.311000 # Cycle average of tags in use
system.cpu.icache.total_refs 231979155 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 859 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 270057.223516 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 666.311000 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.325347 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.325347 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 231979155 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 231979155 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 231979155 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 231979155 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 231979155 # number of overall hits
system.cpu.icache.overall_hits::total 231979155 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1072 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1072 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1072 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1072 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1072 # number of overall misses
system.cpu.icache.overall_misses::total 1072 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 58539000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 58539000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 58539000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 58539000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 58539000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 58539000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 231980227 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 231980227 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 231980227 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 231980227 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 231980227 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 231980227 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000005 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000005 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000005 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000005 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000005 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000005 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54607.276119 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 54607.276119 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54607.276119 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 54607.276119 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54607.276119 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 54607.276119 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 125500 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 31375 # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 213 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 213 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 213 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 213 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 213 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 213 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 859 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 859 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 859 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 859 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 859 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 45929000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 45929000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 45929000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 45929000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 45929000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 45929000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53467.986030 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53467.986030 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53467.986030 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 53467.986030 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53467.986030 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 53467.986030 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 9107352 # number of replacements
system.cpu.dcache.tagsinuse 4082.536815 # Cycle average of tags in use
system.cpu.dcache.total_refs 595069970 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 9111448 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 65.310143 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 12672189000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4082.536815 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.996713 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.996713 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 437271423 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 437271423 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 157798547 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 157798547 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 595069970 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 595069970 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 595069970 # number of overall hits
system.cpu.dcache.overall_hits::total 595069970 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 7324240 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 7324240 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 2929955 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 2929955 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 10254195 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 10254195 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 10254195 # number of overall misses
system.cpu.dcache.overall_misses::total 10254195 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 180897499500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 180897499500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 110294932000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 110294932000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 291192431500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 291192431500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 291192431500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 291192431500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 605324165 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 605324165 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 605324165 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 605324165 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016474 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.016474 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.018229 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.018229 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.016940 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.016940 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.016940 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.016940 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24698.466940 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 24698.466940 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37643.899650 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 37643.899650 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 28397.395554 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 28397.395554 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 28397.395554 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 28397.395554 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 11000000 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 8092150500 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 2762 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 209020 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 3982.621289 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 38714.718687 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 3058572 # number of writebacks
system.cpu.dcache.writebacks::total 3058572 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 101958 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 101958 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1040789 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 1040789 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 1142747 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 1142747 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 1142747 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 1142747 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222282 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 7222282 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889166 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 1889166 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 9111448 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 9111448 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 9111448 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 9111448 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 156091594000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 156091594000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 59191446500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 59191446500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 215283040500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 215283040500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 215283040500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 215283040500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011754 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011754 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.015052 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.015052 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21612.503361 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21612.503361 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31332.051551 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31332.051551 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23627.752746 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 23627.752746 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23627.752746 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 23627.752746 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 2686301 # number of replacements
system.cpu.l2cache.tagsinuse 26348.804807 # Cycle average of tags in use
system.cpu.l2cache.total_refs 7564571 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 2710944 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 2.790383 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 224336260000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 10843.214494 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 26.756246 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 15478.834067 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.330909 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.000817 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.472377 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.804102 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.data 5414817 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 5414817 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 3058572 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 3058572 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 1000333 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 1000333 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.data 6415150 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 6415150 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.data 6415150 # number of overall hits
system.cpu.l2cache.overall_hits::total 6415150 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 859 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 1807023 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 1807882 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 889275 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 889275 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 859 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 2696298 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 2697157 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 859 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 2696298 # number of overall misses
system.cpu.l2cache.overall_misses::total 2697157 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 44955000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 94411778000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 94456733000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 46506892000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 46506892000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 44955000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 140918670000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 140963625000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 44955000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 140918670000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 140963625000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 859 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 7221840 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 7222699 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 3058572 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 3058572 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889608 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 1889608 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 859 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 9111448 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 9112307 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 859 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 9111448 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 9112307 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250216 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.250306 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.470613 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.470613 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.295924 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.295991 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.295924 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.295991 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52334.109430 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52247.136865 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52247.178190 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52297.536757 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52297.536757 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52334.109430 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52263.759421 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52263.781827 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52334.109430 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52263.759421 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52263.781827 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 580500 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 70 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8292.857143 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 1170911 # number of writebacks
system.cpu.l2cache.writebacks::total 1170911 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 859 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1807023 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 1807882 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 889275 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 889275 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 859 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 2696298 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 2697157 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 2696298 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 2697157 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 34480500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 72319844500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 72354325000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 35671150000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 35671150000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34480500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 107990994500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 108025475000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34480500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 107990994500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 108025475000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250216 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.250306 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.470613 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.470613 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.295924 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.295991 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.295924 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.295991 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40140.279395 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40021.540678 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40021.597095 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40112.619831 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40112.619831 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40140.279395 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40051.579796 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40051.608045 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40140.279395 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40051.579796 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40051.608045 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
|
