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|
---------- Begin Simulation Statistics ----------
sim_seconds 0.993559 # Number of seconds simulated
sim_ticks 993559170500 # Number of ticks simulated
final_tick 993559170500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 90803 # Simulator instruction rate (inst/s)
host_op_rate 90803 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 49576515 # Simulator tick rate (ticks/s)
host_mem_usage 449304 # Number of bytes of host memory used
host_seconds 20040.92 # Real time elapsed on the host
sim_insts 1819780127 # Number of instructions simulated
sim_ops 1819780127 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 54976 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 125365056 # Number of bytes read from this memory
system.physmem.bytes_read::total 125420032 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 54976 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 54976 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 65155712 # Number of bytes written to this memory
system.physmem.bytes_written::total 65155712 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 859 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1958829 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1959688 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1018058 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1018058 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 55332 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 126177745 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 126233078 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 55332 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 55332 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 65578089 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 65578089 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 65578089 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 55332 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 126177745 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 191811167 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 1959688 # Total number of read requests seen
system.physmem.writeReqs 1018058 # Total number of write requests seen
system.physmem.cpureqs 2977748 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 125420032 # Total number of bytes read from memory
system.physmem.bytesWritten 65155712 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 125420032 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 65155712 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 582 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 122179 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 121801 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 121647 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 123761 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 123294 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 122180 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 120330 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 121052 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 121195 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 121884 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 121113 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 123048 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 125175 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 123789 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 122721 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 123937 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 63389 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 62256 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 62952 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 63764 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 64028 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 63763 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 63369 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 63367 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 63391 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 63723 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 63292 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 64137 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 64555 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 64147 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 63647 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 64278 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 2 # Number of times wr buffer was full causing retry
system.physmem.totGap 993559118500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 1959688 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 1018058 # Categorize write packet sizes
system.physmem.rdQLenPdf::0 1630116 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 205318 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 87737 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 35934 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 41624 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 43773 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 44240 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 44256 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 44259 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 44259 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 44260 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 44262 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 44262 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 44263 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 44263 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 44263 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 44263 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 44263 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 44263 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 44263 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 44263 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 44263 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 44263 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 44263 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 44263 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 44263 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 44263 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 2640 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 491 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 24 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 8 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 5 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 5 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 4 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 2 # What write queue length does an incoming req see
system.physmem.totQLat 35843451500 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 104284202750 # Sum of mem lat for all requests
system.physmem.totBusLat 9795530000 # Total cycles spent in databus access
system.physmem.totBankLat 58645221250 # Total cycles spent in bank access
system.physmem.avgQLat 18295.82 # Average queueing delay per request
system.physmem.avgBankLat 29934.69 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
system.physmem.avgMemAccLat 53230.51 # Average memory access latency
system.physmem.avgRdBW 126.23 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 65.58 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 126.23 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 65.58 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 1.50 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.10 # Average read queue length over time
system.physmem.avgWrQLen 10.46 # Average write queue length over time
system.physmem.readRowHits 770937 # Number of row buffer hits during reads
system.physmem.writeRowHits 285715 # Number of row buffer hits during writes
system.physmem.readRowHitRate 39.35 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 28.06 # Row buffer hit rate for writes
system.physmem.avgGap 333661.47 # Average gap between requests
system.cpu.branchPred.lookups 326540496 # Number of BP lookups
system.cpu.branchPred.condPredicted 252608543 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 138248451 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 220022753 # Number of BTB lookups
system.cpu.branchPred.BTBHits 135563778 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 61.613527 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 16767439 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 6 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 444796009 # DTB read hits
system.cpu.dtb.read_misses 4897078 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 449693087 # DTB read accesses
system.cpu.dtb.write_hits 160833358 # DTB write hits
system.cpu.dtb.write_misses 1701304 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 162534662 # DTB write accesses
system.cpu.dtb.data_hits 605629367 # DTB hits
system.cpu.dtb.data_misses 6598382 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 612227749 # DTB accesses
system.cpu.itb.fetch_hits 232025963 # ITB hits
system.cpu.itb.fetch_misses 22 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 232025985 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 29 # Number of system calls
system.cpu.numCycles 1987118342 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.branch_predictor.predictedTaken 172378847 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 154161649 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 1667662468 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 1376202617 # Number of Writes to Int. Register File
system.cpu.regfile_manager.intRegFileAccesses 3043865085 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 230 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 345 # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses 575 # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards 651727790 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 617884569 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 120519408 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 11130585 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted 131649993 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted 83550128 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct 61.175613 # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions 1139371391 # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies 75 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches
system.cpu.threadCycles 1741838474 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled 7484621 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 415293731 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 1571824611 # Number of cycles cpu stages are processed.
system.cpu.activity 79.100705 # Percentage of cycles cpu is active
system.cpu.comLoads 444595663 # Number of Load instructions committed
system.cpu.comStores 160728502 # Number of Store instructions committed
system.cpu.comBranches 214632552 # Number of Branches instructions committed
system.cpu.comNops 83736345 # Number of Nop instructions committed
system.cpu.comNonSpec 29 # Number of Non-Speculative instructions committed
system.cpu.comInts 916086844 # Number of Integer instructions committed
system.cpu.comFloats 190 # Number of Floating Point instructions committed
system.cpu.committedInsts 1819780127 # Number of Instructions committed (Per-Thread)
system.cpu.committedOps 1819780127 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 1819780127 # Number of Instructions committed (Total)
system.cpu.cpi 1.091955 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
system.cpu.cpi_total 1.091955 # CPI: Total CPI of All Threads
system.cpu.ipc 0.915789 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
system.cpu.ipc_total 0.915789 # IPC: Total IPC of All Threads
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system.cpu.stage0.runCycles 1186856695 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 59.727530 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage1.runCycles 933699142 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 46.987596 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 1014725184 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 972393158 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 48.934839 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 1577495448 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 409622894 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 20.613915 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 965781598 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 1021336744 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 51.397882 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.icache.sampled_refs 859 # Sample count of references to valid blocks.
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system.cpu.icache.ReadReq_misses::total 1109 # number of ReadReq misses
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system.cpu.icache.demand_misses::total 1109 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1109 # number of overall misses
system.cpu.icache.overall_misses::total 1109 # number of overall misses
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system.cpu.icache.ReadReq_miss_latency::total 64819000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 64819000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 64819000 # number of demand (read+write) miss cycles
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system.cpu.icache.overall_miss_latency::total 64819000 # number of overall miss cycles
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system.cpu.icache.overall_accesses::total 232025963 # number of overall (read+write) accesses
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system.cpu.icache.ReadReq_avg_miss_latency::total 58448.151488 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 58448.151488 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 58448.151488 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 58448.151488 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 58448.151488 # average overall miss latency
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system.cpu.icache.overall_mshr_hits::total 250 # number of overall MSHR hits
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system.cpu.icache.ReadReq_mshr_miss_latency::total 51089000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 51089000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 51089000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 51089000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 51089000 # number of overall MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses
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system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 59474.970896 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 59474.970896 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59474.970896 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 59474.970896 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59474.970896 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 59474.970896 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.Writeback_hits::total 3693293 # number of Writeback hits
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system.cpu.l2cache.Writeback_accesses::writebacks 3693293 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 3693293 # number of Writeback accesses(hits+misses)
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system.cpu.l2cache.overall_mshr_misses::cpu.data 1958829 # number of overall MSHR misses
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system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 124968834490 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 125008399964 # number of overall MSHR miss cycles
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system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214985 # mshr miss rate for demand accesses
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system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 46059.923166 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63797.725320 # average overall mshr miss latency
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system.cpu.dcache.WriteReq_misses::total 4484420 # number of WriteReq misses
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system.cpu.dcache.demand_miss_latency::cpu.data 369799222500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 369799222500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 369799222500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 369799222500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 605324165 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 605324165 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 605324165 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 605324165 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016480 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.016480 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027901 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.027901 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.019512 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.019512 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.019512 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.019512 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22832.014404 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 22832.014404 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45158.843730 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 45158.843730 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 31308.868607 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 31308.868607 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 31308.868607 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 31308.868607 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 13465422 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 4771270 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 372557 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 65753 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 36.143253 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 72.563533 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 3693293 # number of writebacks
system.cpu.dcache.writebacks::total 3693293 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 104622 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 104622 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2595235 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 2595235 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 2699857 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 2699857 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 2699857 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 2699857 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222283 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 7222283 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889185 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 1889185 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 9111468 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 9111468 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 9111468 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 9111468 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 150964297500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 150964297500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 79314869000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 79314869000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 230279166500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 230279166500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 230279166500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 230279166500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011754 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011754 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.015052 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.015052 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20902.572981 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20902.572981 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41983.643211 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41983.643211 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25273.552681 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 25273.552681 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25273.552681 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 25273.552681 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
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