path: root/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  1.208778                       # Number of seconds simulated
sim_ticks                                1208777694500                       # Number of ticks simulated
final_tick                               1208777694500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 390102                       # Simulator instruction rate (inst/s)
host_op_rate                                   390102                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                              258186532                       # Simulator tick rate (ticks/s)
host_mem_usage                                 253640                       # Number of bytes of host memory used
host_seconds                                  4681.80                       # Real time elapsed on the host
sim_insts                                  1826378509                       # Number of instructions simulated
sim_ops                                    1826378509                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst             61312                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data         124970112                       # Number of bytes read from this memory
system.physmem.bytes_read::total            125031424                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst        61312                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           61312                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     65416896                       # Number of bytes written to this memory
system.physmem.bytes_written::total          65416896                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst                958                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data            1952658                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               1953616                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1022139                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1022139                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst                50722                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data            103385521                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total               103436244                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst           50722                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total              50722                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks          54118219                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total               54118219                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks          54118219                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst               50722                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data           103385521                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              157554463                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                       1953616                       # Number of read requests accepted
system.physmem.writeReqs                      1022139                       # Number of write requests accepted
system.physmem.readBursts                     1953616                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                    1022139                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                124948416                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     83008                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  65415616                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                 125031424                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               65416896                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                     1297                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0              118316                       # Per bank write bursts
system.physmem.perBankRdBursts::1              113525                       # Per bank write bursts
system.physmem.perBankRdBursts::2              115740                       # Per bank write bursts
system.physmem.perBankRdBursts::3              117258                       # Per bank write bursts
system.physmem.perBankRdBursts::4              117310                       # Per bank write bursts
system.physmem.perBankRdBursts::5              117126                       # Per bank write bursts
system.physmem.perBankRdBursts::6              119402                       # Per bank write bursts
system.physmem.perBankRdBursts::7              124113                       # Per bank write bursts
system.physmem.perBankRdBursts::8              126650                       # Per bank write bursts
system.physmem.perBankRdBursts::9              129582                       # Per bank write bursts
system.physmem.perBankRdBursts::10             128169                       # Per bank write bursts
system.physmem.perBankRdBursts::11             129917                       # Per bank write bursts
system.physmem.perBankRdBursts::12             125580                       # Per bank write bursts
system.physmem.perBankRdBursts::13             124837                       # Per bank write bursts
system.physmem.perBankRdBursts::14             122150                       # Per bank write bursts
system.physmem.perBankRdBursts::15             122644                       # Per bank write bursts
system.physmem.perBankWrBursts::0               61421                       # Per bank write bursts
system.physmem.perBankWrBursts::1               61661                       # Per bank write bursts
system.physmem.perBankWrBursts::2               60724                       # Per bank write bursts
system.physmem.perBankWrBursts::3               61398                       # Per bank write bursts
system.physmem.perBankWrBursts::4               61819                       # Per bank write bursts
system.physmem.perBankWrBursts::5               63309                       # Per bank write bursts
system.physmem.perBankWrBursts::6               64356                       # Per bank write bursts
system.physmem.perBankWrBursts::7               65855                       # Per bank write bursts
system.physmem.perBankWrBursts::8               65577                       # Per bank write bursts
system.physmem.perBankWrBursts::9               66031                       # Per bank write bursts
system.physmem.perBankWrBursts::10              65643                       # Per bank write bursts
system.physmem.perBankWrBursts::11              65945                       # Per bank write bursts
system.physmem.perBankWrBursts::12              64508                       # Per bank write bursts
system.physmem.perBankWrBursts::13              64526                       # Per bank write bursts
system.physmem.perBankWrBursts::14              64900                       # Per bank write bursts
system.physmem.perBankWrBursts::15              64446                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    1208777578000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                 1953616                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                1022139                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                   1830097                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    122205                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                        17                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    30602                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    32045                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    55307                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    59695                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    60116                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    60223                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    60190                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    60196                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    60182                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    60140                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    60199                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    60169                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    60684                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    61042                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    60657                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    61101                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    59828                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                    59617                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                       96                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                       18                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        7                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        3                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples      1831457                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      103.940817                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean      81.136003                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     130.529919                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127        1452947     79.33%     79.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255       261995     14.31%     93.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        48664      2.66%     96.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511        20593      1.12%     97.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639        13175      0.72%     98.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         7238      0.40%     98.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         5438      0.30%     98.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         4580      0.25%     99.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        16827      0.92%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total        1831457                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         59614                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        32.747643                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      146.947369                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-511           59453     99.73%     99.73% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::512-1023          115      0.19%     99.92% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-1535            9      0.02%     99.94% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1536-2047            9      0.02%     99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-2559            8      0.01%     99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2560-3071            3      0.01%     99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::3072-3583            3      0.01%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::3584-4095            3      0.01%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::4096-4607            2      0.00%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::4608-5119            2      0.00%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::6656-7167            1      0.00%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::8704-9215            1      0.00%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::9216-9727            1      0.00%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::10752-11263            1      0.00%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::11776-12287            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::12288-12799            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::14848-15359            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           59614                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         59614                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        17.145620                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       17.109391                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        1.119268                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16              27453     46.05%     46.05% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17               1268      2.13%     48.18% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18              26337     44.18%     92.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19               4007      6.72%     99.08% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20                455      0.76%     99.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21                 71      0.12%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22                 15      0.03%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23                  6      0.01%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24                  1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::33                  1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           59614                       # Writes before turning the bus around for reads
system.physmem.totQLat                    36537628750                       # Total ticks spent queuing
system.physmem.totMemAccLat               73143610000                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   9761595000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       18714.99                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  37464.99                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                         103.37                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                          54.12                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                      103.44                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                       54.12                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           1.23                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.81                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.42                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        24.80                       # Average write queue length when enqueuing
system.physmem.readRowHits                     723773                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    419204                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   37.07                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  41.01                       # Row buffer hit rate for writes
system.physmem.avgGap                       406208.70                       # Average gap between requests
system.physmem.pageHitRate                      38.43                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                 6714376200                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                 3663598125                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                7353738600                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy               3243518640                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy            78951397200                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy           415074736440                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           361165338750                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             876166703955                       # Total energy per rank (pJ)
system.physmem_0.averagePower              724.837554                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   598070170000                       # Time in different power states
system.physmem_0.memoryStateTime::REF     40363700000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT    570342873000                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                 7131423600                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                 3891153750                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                7874224800                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy               3379812480                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy            78951397200                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy           426560774805                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           351089866500                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             878878653135                       # Total energy per rank (pJ)
system.physmem_1.averagePower              727.081103                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   581228871000                       # Time in different power states
system.physmem_1.memoryStateTime::REF     40363700000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT    587184084000                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu.branchPred.lookups               246097965                       # Number of BP lookups
system.cpu.branchPred.condPredicted         186356162                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect          15588061                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups            167640085                       # Number of BTB lookups
system.cpu.branchPred.BTBHits               165196337                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             98.542265                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                18413332                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect             104391                       # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups             297                       # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits                 67                       # Number of indirect target hits.
system.cpu.branchPred.indirectMisses              230                       # Number of indirect misses.
system.cpu.branchPredindirectMispredicted           98                       # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dtb.fetch_hits                           0                       # ITB hits
system.cpu.dtb.fetch_misses                         0                       # ITB misses
system.cpu.dtb.fetch_acv                            0                       # ITB acv
system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
system.cpu.dtb.read_hits                    452860657                       # DTB read hits
system.cpu.dtb.read_misses                    4979867                       # DTB read misses
system.cpu.dtb.read_acv                             0                       # DTB read access violations
system.cpu.dtb.read_accesses                457840524                       # DTB read accesses
system.cpu.dtb.write_hits                   161378231                       # DTB write hits
system.cpu.dtb.write_misses                   1709431                       # DTB write misses
system.cpu.dtb.write_acv                            0                       # DTB write access violations
system.cpu.dtb.write_accesses               163087662                       # DTB write accesses
system.cpu.dtb.data_hits                    614238888                       # DTB hits
system.cpu.dtb.data_misses                    6689298                       # DTB misses
system.cpu.dtb.data_acv                             0                       # DTB access violations
system.cpu.dtb.data_accesses                620928186                       # DTB accesses
system.cpu.itb.fetch_hits                   597989612                       # ITB hits
system.cpu.itb.fetch_misses                        19                       # ITB misses
system.cpu.itb.fetch_acv                            0                       # ITB acv
system.cpu.itb.fetch_accesses               597989631                       # ITB accesses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.read_acv                             0                       # DTB read access violations
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.write_acv                            0                       # DTB write access violations
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.data_hits                            0                       # DTB hits
system.cpu.itb.data_misses                          0                       # DTB misses
system.cpu.itb.data_acv                             0                       # DTB access violations
system.cpu.itb.data_accesses                        0                       # DTB accesses
system.cpu.workload.num_syscalls                   29                       # Number of system calls
system.cpu.numCycles                       2417555389                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                  1826378509                       # Number of instructions committed
system.cpu.committedOps                    1826378509                       # Number of ops (including micro ops) committed
system.cpu.discardedOps                      51811935                       # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
system.cpu.cpi                               1.323688                       # CPI: cycles per instruction
system.cpu.ipc                               0.755465                       # IPC: instructions per cycle
system.cpu.op_class_0::No_OpClass            83736345      4.58%      4.58% # Class of committed instruction
system.cpu.op_class_0::IntAlu              1129914150     61.87%     66.45% # Class of committed instruction
system.cpu.op_class_0::IntMult                     75      0.00%     66.45% # Class of committed instruction
system.cpu.op_class_0::IntDiv                       0      0.00%     66.45% # Class of committed instruction
system.cpu.op_class_0::FloatAdd                805244      0.04%     66.50% # Class of committed instruction
system.cpu.op_class_0::FloatCmp                    13      0.00%     66.50% # Class of committed instruction
system.cpu.op_class_0::FloatCvt                   100      0.00%     66.50% # Class of committed instruction
system.cpu.op_class_0::FloatMult                   11      0.00%     66.50% # Class of committed instruction
system.cpu.op_class_0::FloatDiv                    24      0.00%     66.50% # Class of committed instruction
system.cpu.op_class_0::FloatSqrt                    0      0.00%     66.50% # Class of committed instruction
system.cpu.op_class_0::SimdAdd                      0      0.00%     66.50% # Class of committed instruction
system.cpu.op_class_0::SimdAddAcc                   0      0.00%     66.50% # Class of committed instruction
system.cpu.op_class_0::SimdAlu                      0      0.00%     66.50% # Class of committed instruction
system.cpu.op_class_0::SimdCmp                      0      0.00%     66.50% # Class of committed instruction
system.cpu.op_class_0::SimdCvt                      0      0.00%     66.50% # Class of committed instruction
system.cpu.op_class_0::SimdMisc                     0      0.00%     66.50% # Class of committed instruction
system.cpu.op_class_0::SimdMult                     0      0.00%     66.50% # Class of committed instruction
system.cpu.op_class_0::SimdMultAcc                  0      0.00%     66.50% # Class of committed instruction
system.cpu.op_class_0::SimdShift                    0      0.00%     66.50% # Class of committed instruction
system.cpu.op_class_0::SimdShiftAcc                 0      0.00%     66.50% # Class of committed instruction
system.cpu.op_class_0::SimdSqrt                     0      0.00%     66.50% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAdd                 0      0.00%     66.50% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAlu                 0      0.00%     66.50% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCmp                 0      0.00%     66.50% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCvt                 0      0.00%     66.50% # Class of committed instruction
system.cpu.op_class_0::SimdFloatDiv                 0      0.00%     66.50% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMisc                0      0.00%     66.50% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMult                0      0.00%     66.50% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMultAcc             0      0.00%     66.50% # Class of committed instruction
system.cpu.op_class_0::SimdFloatSqrt                0      0.00%     66.50% # Class of committed instruction
system.cpu.op_class_0::MemRead              449492741     24.61%     91.11% # Class of committed instruction
system.cpu.op_class_0::MemWrite             162429806      8.89%    100.00% # Class of committed instruction
system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
system.cpu.op_class_0::total               1826378509                       # Class of committed instruction
system.cpu.tickCycles                      2075251932                       # Number of cycles that the object actually ticked
system.cpu.idleCycles                       342303457                       # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements           9121974                       # number of replacements
system.cpu.dcache.tags.tagsinuse          4080.726355                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           601538856                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           9126070                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             65.914337                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle       16821281500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data  4080.726355                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.996271                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.996271                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           56                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1         1562                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2         2407                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3           71                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses        1231275880                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses       1231275880                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data    443056865                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       443056865                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data    158481991                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total      158481991                       # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data     601538856                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        601538856                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    601538856                       # number of overall hits
system.cpu.dcache.overall_hits::total       601538856                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      7289538                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       7289538                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      2246511                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      2246511                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data      9536049                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        9536049                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      9536049                       # number of overall misses
system.cpu.dcache.overall_misses::total       9536049                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 185480529000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 185480529000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 108417025500                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 108417025500                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 293897554500                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 293897554500                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 293897554500                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 293897554500                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    450346403                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    450346403                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data    160728502                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total    160728502                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    611074905                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    611074905                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    611074905                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    611074905                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.016187                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.016187                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.013977                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.013977                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.015605                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.015605                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.015605                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.015605                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25444.757816                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 25444.757816                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48260.180119                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 48260.180119                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 30819.635522                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 30819.635522                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 30819.635522                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 30819.635522                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks      3686603                       # number of writebacks
system.cpu.dcache.writebacks::total           3686603                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data        50808                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total        50808                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data       359171                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total       359171                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data       409979                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total       409979                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data       409979                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total       409979                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7238730                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      7238730                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1887340                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total      1887340                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      9126070                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      9126070                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      9126070                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      9126070                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 177011068000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 177011068000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  83258719000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  83258719000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 260269787000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 260269787000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 260269787000                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 260269787000                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.016074                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.016074                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.011742                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.011742                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.014934                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.014934                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.014934                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.014934                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24453.332007                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24453.332007                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44114.319095                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44114.319095                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28519.372194                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 28519.372194                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28519.372194                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 28519.372194                       # average overall mshr miss latency
system.cpu.icache.tags.replacements                 3                       # number of replacements
system.cpu.icache.tags.tagsinuse           750.173547                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           597988654                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs               958                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs          624205.275574                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   750.173547                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.366296                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.366296                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          955                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           81                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4          874                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.466309                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses        1195980182                       # Number of tag accesses
system.cpu.icache.tags.data_accesses       1195980182                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst    597988654                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       597988654                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     597988654                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        597988654                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    597988654                       # number of overall hits
system.cpu.icache.overall_hits::total       597988654                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst          958                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total           958                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst          958                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total            958                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst          958                       # number of overall misses
system.cpu.icache.overall_misses::total           958                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst     76338000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total     76338000                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst     76338000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total     76338000                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst     76338000                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total     76338000                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    597989612                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    597989612                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    597989612                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    597989612                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    597989612                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    597989612                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000002                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000002                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000002                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000002                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000002                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000002                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 79684.759916                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 79684.759916                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 79684.759916                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 79684.759916                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 79684.759916                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 79684.759916                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks            3                       # number of writebacks
system.cpu.icache.writebacks::total                 3                       # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst          958                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total          958                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst          958                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total          958                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst          958                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total          958                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     75380000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total     75380000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst     75380000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total     75380000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst     75380000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total     75380000                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000002                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000002                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000002                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78684.759916                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78684.759916                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78684.759916                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 78684.759916                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78684.759916                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 78684.759916                       # average overall mshr miss latency
system.cpu.l2cache.tags.replacements          1920891                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        30765.315888                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs           14409692                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs          1950696                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             7.386949                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle      89219766000                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 14798.392410                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst    42.817395                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 15924.106083                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.451611                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.001307                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.485965                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.938883                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        29805                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0          155                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1           36                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1217                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3        12865                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        15532                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.909576                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses        149830076                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses       149830076                       # Number of data accesses
system.cpu.l2cache.WritebackDirty_hits::writebacks      3686603                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total      3686603                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks            3                       # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total            3                       # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data      1106830                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total      1106830                       # number of ReadExReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data      6066582                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total      6066582                       # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.data      7173412                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         7173412                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.data      7173412                       # number of overall hits
system.cpu.l2cache.overall_hits::total        7173412                       # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data       780510                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       780510                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          958                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total          958                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data      1172148                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total      1172148                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst          958                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data      1952658                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total       1953616                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst          958                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data      1952658                       # number of overall misses
system.cpu.l2cache.overall_misses::total      1953616                       # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  68734828000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  68734828000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     73941000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total     73941000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 102426227000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 102426227000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst     73941000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 171161055000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 171234996000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst     73941000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 171161055000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 171234996000                       # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks      3686603                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total      3686603                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks            3                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total            3                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data      1887340                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total      1887340                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          958                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total          958                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      7238730                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total      7238730                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst          958                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      9126070                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      9127028                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst          958                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      9126070                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      9127028                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.413550                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.413550                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst            1                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total            1                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.161927                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.161927                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst            1                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.213965                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.214047                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst            1                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.213965                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.214047                       # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88063.994055                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88063.994055                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77182.672234                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77182.672234                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 87383.356880                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 87383.356880                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77182.672234                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87655.418921                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 87650.283372                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77182.672234                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87655.418921                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 87650.283372                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.writebacks::writebacks      1022139                       # number of writebacks
system.cpu.l2cache.writebacks::total          1022139                       # number of writebacks
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          242                       # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total          242                       # number of CleanEvict MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       780510                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       780510                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          958                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total          958                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data      1172148                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total      1172148                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst          958                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data      1952658                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total      1953616                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst          958                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data      1952658                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total      1953616                       # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  60929728000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  60929728000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     64361000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     64361000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  90704747000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  90704747000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     64361000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 151634475000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 151698836000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     64361000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 151634475000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 151698836000                       # number of overall MSHR miss cycles
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.413550                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.413550                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.161927                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.161927                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.213965                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.214047                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.213965                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.214047                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78063.994055                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78063.994055                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67182.672234                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67182.672234                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77383.356880                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77383.356880                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67182.672234                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77655.418921                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77650.283372                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67182.672234                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77655.418921                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77650.283372                       # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests     18249005                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests      9121977                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops         1268                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1268                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp       7239688                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty      4708742                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean            3                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict      6334123                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq      1887340                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp      1887340                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq          958                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq      7238730                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1919                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     27374114                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total          27376033                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        61504                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    820011072                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          820072576                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                     1920891                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples     11047919                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        0.000115                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.010713                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0           11046651     99.99%     99.99% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1               1268      0.01%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total       11047919                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy    12811108500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          1.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy       1437000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy   13689105000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          1.1                       # Layer utilization (%)
system.membus.trans_dist::ReadResp            1173106                       # Transaction distribution
system.membus.trans_dist::WritebackDirty      1022139                       # Transaction distribution
system.membus.trans_dist::CleanEvict           897726                       # Transaction distribution
system.membus.trans_dist::ReadExReq            780510                       # Transaction distribution
system.membus.trans_dist::ReadExResp           780510                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq       1173106                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      5827097                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                5827097                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    190448320                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               190448320                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoop_fanout::samples           3873481                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                 3873481    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total             3873481                       # Request fanout histogram
system.membus.reqLayer0.occupancy          8428417500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.7                       # Layer utilization (%)
system.membus.respLayer1.occupancy        10685410500                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.9                       # Layer utilization (%)

---------- End Simulation Statistics   ----------