path: root/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.685488                       # Number of seconds simulated
sim_ticks                                685488076000                       # Number of ticks simulated
final_tick                               685488076000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 134484                       # Simulator instruction rate (inst/s)
host_op_rate                                   134484                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               53101916                       # Simulator tick rate (ticks/s)
host_mem_usage                                 257516                       # Number of bytes of host memory used
host_seconds                                 12908.91                       # Real time elapsed on the host
sim_insts                                  1736043781                       # Number of instructions simulated
sim_ops                                    1736043781                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst             61952                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data         125793664                       # Number of bytes read from this memory
system.physmem.bytes_read::total            125855616                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst        61952                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           61952                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     65265536                       # Number of bytes written to this memory
system.physmem.bytes_written::total          65265536                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst                968                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data            1965526                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               1966494                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1019774                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1019774                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst                90376                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data            183509631                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total               183600008                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst           90376                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total              90376                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks          95210316                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total               95210316                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks          95210316                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst               90376                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data           183509631                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              278810323                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                       1966494                       # Number of read requests accepted
system.physmem.writeReqs                      1019774                       # Number of write requests accepted
system.physmem.readBursts                     1966494                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                    1019774                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                125820608                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     35008                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  65264256                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                 125855616                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               65265536                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      547                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0              119024                       # Per bank write bursts
system.physmem.perBankRdBursts::1              114431                       # Per bank write bursts
system.physmem.perBankRdBursts::2              116551                       # Per bank write bursts
system.physmem.perBankRdBursts::3              118044                       # Per bank write bursts
system.physmem.perBankRdBursts::4              118169                       # Per bank write bursts
system.physmem.perBankRdBursts::5              117821                       # Per bank write bursts
system.physmem.perBankRdBursts::6              120193                       # Per bank write bursts
system.physmem.perBankRdBursts::7              124929                       # Per bank write bursts
system.physmem.perBankRdBursts::8              127563                       # Per bank write bursts
system.physmem.perBankRdBursts::9              130460                       # Per bank write bursts
system.physmem.perBankRdBursts::10             129120                       # Per bank write bursts
system.physmem.perBankRdBursts::11             130791                       # Per bank write bursts
system.physmem.perBankRdBursts::12             126621                       # Per bank write bursts
system.physmem.perBankRdBursts::13             125625                       # Per bank write bursts
system.physmem.perBankRdBursts::14             122955                       # Per bank write bursts
system.physmem.perBankRdBursts::15             123650                       # Per bank write bursts
system.physmem.perBankWrBursts::0               61294                       # Per bank write bursts
system.physmem.perBankWrBursts::1               61576                       # Per bank write bursts
system.physmem.perBankWrBursts::2               60653                       # Per bank write bursts
system.physmem.perBankWrBursts::3               61320                       # Per bank write bursts
system.physmem.perBankWrBursts::4               61767                       # Per bank write bursts
system.physmem.perBankWrBursts::5               63184                       # Per bank write bursts
system.physmem.perBankWrBursts::6               64210                       # Per bank write bursts
system.physmem.perBankWrBursts::7               65704                       # Per bank write bursts
system.physmem.perBankWrBursts::8               65475                       # Per bank write bursts
system.physmem.perBankWrBursts::9               65876                       # Per bank write bursts
system.physmem.perBankWrBursts::10              65422                       # Per bank write bursts
system.physmem.perBankWrBursts::11              65733                       # Per bank write bursts
system.physmem.perBankWrBursts::12              64307                       # Per bank write bursts
system.physmem.perBankWrBursts::13              64297                       # Per bank write bursts
system.physmem.perBankWrBursts::14              64633                       # Per bank write bursts
system.physmem.perBankWrBursts::15              64303                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           1                       # Number of times write queue was full causing retry
system.physmem.totGap                    685487953500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                 1966494                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                1019774                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                   1645141                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    231582                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     69181                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                     20030                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                        11                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                     45485                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                     45698                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                     45690                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                     45678                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                     45669                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                     45680                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                     45691                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                     45674                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                     45676                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                     45713                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                    45709                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                    45705                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                    45771                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                    45761                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                    45979                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    46118                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    46280                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    47317                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    47531                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    47531                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    49534                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    48711                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                      939                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                      183                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                       27                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                       11                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        3                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        3                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples      1822247                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      104.837037                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean      80.099826                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     197.854977                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::64-65        1460763     80.16%     80.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-129       186024     10.21%     90.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192-193        72307      3.97%     94.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-257        32393      1.78%     96.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320-321        16822      0.92%     97.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-385        10551      0.58%     97.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448-449         6953      0.38%     98.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-513         6800      0.37%     98.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576-577         3880      0.21%     98.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-641         3184      0.17%     98.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704-705         2717      0.15%     98.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-769         2015      0.11%     99.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832-833         1651      0.09%     99.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-897         1492      0.08%     99.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960-961         1271      0.07%     99.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1025         1102      0.06%     99.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088-1089          982      0.05%     99.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152-1153         1041      0.06%     99.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216-1217          864      0.05%     99.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280-1281          817      0.04%     99.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344-1345          719      0.04%     99.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408-1409         2906      0.16%     99.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472-1473          391      0.02%     99.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536-1537          753      0.04%     99.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600-1601          249      0.01%     99.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664-1665          220      0.01%     99.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728-1729          185      0.01%     99.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1792-1793          207      0.01%     99.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856-1857          171      0.01%     99.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920-1921          149      0.01%     99.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984-1985          132      0.01%     99.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2048-2049          171      0.01%     99.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112-2113          381      0.02%     99.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176-2177          117      0.01%     99.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240-2241           95      0.01%     99.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304-2305           87      0.00%     99.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368-2369           78      0.00%     99.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2432-2433           78      0.00%     99.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496-2497           61      0.00%     99.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2560-2561           72      0.00%     99.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2624-2625           41      0.00%     99.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688-2689           45      0.00%     99.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2752-2753           36      0.00%     99.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816-2817           45      0.00%     99.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880-2881           35      0.00%     99.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2944-2945           29      0.00%     99.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3008-3009           23      0.00%     99.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3072-3073           45      0.00%     99.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3136-3137           24      0.00%     99.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3200-3201           26      0.00%     99.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3264-3265           27      0.00%     99.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3328-3329           27      0.00%     99.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3392-3393           22      0.00%     99.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456-3457           20      0.00%     99.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3520-3521           15      0.00%     99.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3584-3585           30      0.00%     99.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3648-3649           11      0.00%     99.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3712-3713           17      0.00%     99.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3776-3777           14      0.00%     99.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3840-3841           16      0.00%     99.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3904-3905           14      0.00%     99.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3968-3969           21      0.00%     99.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4032-4033           10      0.00%     99.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4096-4097           22      0.00%     99.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4160-4161           15      0.00%     99.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4224-4225           17      0.00%     99.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4288-4289           13      0.00%     99.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4352-4353           13      0.00%     99.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4416-4417            8      0.00%     99.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4480-4481           11      0.00%     99.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4544-4545           13      0.00%     99.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4608-4609           23      0.00%     99.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4672-4673           10      0.00%     99.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4736-4737           15      0.00%     99.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4800-4801           16      0.00%     99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4864-4865           15      0.00%     99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4928-4929           13      0.00%     99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4992-4993           14      0.00%     99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5056-5057           12      0.00%     99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5120-5121           21      0.00%     99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5184-5185           13      0.00%     99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5248-5249           18      0.00%     99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5312-5313            6      0.00%     99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5376-5377           18      0.00%     99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5440-5441           13      0.00%     99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5504-5505           11      0.00%     99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5568-5569            8      0.00%     99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5632-5633           16      0.00%     99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5696-5697            8      0.00%     99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5760-5761            8      0.00%     99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5824-5825            8      0.00%     99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5888-5889           17      0.00%     99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5952-5953            7      0.00%     99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6016-6017           14      0.00%     99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6080-6081            9      0.00%     99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6144-6145           16      0.00%     99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6208-6209            7      0.00%     99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6272-6273           14      0.00%     99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6336-6337            8      0.00%     99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6400-6401           13      0.00%     99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6464-6465           12      0.00%     99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6528-6529           14      0.00%     99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6592-6593            8      0.00%     99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6656-6657           85      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6720-6721            5      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6784-6785            6      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6848-6849           29      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6912-6913            6      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7040-7041            3      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7104-7105            1      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7168-7169            1      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7296-7297            2      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7424-7425            5      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7488-7489            1      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7552-7553            1      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7616-7617            1      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7680-7681            7      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7808-7809            2      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7936-7937            2      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8000-8001            2      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8064-8065            2      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8192-8193          125      0.01%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total        1822247                       # Bytes accessed per row activation
system.physmem.totQLat                    24360796250                       # Total ticks spent queuing
system.physmem.totMemAccLat               84735751250                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   9829735000                       # Total ticks spent in databus transfers
system.physmem.totBankLat                 50545220000                       # Total ticks spent accessing banks
system.physmem.avgQLat                       12391.38                       # Average queueing delay per DRAM burst
system.physmem.avgBankLat                    25710.37                       # Average bank access latency per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  43101.75                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                         183.55                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                          95.21                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                      183.60                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                       95.21                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           2.18                       # Data bus utilization in percentage
system.physmem.busUtilRead                       1.43                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.74                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         0.12                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        10.63                       # Average write queue length when enqueuing
system.physmem.readRowHits                     818889                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    344565                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   41.65                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  33.79                       # Row buffer hit rate for writes
system.physmem.avgGap                       229546.70                       # Average gap between requests
system.physmem.pageHitRate                      38.97                       # Row buffer hit rate, read and write combined
system.physmem.prechargeAllPercent               7.09                       # Percentage of time for which DRAM has all the banks in precharge state
system.membus.throughput                    278810323                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq             1191305                       # Transaction distribution
system.membus.trans_dist::ReadResp            1191305                       # Transaction distribution
system.membus.trans_dist::Writeback           1019774                       # Transaction distribution
system.membus.trans_dist::ReadExReq            775189                       # Transaction distribution
system.membus.trans_dist::ReadExResp           775189                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      4952762                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                4952762                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    191121152                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total           191121152                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus              191121152                       # Total data (bytes)
system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy         11874044250                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               1.7                       # Layer utilization (%)
system.membus.respLayer1.occupancy        18494220250                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              2.7                       # Layer utilization (%)
system.cpu.branchPred.lookups               381678235                       # Number of BP lookups
system.cpu.branchPred.condPredicted         296637110                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect          16088915                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups            262749250                       # Number of BTB lookups
system.cpu.branchPred.BTBHits               259783318                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             98.871193                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                24705471                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect               3030                       # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits                           0                       # ITB hits
system.cpu.dtb.fetch_misses                         0                       # ITB misses
system.cpu.dtb.fetch_acv                            0                       # ITB acv
system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
system.cpu.dtb.read_hits                    613987676                       # DTB read hits
system.cpu.dtb.read_misses                   11260420                       # DTB read misses
system.cpu.dtb.read_acv                             0                       # DTB read access violations
system.cpu.dtb.read_accesses                625248096                       # DTB read accesses
system.cpu.dtb.write_hits                   212348403                       # DTB write hits
system.cpu.dtb.write_misses                   7134109                       # DTB write misses
system.cpu.dtb.write_acv                            0                       # DTB write access violations
system.cpu.dtb.write_accesses               219482512                       # DTB write accesses
system.cpu.dtb.data_hits                    826336079                       # DTB hits
system.cpu.dtb.data_misses                   18394529                       # DTB misses
system.cpu.dtb.data_acv                             0                       # DTB access violations
system.cpu.dtb.data_accesses                844730608                       # DTB accesses
system.cpu.itb.fetch_hits                   391118478                       # ITB hits
system.cpu.itb.fetch_misses                        44                       # ITB misses
system.cpu.itb.fetch_acv                            0                       # ITB acv
system.cpu.itb.fetch_accesses               391118522                       # ITB accesses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.read_acv                             0                       # DTB read access violations
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.write_acv                            0                       # DTB write access violations
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.data_hits                            0                       # DTB hits
system.cpu.itb.data_misses                          0                       # DTB misses
system.cpu.itb.data_acv                             0                       # DTB access violations
system.cpu.itb.data_accesses                        0                       # DTB accesses
system.cpu.workload.num_syscalls                   29                       # Number of system calls
system.cpu.numCycles                       1370976153                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles          402585457                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                     3161328538                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                   381678235                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches          284488789                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     574592396                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles               140681937                       # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles              190961804                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                  143                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles          1466                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles            1                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                 391118478                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes               8069239                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples         1284965558                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              2.460244                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.144346                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                710373162     55.28%     55.28% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                 42677954      3.32%     58.60% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 21796461      1.70%     60.30% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                 39706509      3.09%     63.39% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                129357441     10.07%     73.46% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                 61547596      4.79%     78.25% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                 38577258      3.00%     81.25% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                 28126573      2.19%     83.44% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                212802604     16.56%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total           1284965558                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.278399                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        2.305896                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                434593706                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles             172173126                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 542518914                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles              18856302                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles              116823510                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved             58351123                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                   876                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts             3088655283                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                  2048                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles              116823510                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                457554918                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles               116845929                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles           6766                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 535622730                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              58111705                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts             3006575354                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                610156                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                1852925                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents              51779132                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands          2247748999                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            3899198212                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       3899055356                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups            142855                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps            1376202963                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                871546036                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts                162                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts            160                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                 123661161                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads            679705832                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores           255482967                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads          67737746                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores         37011786                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                 2724988246                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded                 122                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                2509612209                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued           3204133                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined       979747229                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined    416253397                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved             93                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples    1284965558                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         1.953058                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.971218                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           442955350     34.47%     34.47% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1           203613373     15.85%     50.32% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2           185757734     14.46%     64.77% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3           153374382     11.94%     76.71% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4           133013671     10.35%     87.06% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5            80752885      6.28%     93.35% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6            65067569      5.06%     98.41% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7            15309053      1.19%     99.60% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8             5121541      0.40%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total      1284965558                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                 2189478     11.81%     11.81% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%     11.81% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     11.81% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     11.81% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     11.81% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     11.81% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     11.81% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     11.81% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     11.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     11.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     11.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     11.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     11.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     11.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     11.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     11.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     11.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     11.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     11.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     11.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     11.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     11.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     11.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     11.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     11.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     11.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     11.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     11.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     11.81% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead               11923612     64.31%     76.12% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite               4426862     23.88%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu            1643894908     65.50%     65.50% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                  110      0.00%     65.50% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     65.50% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                 256      0.00%     65.50% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                  15      0.00%     65.50% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                 159      0.00%     65.50% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                 28      0.00%     65.50% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                  24      0.00%     65.50% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     65.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     65.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     65.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     65.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     65.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     65.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     65.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     65.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     65.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     65.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     65.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     65.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     65.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     65.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     65.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     65.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     65.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     65.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     65.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     65.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     65.50% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead            641620248     25.57%     91.07% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite           224096461      8.93%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total             2509612209                       # Type of FU issued
system.cpu.iq.rate                           1.830529                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                    18539952                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.007388                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         6324036158                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes        3703625637                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses   2413191204                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads             1897903                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes            1215976                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses       850771                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses             2527214134                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                  938027                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads         62593572                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads    235110169                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses       263246                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation       107760                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores     94754465                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads           95                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked       1543010                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles              116823510                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                56431673                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles               1297935                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts          2867161807                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts           8942583                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts             679705832                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts            255482967                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts                122                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                 282108                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                 18553                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents         107760                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect       10367292                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect      8554999                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts             18922291                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts            2462270338                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts             625248683                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts          47341871                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                     142173439                       # number of nop insts executed
system.cpu.iew.exec_refs                    844731223                       # number of memory reference insts executed
system.cpu.iew.exec_branches                300901770                       # Number of branches executed
system.cpu.iew.exec_stores                  219482540                       # Number of stores executed
system.cpu.iew.exec_rate                     1.795998                       # Inst execution rate
system.cpu.iew.wb_sent                     2441991151                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                    2414041975                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                1388322535                       # num instructions producing a value
system.cpu.iew.wb_consumers                1764247998                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.760820                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.786920                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts       826708029                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls              29                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts          16088134                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples   1168142048                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.557841                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.499033                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    654070645     55.99%     55.99% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1    174984637     14.98%     70.97% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2     86150926      7.38%     78.35% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     53558629      4.58%     82.93% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4     34734385      2.97%     85.91% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5     26071538      2.23%     88.14% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6     21585678      1.85%     89.99% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7     22876428      1.96%     91.94% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8     94109182      8.06%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total   1168142048                       # Number of insts commited each cycle
system.cpu.commit.committedInsts           1819780126                       # Number of instructions committed
system.cpu.commit.committedOps             1819780126                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                      605324165                       # Number of memory references committed
system.cpu.commit.loads                     444595663                       # Number of loads committed
system.cpu.commit.membars                           0                       # Number of memory barriers committed
system.cpu.commit.branches                  214632552                       # Number of branches committed
system.cpu.commit.fp_insts                     805525                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                1718967519                       # Number of committed integer instructions.
system.cpu.commit.function_calls             16767440                       # Number of function calls committed.
system.cpu.commit.bw_lim_events              94109182                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                   3634741821                       # The number of ROB reads
system.cpu.rob.rob_writes                  5409898345                       # The number of ROB writes
system.cpu.timesIdled                          948322                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                        86010595                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                  1736043781                       # Number of Instructions Simulated
system.cpu.committedOps                    1736043781                       # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total            1736043781                       # Number of Instructions Simulated
system.cpu.cpi                               0.789713                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.789713                       # CPI: Total CPI of All Threads
system.cpu.ipc                               1.266283                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         1.266283                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads               3318184796                       # number of integer regfile reads
system.cpu.int_regfile_writes              1932088897                       # number of integer regfile writes
system.cpu.fp_regfile_reads                     30223                       # number of floating regfile reads
system.cpu.fp_regfile_writes                      511                       # number of floating regfile writes
system.cpu.misc_regfile_reads                      25                       # number of misc regfile reads
system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
system.cpu.toL2Bus.throughput              1204982897                       # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq        7297626                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       7297626                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback      3725040                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq      1883606                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp      1883606                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1936                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     22085568                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total          22087504                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        61952                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    825939456                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total      826001408                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus         826001408                       # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy    10178244432                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          1.5                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy       1613250                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy   14084473000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          2.1                       # Layer utilization (%)
system.cpu.icache.tags.replacements                 1                       # number of replacements
system.cpu.icache.tags.tagsinuse           776.507603                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           391116973                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs               968                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs          404046.459711                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   776.507603                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.379154                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.379154                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst    391116973                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       391116973                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     391116973                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        391116973                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    391116973                       # number of overall hits
system.cpu.icache.overall_hits::total       391116973                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst         1504                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total          1504                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst         1504                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total           1504                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst         1504                       # number of overall misses
system.cpu.icache.overall_misses::total          1504                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    108221250                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    108221250                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    108221250                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    108221250                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    108221250                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    108221250                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    391118477                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    391118477                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    391118477                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    391118477                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    391118477                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    391118477                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000004                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000004                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000004                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000004                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000004                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000004                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71955.618351                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 71955.618351                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 71955.618351                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 71955.618351                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 71955.618351                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 71955.618351                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs          344                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 3                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs   114.666667                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst          536                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total          536                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst          536                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total          536                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst          536                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total          536                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst          968                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total          968                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst          968                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total          968                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst          968                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total          968                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     75754750                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total     75754750                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst     75754750                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total     75754750                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst     75754750                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total     75754750                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000002                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000002                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000002                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78259.039256                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78259.039256                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78259.039256                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 78259.039256                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78259.039256                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 78259.039256                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements          1933792                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        31423.528987                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            9058568                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs          1963567                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             4.613323                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle      28354220250                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 14586.952110                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst    26.526107                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 16810.050770                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.445158                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.000810                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.513002                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.958970                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.data      6106321                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        6106321                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks      3725040                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      3725040                       # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data      1108417                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total      1108417                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.data      7214738                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         7214738                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.data      7214738                       # number of overall hits
system.cpu.l2cache.overall_hits::total        7214738                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst          968                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data      1190337                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total      1191305                       # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       775189                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       775189                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst          968                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data      1965526                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total       1966494                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst          968                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data      1965526                       # number of overall misses
system.cpu.l2cache.overall_misses::total      1966494                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     74779750                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 102580412000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 102655191750                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  67293864000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  67293864000                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst     74779750                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 169874276000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 169949055750                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst     74779750                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 169874276000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 169949055750                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst          968                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data      7296658                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      7297626                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks      3725040                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      3725040                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data      1883606                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total      1883606                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst          968                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      9180264                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      9181232                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst          968                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      9180264                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      9181232                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst            1                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.163135                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.163246                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.411545                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.411545                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst            1                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.214103                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.214186                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst            1                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.214103                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.214186                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77251.807851                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 86177.621968                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 86170.369259                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 86809.621912                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 86809.621912                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77251.807851                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 86426.878098                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 86422.361701                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77251.807851                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86426.878098                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 86422.361701                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks      1019774                       # number of writebacks
system.cpu.l2cache.writebacks::total          1019774                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          968                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data      1190337                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total      1191305                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       775189                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       775189                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst          968                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data      1965526                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total      1966494                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst          968                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data      1965526                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total      1966494                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     62594250                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  87638263500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total  87700857750                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  57538532000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  57538532000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     62594250                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 145176795500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 145239389750                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     62594250                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 145176795500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 145239389750                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.163135                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.163246                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.411545                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.411545                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.214103                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.214186                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.214103                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.214186                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64663.481405                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 73624.749546                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 73617.468029                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 74225.165734                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 74225.165734                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64663.481405                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73861.549275                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73857.021557                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64663.481405                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73861.549275                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73857.021557                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements           9176168                       # number of replacements
system.cpu.dcache.tags.tagsinuse          4087.562922                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           694279443                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           9180264                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             75.627394                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle        5178034250                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data  4087.562922                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.997940                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.997940                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data    538739511                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       538739511                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data    155539929                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total      155539929                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data            3                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total            3                       # number of LoadLockedReq hits
system.cpu.dcache.demand_hits::cpu.data     694279440                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        694279440                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    694279440                       # number of overall hits
system.cpu.dcache.overall_hits::total       694279440                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data     11387381                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total      11387381                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      5188573                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      5188573                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data            1                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total            1                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data     16575954                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total       16575954                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data     16575954                       # number of overall misses
system.cpu.dcache.overall_misses::total      16575954                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 342766302500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 342766302500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 296010973410                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 296010973410                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       274500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total       274500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 638777275910                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 638777275910                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 638777275910                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 638777275910                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    550126892                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    550126892                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data    160728502                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total    160728502                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data            4                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total            4                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    710855394                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    710855394                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    710855394                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    710855394                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.020700                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.020700                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.032282                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.032282                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.250000                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.250000                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.023318                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.023318                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.023318                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.023318                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30100.538702                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 30100.538702                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57050.555791                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 57050.555791                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data       274500                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total       274500                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 38536.380827                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 38536.380827                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 38536.380827                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 38536.380827                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs     12380978                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets      8648655                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs            745505                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets           65134                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    16.607505                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets   132.782495                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      3725040                       # number of writebacks
system.cpu.dcache.writebacks::total           3725040                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data      4090717                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total      4090717                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data      3304974                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total      3304974                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      7395691                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      7395691                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      7395691                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      7395691                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7296664                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      7296664                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1883599                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total      1883599                       # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data            1                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total            1                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      9180263                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      9180263                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      9180263                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      9180263                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 171778792500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 171778792500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  80694684874                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  80694684874                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data       272500                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total       272500                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 252473477374                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 252473477374                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 252473477374                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 252473477374                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.013264                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.013264                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.011719                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.011719                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.250000                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.250000                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.012914                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.012914                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.012914                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.012914                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23542.099855                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23542.099855                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42840.692140                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42840.692140                       # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data       272500                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total       272500                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27501.769543                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 27501.769543                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27501.769543                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 27501.769543                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------