path: root/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.694171                       # Number of seconds simulated
sim_ticks                                694171131000                       # Number of ticks simulated
final_tick                               694171131000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 178600                       # Simulator instruction rate (inst/s)
host_op_rate                                   178600                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               71414604                       # Simulator tick rate (ticks/s)
host_mem_usage                                 227828                       # Number of bytes of host memory used
host_seconds                                  9720.30                       # Real time elapsed on the host
sim_insts                                  1736043781                       # Number of instructions simulated
sim_ops                                    1736043781                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst             61632                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data         125790400                       # Number of bytes read from this memory
system.physmem.bytes_read::total            125852032                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst        61632                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           61632                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     65261440                       # Number of bytes written to this memory
system.physmem.bytes_written::total          65261440                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst                963                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data            1965475                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               1966438                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1019710                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1019710                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst                88785                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data            181209495                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total               181298280                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst           88785                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total              88785                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks          94013475                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total               94013475                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks          94013475                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst               88785                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data           181209495                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              275311755                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                       1966438                       # Total number of read requests accepted by DRAM controller
system.physmem.writeReqs                      1019710                       # Total number of write requests accepted by DRAM controller
system.physmem.readBursts                     1966438                       # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
system.physmem.writeBursts                    1019710                       # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
system.physmem.bytesRead                    125852032                       # Total number of bytes read from memory
system.physmem.bytesWritten                  65261440                       # Total number of bytes written to memory
system.physmem.bytesConsumedRd              125852032                       # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr               65261440                       # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ                      561                       # Number of DRAM read bursts serviced by write Q
system.physmem.neitherReadNorWrite                  0                       # Reqs where no action is needed
system.physmem.perBankRdReqs::0                119011                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::1                114417                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::2                116554                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::3                118021                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::4                118126                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::5                117795                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::6                120229                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::7                124937                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::8                127536                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::9                130495                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::10               129073                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::11               130794                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::12               126583                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::13               125666                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::14               122963                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::15               123677                       # Track reads on a per bank basis
system.physmem.perBankWrReqs::0                 61282                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::1                 61566                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::2                 60662                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::3                 61309                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::4                 61746                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::5                 63171                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::6                 64226                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::7                 65702                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::8                 65470                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::9                 65888                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::10                65399                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::11                65733                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::12                64310                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::13                64314                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::14                64641                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::15                64291                       # Track writes on a per bank basis
system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
system.physmem.numWrRetry                           8                       # Number of times wr buffer was full causing retry
system.physmem.totGap                    694171008500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
system.physmem.readPktSize::2                       0                       # Categorize read packet sizes
system.physmem.readPktSize::3                       0                       # Categorize read packet sizes
system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
system.physmem.readPktSize::6                 1966438                       # Categorize read packet sizes
system.physmem.writePktSize::0                      0                       # Categorize write packet sizes
system.physmem.writePktSize::1                      0                       # Categorize write packet sizes
system.physmem.writePktSize::2                      0                       # Categorize write packet sizes
system.physmem.writePktSize::3                      0                       # Categorize write packet sizes
system.physmem.writePktSize::4                      0                       # Categorize write packet sizes
system.physmem.writePktSize::5                      0                       # Categorize write packet sizes
system.physmem.writePktSize::6                1019710                       # Categorize write packet sizes
system.physmem.rdQLenPdf::0                   1645970                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    229492                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     69771                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                     20630                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                        13                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                     43449                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                     44164                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                     44296                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                     44320                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                     44324                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                     44324                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                     44324                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                     44324                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                     44325                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                     44335                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                    44335                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                    44335                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                    44335                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                    44335                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                    44335                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    44335                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    44335                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    44335                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    44335                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    44335                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    44335                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    44335                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    44335                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                      887                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                      172                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                       40                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                       16                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                       12                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                       11                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                       11                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                       11                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                       10                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples      1724767                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      110.763752                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean      80.212194                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     303.511378                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::64-65        1378543     79.93%     79.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-129       191920     11.13%     91.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192-193        57620      3.34%     94.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-257        28373      1.65%     96.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320-321        15698      0.91%     96.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-385         9692      0.56%     97.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448-449         6693      0.39%     97.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-513         6792      0.39%     98.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576-577         3776      0.22%     98.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-641         2960      0.17%     98.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704-705         2630      0.15%     98.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-769         2677      0.16%     98.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832-833         1390      0.08%     99.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-897         1126      0.07%     99.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960-961         1092      0.06%     99.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1025          878      0.05%     99.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088-1089          859      0.05%     99.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152-1153          813      0.05%     99.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216-1217          757      0.04%     99.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280-1281          627      0.04%     99.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344-1345          709      0.04%     99.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408-1409          705      0.04%     99.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472-1473         3570      0.21%     99.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536-1537          579      0.03%     99.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600-1601          253      0.01%     99.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664-1665          194      0.01%     99.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728-1729          136      0.01%     99.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1792-1793          146      0.01%     99.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856-1857          142      0.01%     99.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920-1921           94      0.01%     99.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984-1985           85      0.00%     99.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2048-2049          102      0.01%     99.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112-2113           71      0.00%     99.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176-2177           61      0.00%     99.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240-2241           59      0.00%     99.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304-2305           49      0.00%     99.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368-2369           59      0.00%     99.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2432-2433           59      0.00%     99.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496-2497           39      0.00%     99.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2560-2561           46      0.00%     99.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2624-2625           34      0.00%     99.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688-2689           39      0.00%     99.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2752-2753           28      0.00%     99.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816-2817           48      0.00%     99.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880-2881           43      0.00%     99.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2944-2945           24      0.00%     99.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3008-3009           22      0.00%     99.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3072-3073           32      0.00%     99.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3136-3137           25      0.00%     99.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3200-3201           21      0.00%     99.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3264-3265           25      0.00%     99.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3328-3329           26      0.00%     99.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3392-3393           20      0.00%     99.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456-3457           15      0.00%     99.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3520-3521           19      0.00%     99.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3584-3585           25      0.00%     99.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3648-3649           13      0.00%     99.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3712-3713           10      0.00%     99.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3776-3777           13      0.00%     99.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3840-3841           27      0.00%     99.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3904-3905           21      0.00%     99.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3968-3969           10      0.00%     99.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4032-4033           20      0.00%     99.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4096-4097            6      0.00%     99.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4160-4161           16      0.00%     99.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4224-4225           14      0.00%     99.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4288-4289           20      0.00%     99.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4352-4353           28      0.00%     99.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4416-4417            7      0.00%     99.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4480-4481           12      0.00%     99.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4544-4545            8      0.00%     99.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4608-4609           10      0.00%     99.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4672-4673            9      0.00%     99.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4736-4737            6      0.00%     99.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4800-4801           10      0.00%     99.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4864-4865           15      0.00%     99.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4928-4929           14      0.00%     99.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4992-4993           10      0.00%     99.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5056-5057            9      0.00%     99.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5120-5121           12      0.00%     99.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5184-5185           10      0.00%     99.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5248-5249            6      0.00%     99.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5312-5313           21      0.00%     99.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5376-5377           13      0.00%     99.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5440-5441           11      0.00%     99.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5504-5505            8      0.00%     99.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5568-5569            6      0.00%     99.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5632-5633            7      0.00%     99.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5696-5697            7      0.00%     99.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5760-5761            7      0.00%     99.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5824-5825            6      0.00%     99.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5888-5889           13      0.00%     99.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5952-5953           19      0.00%     99.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6016-6017            2      0.00%     99.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6080-6081           10      0.00%     99.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6144-6145            8      0.00%     99.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6208-6209            5      0.00%     99.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6272-6273            4      0.00%     99.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6336-6337           11      0.00%     99.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6400-6401           12      0.00%     99.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6464-6465            7      0.00%     99.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6528-6529            4      0.00%     99.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6592-6593            3      0.00%     99.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6656-6657            8      0.00%     99.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6720-6721            3      0.00%     99.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6784-6785            4      0.00%     99.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6848-6849            6      0.00%     99.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6912-6913            4      0.00%     99.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6976-6977           12      0.00%     99.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7040-7041            6      0.00%     99.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7104-7105            3      0.00%     99.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7168-7169           11      0.00%     99.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7232-7233            9      0.00%     99.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7296-7297            2      0.00%     99.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7360-7361           17      0.00%     99.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7424-7425           11      0.00%     99.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7488-7489            2      0.00%     99.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7552-7553            5      0.00%     99.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7616-7617            5      0.00%     99.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7680-7681          123      0.01%     99.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7744-7745           12      0.00%     99.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7808-7809            5      0.00%     99.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7872-7873            5      0.00%     99.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7936-7937            6      0.00%     99.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8000-8001           18      0.00%     99.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8064-8065            6      0.00%     99.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8128-8129           15      0.00%     99.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8192-8193         1429      0.08%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total        1724767                       # Bytes accessed per row activation
system.physmem.totQLat                    33917679750                       # Total cycles spent in queuing delays
system.physmem.totMemAccLat               98022206000                       # Sum of mem lat for all requests
system.physmem.totBusLat                   9829385000                       # Total cycles spent in databus access
system.physmem.totBankLat                 54275141250                       # Total cycles spent in bank access
system.physmem.avgQLat                       17253.21                       # Average queueing delay per request
system.physmem.avgBankLat                    27608.62                       # Average bank access latency per request
system.physmem.avgBusLat                      5000.00                       # Average bus latency per request
system.physmem.avgMemAccLat                  49861.82                       # Average memory access latency
system.physmem.avgRdBW                         181.30                       # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW                          94.01                       # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW                 181.30                       # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW                  94.01                       # Average consumed write bandwidth in MB/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MB/s
system.physmem.busUtil                           2.15                       # Data bus utilization in percentage
system.physmem.avgRdQLen                         0.14                       # Average read queue length over time
system.physmem.avgWrQLen                        10.67                       # Average write queue length over time
system.physmem.readRowHits                     908058                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    352757                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   46.19                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  34.59                       # Row buffer hit rate for writes
system.physmem.avgGap                       232463.70                       # Average gap between requests
system.membus.throughput                    275311755                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq             1191259                       # Transaction distribution
system.membus.trans_dist::ReadResp            1191259                       # Transaction distribution
system.membus.trans_dist::Writeback           1019710                       # Transaction distribution
system.membus.trans_dist::ReadExReq            775179                       # Transaction distribution
system.membus.trans_dist::ReadExResp           775179                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      4952586                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                4952586                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    191113472                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total           191113472                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus              191113472                       # Total data (bytes)
system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy         11881655250                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               1.7                       # Layer utilization (%)
system.membus.respLayer1.occupancy        18594236500                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              2.7                       # Layer utilization (%)
system.cpu.branchPred.lookups               381853679                       # Number of BP lookups
system.cpu.branchPred.condPredicted         296812462                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect          16082560                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups            263010897                       # Number of BTB lookups
system.cpu.branchPred.BTBHits               259938392                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             98.831796                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                24703686                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect               3043                       # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits                           0                       # ITB hits
system.cpu.dtb.fetch_misses                         0                       # ITB misses
system.cpu.dtb.fetch_acv                            0                       # ITB acv
system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
system.cpu.dtb.read_hits                    613967200                       # DTB read hits
system.cpu.dtb.read_misses                   11252585                       # DTB read misses
system.cpu.dtb.read_acv                             0                       # DTB read access violations
system.cpu.dtb.read_accesses                625219785                       # DTB read accesses
system.cpu.dtb.write_hits                   212300531                       # DTB write hits
system.cpu.dtb.write_misses                   7117395                       # DTB write misses
system.cpu.dtb.write_acv                            0                       # DTB write access violations
system.cpu.dtb.write_accesses               219417926                       # DTB write accesses
system.cpu.dtb.data_hits                    826267731                       # DTB hits
system.cpu.dtb.data_misses                   18369980                       # DTB misses
system.cpu.dtb.data_acv                             0                       # DTB access violations
system.cpu.dtb.data_accesses                844637711                       # DTB accesses
system.cpu.itb.fetch_hits                   391085180                       # ITB hits
system.cpu.itb.fetch_misses                        51                       # ITB misses
system.cpu.itb.fetch_acv                            0                       # ITB acv
system.cpu.itb.fetch_accesses               391085231                       # ITB accesses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.read_acv                             0                       # DTB read access violations
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.write_acv                            0                       # DTB write access violations
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.data_hits                            0                       # DTB hits
system.cpu.itb.data_misses                          0                       # DTB misses
system.cpu.itb.data_acv                             0                       # DTB access violations
system.cpu.itb.data_accesses                        0                       # DTB accesses
system.cpu.workload.num_syscalls                   29                       # Number of system calls
system.cpu.numCycles                       1388342263                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles          402551684                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                     3162454030                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                   381853679                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches          284642078                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     574754052                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles               140783496                       # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles              197047269                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                   30                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles          1488                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles           13                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                 391085180                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes               8065065                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples         1291251504                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              2.449139                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.141692                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                716497452     55.49%     55.49% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                 42682670      3.31%     58.79% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 21784053      1.69%     60.48% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                 39696423      3.07%     63.56% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                129425846     10.02%     73.58% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                 61545626      4.77%     78.35% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                 38574460      2.99%     81.33% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                 28124081      2.18%     83.51% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                212920893     16.49%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total           1291251504                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.275043                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        2.277863                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                434540420                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles             178303124                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 542717448                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles              18794331                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles              116896181                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved             58354479                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                   840                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts             3089587827                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                  2045                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles              116896181                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                457532531                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles               123212849                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles           5836                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 535730171                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              57873936                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts             3007379456                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                610253                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                1826446                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents              51579864                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands          2248363732                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            3900421320                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       3899178783                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups           1242537                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps            1376202963                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                872160769                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts                168                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts            168                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                 123444205                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads            679751883                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores           255539846                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads          68026727                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores         37555626                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                 2725485841                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded                 123                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                2509620077                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued           3191439                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined       980254556                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined    417071077                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved             94                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples    1291251504                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         1.943556                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.971187                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           449456095     34.81%     34.81% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1           203314241     15.75%     50.55% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2           185688017     14.38%     64.93% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3           153487226     11.89%     76.82% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4           133078124     10.31%     87.13% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5            80722513      6.25%     93.38% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6            65115490      5.04%     98.42% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7            15268261      1.18%     99.60% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8             5121537      0.40%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total      1291251504                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                 2192750     11.84%     11.84% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%     11.84% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     11.84% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     11.84% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     11.84% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     11.84% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     11.84% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     11.84% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     11.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     11.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     11.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     11.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     11.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     11.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     11.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     11.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     11.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     11.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     11.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     11.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     11.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     11.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     11.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     11.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     11.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     11.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     11.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     11.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     11.84% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead               11923038     64.36%     76.19% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite               4410634     23.81%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu            1643953882     65.51%     65.51% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                  103      0.00%     65.51% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     65.51% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                 266      0.00%     65.51% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                  15      0.00%     65.51% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                 157      0.00%     65.51% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                 35      0.00%     65.51% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                  25      0.00%     65.51% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     65.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     65.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     65.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     65.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     65.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     65.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     65.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     65.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     65.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     65.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     65.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     65.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     65.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     65.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     65.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     65.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     65.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     65.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     65.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     65.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     65.51% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead            641631628     25.57%     91.07% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite           224033966      8.93%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total             2509620077                       # Type of FU issued
system.cpu.iq.rate                           1.807638                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                    18526422                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.007382                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         6330307505                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes        3704630064                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses   2413135648                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads             1902014                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes            1217951                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses       852306                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses             2527206104                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                  940395                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads         62612888                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads    235156220                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses       263801                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation       109236                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores     94811344                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads          161                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked       1579414                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles              116896181                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                59627165                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles               1293281                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts          2867673451                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts           8945086                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts             679751883                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts            255539846                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts                123                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                 277586                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                 17880                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents         109236                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect       10358298                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect      8554506                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts             18912804                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts            2462213177                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts             625220360                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts          47406900                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                     142187487                       # number of nop insts executed
system.cpu.iew.exec_refs                    844638305                       # number of memory reference insts executed
system.cpu.iew.exec_branches                300894564                       # Number of branches executed
system.cpu.iew.exec_stores                  219417945                       # Number of stores executed
system.cpu.iew.exec_rate                     1.773491                       # Inst execution rate
system.cpu.iew.wb_sent                     2441919357                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                    2413987954                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                1388436926                       # num instructions producing a value
system.cpu.iew.wb_consumers                1764428707                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.738756                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.786905                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts       827192555                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls              29                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts          16081773                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples   1174355323                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.549599                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.495377                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    660542597     56.25%     56.25% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1    174710504     14.88%     71.12% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2     86129545      7.33%     78.46% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     53592661      4.56%     83.02% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4     34688707      2.95%     85.98% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5     26049111      2.22%     88.19% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6     21601989      1.84%     90.03% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7     22901440      1.95%     91.98% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8     94138769      8.02%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total   1174355323                       # Number of insts commited each cycle
system.cpu.commit.committedInsts           1819780126                       # Number of instructions committed
system.cpu.commit.committedOps             1819780126                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                      605324165                       # Number of memory references committed
system.cpu.commit.loads                     444595663                       # Number of loads committed
system.cpu.commit.membars                           0                       # Number of memory barriers committed
system.cpu.commit.branches                  214632552                       # Number of branches committed
system.cpu.commit.fp_insts                     805525                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                1718967519                       # Number of committed integer instructions.
system.cpu.commit.function_calls             16767440                       # Number of function calls committed.
system.cpu.commit.bw_lim_events              94138769                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                   3641410035                       # The number of ROB reads
system.cpu.rob.rob_writes                  5410940495                       # The number of ROB writes
system.cpu.timesIdled                          938493                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                        97090759                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                  1736043781                       # Number of Instructions Simulated
system.cpu.committedOps                    1736043781                       # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total            1736043781                       # Number of Instructions Simulated
system.cpu.cpi                               0.799716                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.799716                       # CPI: Total CPI of All Threads
system.cpu.ipc                               1.250444                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         1.250444                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads               3318091757                       # number of integer regfile reads
system.cpu.int_regfile_writes              1932096202                       # number of integer regfile writes
system.cpu.fp_regfile_reads                     30725                       # number of floating regfile reads
system.cpu.fp_regfile_writes                      534                       # number of floating regfile writes
system.cpu.misc_regfile_reads                      25                       # number of misc regfile reads
system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
system.cpu.toL2Bus.throughput              1189905456                       # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq        7297551                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       7297551                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback      3725037                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq      1883631                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp      1883631                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1926                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     22085475                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total          22087401                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        61632                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    825936384                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total      825998016                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus         825998016                       # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy    10178230165                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          1.5                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy       1633750                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy   14189007000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          2.0                       # Layer utilization (%)
system.cpu.icache.tags.replacements                 1                       # number of replacements
system.cpu.icache.tags.tagsinuse           770.551884                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           391083687                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs               963                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs          406109.747664                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   770.551884                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.376246                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.376246                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst    391083687                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       391083687                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     391083687                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        391083687                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    391083687                       # number of overall hits
system.cpu.icache.overall_hits::total       391083687                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst         1493                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total          1493                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst         1493                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total           1493                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst         1493                       # number of overall misses
system.cpu.icache.overall_misses::total          1493                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    108163750                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    108163750                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    108163750                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    108163750                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    108163750                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    108163750                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    391085180                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    391085180                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    391085180                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    391085180                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    391085180                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    391085180                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000004                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000004                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000004                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000004                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000004                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000004                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72447.253851                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 72447.253851                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 72447.253851                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 72447.253851                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 72447.253851                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 72447.253851                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs          340                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 4                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs           85                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst          530                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total          530                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst          530                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total          530                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst          530                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total          530                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst          963                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total          963                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst          963                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total          963                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst          963                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total          963                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     75133750                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total     75133750                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst     75133750                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total     75133750                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst     75133750                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total     75133750                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000002                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000002                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000002                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78020.508827                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78020.508827                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78020.508827                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 78020.508827                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78020.508827                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 78020.508827                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements          1933728                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        31435.165334                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            9058547                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs          1963512                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             4.613441                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle      28123107250                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 14593.465528                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst    26.016964                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 16815.682842                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.445357                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.000794                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.513174                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.959325                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.data      6106292                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        6106292                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks      3725037                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      3725037                       # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data      1108452                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total      1108452                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.data      7214744                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         7214744                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.data      7214744                       # number of overall hits
system.cpu.l2cache.overall_hits::total        7214744                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst          963                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data      1190296                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total      1191259                       # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       775179                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       775179                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst          963                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data      1965475                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total       1966438                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst          963                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data      1965475                       # number of overall misses
system.cpu.l2cache.overall_misses::total      1966438                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     74164750                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 111539773000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 111613937750                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  71882646250                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  71882646250                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst     74164750                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 183422419250                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 183496584000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst     74164750                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 183422419250                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 183496584000                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst          963                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data      7296588                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      7297551                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks      3725037                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      3725037                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data      1883631                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total      1883631                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst          963                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      9180219                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      9181182                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst          963                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      9180219                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      9181182                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst            1                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.163130                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.163241                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.411534                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.411534                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst            1                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.214099                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.214181                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst            1                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.214099                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.214181                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77014.278297                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 93707.592901                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 93694.098219                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 92730.383886                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 92730.383886                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77014.278297                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93322.183823                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 93314.197549                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77014.278297                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93322.183823                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 93314.197549                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks      1019710                       # number of writebacks
system.cpu.l2cache.writebacks::total          1019710                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          963                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data      1190296                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total      1191259                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       775179                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       775179                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst          963                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data      1965475                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total      1966438                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst          963                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data      1965475                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total      1966438                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     61969250                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  96454947000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total  96516916250                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  62065331750                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  62065331750                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     61969250                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 158520278750                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 158582248000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     61969250                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 158520278750                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 158582248000                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.163130                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.163241                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.411534                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.411534                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.214099                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.214181                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.214099                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.214181                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64350.207684                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 81034.420850                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 81020.933525                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80065.806414                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80065.806414                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64350.207684                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80652.401455                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 80644.417978                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64350.207684                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80652.401455                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 80644.417978                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements           9176123                       # number of replacements
system.cpu.dcache.tags.tagsinuse          4087.719090                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           694209653                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           9180219                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             75.620163                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle        5145271250                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data  4087.719090                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.997978                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.997978                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data    538667558                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       538667558                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data    155542093                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total      155542093                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data            2                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total            2                       # number of LoadLockedReq hits
system.cpu.dcache.demand_hits::cpu.data     694209651                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        694209651                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    694209651                       # number of overall hits
system.cpu.dcache.overall_hits::total       694209651                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data     11383512                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total      11383512                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      5186409                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      5186409                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data            1                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total            1                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data     16569921                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total       16569921                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data     16569921                       # number of overall misses
system.cpu.dcache.overall_misses::total      16569921                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 354593331250                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 354593331250                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 296662127899                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 296662127899                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       461500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total       461500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 651255459149                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 651255459149                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 651255459149                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 651255459149                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    550051070                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    550051070                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data    160728502                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total    160728502                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data            3                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total            3                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    710779572                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    710779572                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    710779572                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    710779572                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.020695                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.020695                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.032268                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.032268                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.333333                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.333333                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.023312                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.023312                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.023312                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.023312                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31149.730527                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 31149.730527                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57199.909976                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 57199.909976                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data       461500                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total       461500                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 39303.473997                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 39303.473997                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 39303.473997                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 39303.473997                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs     13761211                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets      8306103                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs            744858                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets           65135                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    18.474946                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets   127.521348                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      3725037                       # number of writebacks
system.cpu.dcache.writebacks::total           3725037                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data      4086921                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total      4086921                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data      3302782                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total      3302782                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      7389703                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      7389703                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      7389703                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      7389703                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7296591                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      7296591                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1883627                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total      1883627                       # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data            1                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total            1                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      9180218                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      9180218                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      9180218                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      9180218                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 180738700500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 180738700500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  85282559486                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  85282559486                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data       459500                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total       459500                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 266021259986                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 266021259986                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 266021259986                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 266021259986                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.013265                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.013265                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.011719                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.011719                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.333333                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.333333                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.012916                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.012916                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.012916                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.012916                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24770.293484                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24770.293484                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45275.715142                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45275.715142                       # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data       459500                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total       459500                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28977.662620                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 28977.662620                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28977.662620                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 28977.662620                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------