blob: aae431db61466980caaefb37c9a00f173fc88978 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
|
---------- Begin Simulation Statistics ----------
sim_seconds 0.680209 # Number of seconds simulated
sim_ticks 680209231000 # Number of ticks simulated
final_tick 680209231000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 134123 # Simulator instruction rate (inst/s)
host_op_rate 134123 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 52551522 # Simulator tick rate (ticks/s)
host_mem_usage 268516 # Number of bytes of host memory used
host_seconds 12943.66 # Real time elapsed on the host
sim_insts 1736043781 # Number of instructions simulated
sim_ops 1736043781 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 61568 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 125794880 # Number of bytes read from this memory
system.physmem.bytes_read::total 125856448 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 61568 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 61568 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 65262848 # Number of bytes written to this memory
system.physmem.bytes_written::total 65262848 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 962 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1965545 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1966507 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1019732 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1019732 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 90513 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 184935567 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 185026081 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 90513 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 90513 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 95945255 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 95945255 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 95945255 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 90513 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 184935567 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 280971335 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 1966507 # Number of read requests accepted
system.physmem.writeReqs 1019732 # Number of write requests accepted
system.physmem.readBursts 1966507 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 1019732 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 125774784 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 81664 # Total number of bytes read from write queue
system.physmem.bytesWritten 65260864 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 125856448 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 65262848 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 1276 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 118983 # Per bank write bursts
system.physmem.perBankRdBursts::1 114362 # Per bank write bursts
system.physmem.perBankRdBursts::2 116533 # Per bank write bursts
system.physmem.perBankRdBursts::3 118021 # Per bank write bursts
system.physmem.perBankRdBursts::4 118095 # Per bank write bursts
system.physmem.perBankRdBursts::5 117780 # Per bank write bursts
system.physmem.perBankRdBursts::6 120157 # Per bank write bursts
system.physmem.perBankRdBursts::7 124901 # Per bank write bursts
system.physmem.perBankRdBursts::8 127484 # Per bank write bursts
system.physmem.perBankRdBursts::9 130413 # Per bank write bursts
system.physmem.perBankRdBursts::10 129050 # Per bank write bursts
system.physmem.perBankRdBursts::11 130729 # Per bank write bursts
system.physmem.perBankRdBursts::12 126632 # Per bank write bursts
system.physmem.perBankRdBursts::13 125586 # Per bank write bursts
system.physmem.perBankRdBursts::14 122901 # Per bank write bursts
system.physmem.perBankRdBursts::15 123604 # Per bank write bursts
system.physmem.perBankWrBursts::0 61270 # Per bank write bursts
system.physmem.perBankWrBursts::1 61551 # Per bank write bursts
system.physmem.perBankWrBursts::2 60668 # Per bank write bursts
system.physmem.perBankWrBursts::3 61328 # Per bank write bursts
system.physmem.perBankWrBursts::4 61752 # Per bank write bursts
system.physmem.perBankWrBursts::5 63187 # Per bank write bursts
system.physmem.perBankWrBursts::6 64234 # Per bank write bursts
system.physmem.perBankWrBursts::7 65693 # Per bank write bursts
system.physmem.perBankWrBursts::8 65471 # Per bank write bursts
system.physmem.perBankWrBursts::9 65863 # Per bank write bursts
system.physmem.perBankWrBursts::10 65411 # Per bank write bursts
system.physmem.perBankWrBursts::11 65720 # Per bank write bursts
system.physmem.perBankWrBursts::12 64318 # Per bank write bursts
system.physmem.perBankWrBursts::13 64300 # Per bank write bursts
system.physmem.perBankWrBursts::14 64642 # Per bank write bursts
system.physmem.perBankWrBursts::15 64293 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 680209108500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 1966507 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 1019732 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 1643607 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 226349 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 73697 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 21571 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 28201 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 29888 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 50211 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 56677 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 59143 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 60086 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 60363 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 60607 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 60720 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 60883 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 61104 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 61463 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 63111 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 63876 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 61304 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 61887 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 60350 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 59595 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 174 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 45 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 11 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 6 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 1771936 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 107.810521 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 82.950451 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 136.949127 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 1375751 77.64% 77.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 273384 15.43% 93.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 53057 2.99% 96.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 21092 1.19% 97.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 12942 0.73% 97.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 6638 0.37% 98.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 4973 0.28% 98.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 3952 0.22% 98.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 20147 1.14% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 1771936 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 59540 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 32.963117 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 163.210264 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023 59503 99.94% 99.94% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047 10 0.02% 99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-3071 10 0.02% 99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::3072-4095 8 0.01% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::4096-5119 2 0.00% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::5120-6143 1 0.00% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::6144-7167 1 0.00% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::8192-9215 1 0.00% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::16384-17407 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::19456-20479 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 59540 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 59540 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 17.126318 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 17.084701 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 1.213811 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16 29197 49.04% 49.04% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17 1546 2.60% 51.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18 22630 38.01% 89.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19 4967 8.34% 97.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20 921 1.55% 99.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21 191 0.32% 99.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22 48 0.08% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23 11 0.02% 99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24 6 0.01% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::25 2 0.00% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26 3 0.01% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::27 4 0.01% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28 2 0.00% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::29 2 0.00% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::30 4 0.01% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::31 5 0.01% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::45 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 59540 # Writes before turning the bus around for reads
system.physmem.totQLat 40008960000 # Total ticks spent queuing
system.physmem.totMemAccLat 76857041250 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 9826155000 # Total ticks spent in databus transfers
system.physmem.avgQLat 20358.40 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 39108.40 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 184.91 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 95.94 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 185.03 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 95.95 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 2.19 # Data bus utilization in percentage
system.physmem.busUtilRead 1.44 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.75 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing
system.physmem.avgWrQLen 24.89 # Average write queue length when enqueuing
system.physmem.readRowHits 795143 # Number of row buffer hits during reads
system.physmem.writeRowHits 417847 # Number of row buffer hits during writes
system.physmem.readRowHitRate 40.46 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 40.98 # Row buffer hit rate for writes
system.physmem.avgGap 227781.20 # Average gap between requests
system.physmem.pageHitRate 40.64 # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE 135240615750 # Time in different power states
system.physmem.memoryStateTime::REF 22713600000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem.memoryStateTime::ACT 522252858000 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
system.membus.throughput 280971335 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 1191350 # Transaction distribution
system.membus.trans_dist::ReadResp 1191350 # Transaction distribution
system.membus.trans_dist::Writeback 1019732 # Transaction distribution
system.membus.trans_dist::ReadExReq 775157 # Transaction distribution
system.membus.trans_dist::ReadExResp 775157 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4952746 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 4952746 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 191119296 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 191119296 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 191119296 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 11871718000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 1.7 # Layer utilization (%)
system.membus.respLayer1.occupancy 18474668250 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 2.7 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.branchPred.lookups 381496982 # Number of BP lookups
system.cpu.branchPred.condPredicted 296448748 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 16088801 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 262281784 # Number of BTB lookups
system.cpu.branchPred.BTBHits 259596653 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 98.976242 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 24710775 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 3135 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 613956448 # DTB read hits
system.cpu.dtb.read_misses 11261576 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 625218024 # DTB read accesses
system.cpu.dtb.write_hits 212357219 # DTB write hits
system.cpu.dtb.write_misses 7142526 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 219499745 # DTB write accesses
system.cpu.dtb.data_hits 826313667 # DTB hits
system.cpu.dtb.data_misses 18404102 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 844717769 # DTB accesses
system.cpu.itb.fetch_hits 391069582 # ITB hits
system.cpu.itb.fetch_misses 39 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 391069621 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 29 # Number of system calls
system.cpu.numCycles 1360418463 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles 402539494 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 3160334453 # Number of instructions fetch has processed
system.cpu.fetch.Branches 381496982 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 284307428 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 574405529 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 140578200 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 186557630 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 26 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 1439 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 391069582 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 8066485 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 1280247946 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.468533 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.146412 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 705842417 55.13% 55.13% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 42672657 3.33% 58.47% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 21781408 1.70% 60.17% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 39699602 3.10% 63.27% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 129277672 10.10% 73.37% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 61541075 4.81% 78.17% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 38576961 3.01% 81.19% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 28126887 2.20% 83.38% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 212729267 16.62% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 1280247946 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.280426 # Number of branch fetches per cycle
system.cpu.fetch.rate 2.323061 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 434538205 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 167760960 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 542351250 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 18854501 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 116743030 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 58351365 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 885 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 3087789939 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 2070 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 116743030 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 457481337 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 112438612 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 7413 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 535473100 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 58104454 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 3005831981 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 610085 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 1830591 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 51785017 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 2247201366 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 3898074686 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 3897930349 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 144336 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 870998403 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 181 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 180 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 123645792 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 679622906 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 255441649 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 67625349 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 36837000 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 2724438630 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 139 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 2509429146 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 3195077 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 979206212 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 415660734 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 110 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 1280247946 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.960112 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.971405 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 438364734 34.24% 34.24% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 203576191 15.90% 50.14% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 185673841 14.50% 64.64% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 153359678 11.98% 76.62% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 133007255 10.39% 87.01% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 80763135 6.31% 93.32% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 65057682 5.08% 98.40% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 15327988 1.20% 99.60% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 5117442 0.40% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 1280247946 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 2183926 11.79% 11.79% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 11.79% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 11.79% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.79% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.79% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.79% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 11.79% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.79% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 11.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 11.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.79% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 11926883 64.38% 76.16% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 4416070 23.84% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 1643735577 65.50% 65.50% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 113 0.00% 65.50% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.50% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 274 0.00% 65.50% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 15 0.00% 65.50% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 163 0.00% 65.50% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 33 0.00% 65.50% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 25 0.00% 65.50% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.50% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 641577426 25.57% 91.07% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 224115520 8.93% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 2509429146 # Type of FU issued
system.cpu.iq.rate 1.844601 # Inst issue rate
system.cpu.iq.fu_busy_cnt 18526879 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.007383 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 6318927693 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 3702533179 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 2413056574 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 1900501 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 1218976 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 851931 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 2527016485 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 939540 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 62611923 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 235027243 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 263015 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 108918 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 94713147 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 189 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 1519116 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 116743030 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 54024400 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 1298779 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 2866611550 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 8938226 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 679622906 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 255441649 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 139 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 284739 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 17925 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 108918 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 10360501 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 8559141 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 18919642 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 2462113163 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 625218563 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 47315983 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 142172781 # number of nop insts executed
system.cpu.iew.exec_refs 844718328 # number of memory reference insts executed
system.cpu.iew.exec_branches 300875979 # Number of branches executed
system.cpu.iew.exec_stores 219499765 # Number of stores executed
system.cpu.iew.exec_rate 1.809820 # Inst execution rate
system.cpu.iew.wb_sent 2441867145 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 2413908505 # cumulative count of insts written-back
system.cpu.iew.wb_producers 1388259644 # num instructions producing a value
system.cpu.iew.wb_consumers 1764197986 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.774387 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.786907 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts 826160079 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 16088003 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 1163504916 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.564050 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.502160 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 649463962 55.82% 55.82% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 174969107 15.04% 70.86% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 86152065 7.40% 78.26% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 53532710 4.60% 82.86% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 34727147 2.98% 85.85% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 26083842 2.24% 88.09% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 21573250 1.85% 89.94% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 22881203 1.97% 91.91% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 94121630 8.09% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 1163504916 # Number of insts commited each cycle
system.cpu.commit.committedInsts 1819780126 # Number of instructions committed
system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 605324165 # Number of memory references committed
system.cpu.commit.loads 444595663 # Number of loads committed
system.cpu.commit.membars 0 # Number of memory barriers committed
system.cpu.commit.branches 214632552 # Number of branches committed
system.cpu.commit.fp_insts 805525 # Number of committed floating point instructions.
system.cpu.commit.int_insts 1718967519 # Number of committed integer instructions.
system.cpu.commit.function_calls 16767440 # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass 83736345 4.60% 4.60% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu 1130719227 62.13% 66.74% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult 75 0.00% 66.74% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.74% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 166 0.00% 66.74% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 13 0.00% 66.74% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 100 0.00% 66.74% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 11 0.00% 66.74% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 24 0.00% 66.74% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 66.74% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 66.74% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 66.74% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 66.74% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 66.74% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 66.74% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 66.74% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 66.74% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 66.74% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 66.74% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 66.74% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 66.74% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 66.74% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 66.74% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 66.74% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 66.74% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 66.74% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 66.74% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.74% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.74% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.74% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead 444595663 24.43% 91.17% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 160728502 8.83% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 1819780126 # Class of committed instruction
system.cpu.commit.bw_lim_events 94121630 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 3629544291 # The number of ROB reads
system.cpu.rob.rob_writes 5408721730 # The number of ROB writes
system.cpu.timesIdled 949757 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 80170517 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1736043781 # Number of Instructions Simulated
system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated
system.cpu.cpi 0.783631 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.783631 # CPI: Total CPI of All Threads
system.cpu.ipc 1.276110 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.276110 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 3317990648 # number of integer regfile reads
system.cpu.int_regfile_writes 1931970641 # number of integer regfile writes
system.cpu.fp_regfile_reads 30869 # number of floating regfile reads
system.cpu.fp_regfile_writes 545 # number of floating regfile writes
system.cpu.misc_regfile_reads 25 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
system.cpu.toL2Bus.throughput 1214348707 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 7297685 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 7297685 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 3725127 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 1883613 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 1883613 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1924 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22085799 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 22087723 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61568 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 825949632 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total 826011200 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus 826011200 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 10178394945 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 1603000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 14072846750 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 2.1 # Layer utilization (%)
system.cpu.icache.tags.replacements 1 # number of replacements
system.cpu.icache.tags.tagsinuse 772.655537 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 391068098 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 962 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 406515.694387 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 772.655537 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.377273 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.377273 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 961 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 902 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.469238 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 782140126 # Number of tag accesses
system.cpu.icache.tags.data_accesses 782140126 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 391068098 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 391068098 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 391068098 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 391068098 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 391068098 # number of overall hits
system.cpu.icache.overall_hits::total 391068098 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1484 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1484 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1484 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1484 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1484 # number of overall misses
system.cpu.icache.overall_misses::total 1484 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 102456750 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 102456750 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 102456750 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 102456750 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 102456750 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 102456750 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 391069582 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 391069582 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 391069582 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 391069582 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 391069582 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 391069582 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69040.936658 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 69040.936658 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 69040.936658 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 69040.936658 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 69040.936658 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 69040.936658 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 407 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs 203.500000 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 522 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 522 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 522 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 522 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 522 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 522 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 962 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 962 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 962 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 962 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 962 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 962 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 71417000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 71417000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 71417000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 71417000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 71417000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 71417000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74238.045738 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74238.045738 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74238.045738 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 74238.045738 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74238.045738 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 74238.045738 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 1933800 # number of replacements
system.cpu.l2cache.tags.tagsinuse 31420.392793 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 9058700 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 1963581 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 4.613357 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 28339083250 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 14569.495652 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.490666 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 16824.406475 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.444626 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000808 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.513440 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.958874 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 29781 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 150 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 975 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 593 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 17306 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 10757 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908844 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 107098594 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 107098594 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.data 6106335 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 6106335 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 3725127 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 3725127 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 1108456 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 1108456 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.data 7214791 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 7214791 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.data 7214791 # number of overall hits
system.cpu.l2cache.overall_hits::total 7214791 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 962 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 1190388 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 1191350 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 775157 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 775157 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 962 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 1965545 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 1966507 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 962 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 1965545 # number of overall misses
system.cpu.l2cache.overall_misses::total 1966507 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 70450000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 97815753000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 97886203000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 63988346750 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 63988346750 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 70450000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 161804099750 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 161874549750 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 70450000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 161804099750 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 161874549750 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 962 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 7296723 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 7297685 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 3725127 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 3725127 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1883613 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 1883613 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 962 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 9180336 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 9181298 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 962 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 9180336 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 9181298 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.163140 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.163250 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.411527 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.411527 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.214104 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.214186 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.214104 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.214186 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73232.848233 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82171.319771 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 82164.102069 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82548.885903 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82548.885903 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73232.848233 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82320.221491 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 82315.776018 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73232.848233 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82320.221491 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 82315.776018 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 1019732 # number of writebacks
system.cpu.l2cache.writebacks::total 1019732 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 962 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1190388 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 1191350 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 775157 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 775157 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 962 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 1965545 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 1966507 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 962 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 1965545 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 1966507 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 58345500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 82892612500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 82950958000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 54245247750 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 54245247750 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 58345500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 137137860250 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 137196205750 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 58345500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 137137860250 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 137196205750 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163140 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163250 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.411527 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.411527 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214104 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.214186 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214104 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.214186 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60650.207900 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 69634.953057 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69627.697990 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69979.691533 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69979.691533 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60650.207900 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69770.908450 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69766.446674 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60650.207900 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69770.908450 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69766.446674 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements 9176240 # number of replacements
system.cpu.dcache.tags.tagsinuse 4087.503872 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 694248122 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 9180336 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 75.623389 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 5175532250 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 4087.503872 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.997926 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.997926 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 694 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 2982 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 416 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 1430846728 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 1430846728 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 538710092 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 538710092 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 155538028 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 155538028 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 2 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 2 # number of LoadLockedReq hits
system.cpu.dcache.demand_hits::cpu.data 694248120 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 694248120 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 694248120 # number of overall hits
system.cpu.dcache.overall_hits::total 694248120 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 11394599 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 11394599 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 5190474 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 5190474 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 16585073 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 16585073 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 16585073 # number of overall misses
system.cpu.dcache.overall_misses::total 16585073 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 331603001250 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 331603001250 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 288972510585 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 288972510585 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 129500 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 129500 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 620575511835 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 620575511835 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 620575511835 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 620575511835 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 550104691 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 550104691 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 3 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 710833193 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 710833193 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 710833193 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 710833193 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020714 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.020714 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032293 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.032293 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.333333 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.333333 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.023332 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.023332 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.023332 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.023332 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 29101.770168 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 29101.770168 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55673.626452 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 55673.626452 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 129500 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 129500 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 37417.713617 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 37417.713617 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 37417.713617 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 37417.713617 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 11561530 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 8659652 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 743678 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 65135 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 15.546419 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 132.949290 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 3725127 # number of writebacks
system.cpu.dcache.writebacks::total 3725127 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4097867 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 4097867 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3306871 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 3306871 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 7404738 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 7404738 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 7404738 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 7404738 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7296732 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 7296732 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883603 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 1883603 # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 9180335 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 9180335 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 9180335 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 9180335 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 167014367250 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 167014367250 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 77391574454 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 77391574454 # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 127500 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 127500 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 244405941704 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 244405941704 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 244405941704 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 244405941704 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013264 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013264 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011719 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011719 # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.333333 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.333333 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012915 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.012915 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012915 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.012915 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22888.927159 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22888.927159 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41086.988317 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41086.988317 # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 127500 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 127500 # average LoadLockedReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26622.769398 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 26622.769398 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26622.769398 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 26622.769398 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
|