path: root/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.671755                       # Number of seconds simulated
sim_ticks                                671754803000                       # Number of ticks simulated
final_tick                               671754803000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 168955                       # Simulator instruction rate (inst/s)
host_op_rate                                   168955                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               65376371                       # Simulator tick rate (ticks/s)
host_mem_usage                                 298196                       # Number of bytes of host memory used
host_seconds                                 10275.19                       # Real time elapsed on the host
sim_insts                                  1736043781                       # Number of instructions simulated
sim_ops                                    1736043781                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst             62400                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data         125486976                       # Number of bytes read from this memory
system.physmem.bytes_read::total            125549376                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst        62400                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           62400                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     65552256                       # Number of bytes written to this memory
system.physmem.bytes_written::total          65552256                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst                975                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data            1960734                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               1961709                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1024254                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1024254                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst                92891                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data            186804732                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total               186897623                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst           92891                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total              92891                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks          97583606                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total               97583606                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks          97583606                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst               92891                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data           186804732                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              284481229                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                       1961709                       # Number of read requests accepted
system.physmem.writeReqs                      1024254                       # Number of write requests accepted
system.physmem.readBursts                     1961709                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                    1024254                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                125464000                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     85376                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  65551040                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                 125549376                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               65552256                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                     1334                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0              118672                       # Per bank write bursts
system.physmem.perBankRdBursts::1              113926                       # Per bank write bursts
system.physmem.perBankRdBursts::2              116092                       # Per bank write bursts
system.physmem.perBankRdBursts::3              117630                       # Per bank write bursts
system.physmem.perBankRdBursts::4              117777                       # Per bank write bursts
system.physmem.perBankRdBursts::5              117495                       # Per bank write bursts
system.physmem.perBankRdBursts::6              119900                       # Per bank write bursts
system.physmem.perBankRdBursts::7              124641                       # Per bank write bursts
system.physmem.perBankRdBursts::8              127326                       # Per bank write bursts
system.physmem.perBankRdBursts::9              130085                       # Per bank write bursts
system.physmem.perBankRdBursts::10             128786                       # Per bank write bursts
system.physmem.perBankRdBursts::11             130484                       # Per bank write bursts
system.physmem.perBankRdBursts::12             126296                       # Per bank write bursts
system.physmem.perBankRdBursts::13             125416                       # Per bank write bursts
system.physmem.perBankRdBursts::14             122597                       # Per bank write bursts
system.physmem.perBankRdBursts::15             123252                       # Per bank write bursts
system.physmem.perBankWrBursts::0               61496                       # Per bank write bursts
system.physmem.perBankWrBursts::1               61762                       # Per bank write bursts
system.physmem.perBankWrBursts::2               60827                       # Per bank write bursts
system.physmem.perBankWrBursts::3               61508                       # Per bank write bursts
system.physmem.perBankWrBursts::4               61962                       # Per bank write bursts
system.physmem.perBankWrBursts::5               63415                       # Per bank write bursts
system.physmem.perBankWrBursts::6               64494                       # Per bank write bursts
system.physmem.perBankWrBursts::7               65970                       # Per bank write bursts
system.physmem.perBankWrBursts::8               65774                       # Per bank write bursts
system.physmem.perBankWrBursts::9               66157                       # Per bank write bursts
system.physmem.perBankWrBursts::10              65800                       # Per bank write bursts
system.physmem.perBankWrBursts::11              66076                       # Per bank write bursts
system.physmem.perBankWrBursts::12              64701                       # Per bank write bursts
system.physmem.perBankWrBursts::13              64671                       # Per bank write bursts
system.physmem.perBankWrBursts::14              65003                       # Per bank write bursts
system.physmem.perBankWrBursts::15              64619                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    671754707500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                 1961709                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                1024254                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                   1618535                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    241019                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     69861                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                     30932                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                        22                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         5                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    26136                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    27711                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    49355                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    56824                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    59458                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    60622                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    61121                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    61180                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    61296                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    61372                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    61501                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    61678                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    62269                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    63697                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    65054                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    62836                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    61622                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                    60248                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      181                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                       61                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                       14                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples      1769993                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      107.917046                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean      82.949504                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     137.477186                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127        1374954     77.68%     77.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255       271630     15.35%     93.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        53313      3.01%     96.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511        21496      1.21%     97.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639        12783      0.72%     97.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         6453      0.36%     98.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         4820      0.27%     98.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         3869      0.22%     98.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        20675      1.17%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total        1769993                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         60112                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        32.611592                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      146.109791                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-511           59940     99.71%     99.71% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::512-1023          128      0.21%     99.93% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-1535           10      0.02%     99.94% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1536-2047            4      0.01%     99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-2559            7      0.01%     99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2560-3071            6      0.01%     99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::3072-3583            4      0.01%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::3584-4095            2      0.00%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::4096-4607            2      0.00%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::4608-5119            2      0.00%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::6656-7167            1      0.00%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::8704-9215            1      0.00%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::9216-9727            1      0.00%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::10240-10751            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::11776-12287            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::12288-12799            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::14848-15359            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           60112                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         60112                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        17.038778                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       16.996488                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        1.239516                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16              31933     53.12%     53.12% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17               1463      2.43%     55.56% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18              20988     34.91%     90.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19               4635      7.71%     98.18% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20                815      1.36%     99.54% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21                185      0.31%     99.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22                 40      0.07%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23                 14      0.02%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24                 10      0.02%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::25                  4      0.01%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26                  3      0.00%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::27                  2      0.00%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28                  1      0.00%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::30                  1      0.00%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32                  3      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::33                  2      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::34                  1      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::35                  1      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36                  2      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::37                  2      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::38                  2      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::42                  2      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::43                  2      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::47                  1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           60112                       # Writes before turning the bus around for reads
system.physmem.totQLat                    40612494250                       # Total ticks spent queuing
system.physmem.totMemAccLat               77369525500                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   9801875000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       20716.70                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  39466.70                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                         186.77                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                          97.58                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                      186.90                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                       97.58                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           2.22                       # Data bus utilization in percentage
system.physmem.busUtilRead                       1.46                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.76                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.10                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        24.87                       # Average write queue length when enqueuing
system.physmem.readRowHits                     792670                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    421939                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   40.43                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  41.19                       # Row buffer hit rate for writes
system.physmem.avgGap                       224970.87                       # Average gap between requests
system.physmem.pageHitRate                      40.70                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                 6484688280                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                 3538272375                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                7379814000                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy               3249285840                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy            43875505440                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy           305078205825                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           135438254250                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             505044026010                       # Total energy per rank (pJ)
system.physmem_0.averagePower              751.831975                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   223329404750                       # Time in different power states
system.physmem_0.memoryStateTime::REF     22431240000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT    425992710250                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                 6896405880                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                 3762919875                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                7910526000                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy               3387653280                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy            43875505440                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy           312108901605                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           129270987000                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             507212899080                       # Total energy per rank (pJ)
system.physmem_1.averagePower              755.060642                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   213031369750                       # Time in different power states
system.physmem_1.memoryStateTime::REF     22431240000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT    436288612000                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu.branchPred.lookups               410738673                       # Number of BP lookups
system.cpu.branchPred.condPredicted         319032195                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect          16276977                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups            282876736                       # Number of BTB lookups
system.cpu.branchPred.BTBHits               279471264                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             98.796129                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                26377862                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect                 17                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dtb.fetch_hits                           0                       # ITB hits
system.cpu.dtb.fetch_misses                         0                       # ITB misses
system.cpu.dtb.fetch_acv                            0                       # ITB acv
system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
system.cpu.dtb.read_hits                    646528255                       # DTB read hits
system.cpu.dtb.read_misses                   12150594                       # DTB read misses
system.cpu.dtb.read_acv                             0                       # DTB read access violations
system.cpu.dtb.read_accesses                658678849                       # DTB read accesses
system.cpu.dtb.write_hits                   218209856                       # DTB write hits
system.cpu.dtb.write_misses                   7511426                       # DTB write misses
system.cpu.dtb.write_acv                            0                       # DTB write access violations
system.cpu.dtb.write_accesses               225721282                       # DTB write accesses
system.cpu.dtb.data_hits                    864738111                       # DTB hits
system.cpu.dtb.data_misses                   19662020                       # DTB misses
system.cpu.dtb.data_acv                             0                       # DTB access violations
system.cpu.dtb.data_accesses                884400131                       # DTB accesses
system.cpu.itb.fetch_hits                   422614397                       # ITB hits
system.cpu.itb.fetch_misses                        44                       # ITB misses
system.cpu.itb.fetch_acv                            0                       # ITB acv
system.cpu.itb.fetch_accesses               422614441                       # ITB accesses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.read_acv                             0                       # DTB read access violations
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.write_acv                            0                       # DTB write access violations
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.data_hits                            0                       # DTB hits
system.cpu.itb.data_misses                          0                       # DTB misses
system.cpu.itb.data_acv                             0                       # DTB access violations
system.cpu.itb.data_accesses                        0                       # DTB accesses
system.cpu.workload.num_syscalls                   29                       # Number of system calls
system.cpu.numCycles                       1343509607                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles          433913722                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                     3420789895                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                   410738673                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches          305849126                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     886512749                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                46016020                       # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles                   29                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles          1692                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles           55                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                 422614397                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes               8419525                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples         1343436257                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              2.546299                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.150257                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                716181443     53.31%     53.31% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                 48040729      3.58%     56.89% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 24412482      1.82%     58.70% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                 45272149      3.37%     62.07% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                143062816     10.65%     72.72% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                 66221905      4.93%     77.65% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                 43789018      3.26%     80.91% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                 29632862      2.21%     83.12% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                226822853     16.88%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total           1343436257                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.305721                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        2.546160                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                355607674                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles             404003493                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 525762782                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles              35055109                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles               23007199                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved             62310513                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                   875                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts             3265200378                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                  2135                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles               23007199                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                373983702                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles               211600441                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles           6939                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 538809166                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles             196028810                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts             3182220984                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents               1833786                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents               20271739                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents              149993150                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents               30859152                       # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands          2378179455                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            4128151916                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       4127979405                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups            172510                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps            1376202963                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps               1001976492                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts                195                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts            195                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  99605318                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads            719399499                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores           272964536                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads          90785513                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores         58783416                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                 2890757443                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded                 174                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                2624793649                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued           1589988                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined      1154713835                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined    506306579                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved            145                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples    1343436257                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         1.953791                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        2.147325                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           538259461     40.07%     40.07% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1           170012804     12.66%     52.72% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2           158478310     11.80%     64.52% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3           149374624     11.12%     75.64% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4           126330762      9.40%     85.04% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5            84386661      6.28%     91.32% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6            68107665      5.07%     96.39% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7            34089750      2.54%     98.93% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8            14396220      1.07%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total      1343436257                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                13176390     35.76%     35.76% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%     35.76% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     35.76% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     35.76% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     35.76% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     35.76% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     35.76% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     35.76% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     35.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     35.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     35.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     35.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     35.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     35.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     35.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     35.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     35.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     35.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     35.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     35.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     35.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     35.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     35.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     35.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     35.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     35.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     35.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     35.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     35.76% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead               19068779     51.75%     87.51% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite               4600766     12.49%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu            1719677353     65.52%     65.52% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                  114      0.00%     65.52% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     65.52% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd              897887      0.03%     65.55% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                  16      0.00%     65.55% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                 158      0.00%     65.55% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                 22      0.00%     65.55% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                  26      0.00%     65.55% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     65.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     65.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     65.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     65.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     65.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     65.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     65.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     65.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     65.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     65.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     65.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     65.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     65.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     65.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     65.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     65.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     65.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     65.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     65.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     65.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     65.55% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead            673327193     25.65%     91.20% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite           230890880      8.80%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total             2624793649                       # Type of FU issued
system.cpu.iq.rate                           1.953684                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                    36845935                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.014038                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         6629473751                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes        4044314699                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses   2522399915                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads             1985727                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes            1304235                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses       894550                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses             2660653801                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                  985783                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads         69567792                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads    274803836                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses       379517                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation       149864                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores    112236034                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads          312                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked       6300661                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles               23007199                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles               150535686                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles              19606000                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts          3042042837                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts           6687461                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts             719399499                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts            272964536                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts                174                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                 810054                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents              19058140                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents         149864                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect       10895731                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect      8841524                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts             19737255                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts            2579092054                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts             658678856                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts          45701595                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                     151285220                       # number of nop insts executed
system.cpu.iew.exec_refs                    884400225                       # number of memory reference insts executed
system.cpu.iew.exec_branches                315980786                       # Number of branches executed
system.cpu.iew.exec_stores                  225721369                       # Number of stores executed
system.cpu.iew.exec_rate                     1.919668                       # Inst execution rate
system.cpu.iew.wb_sent                     2553280591                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                    2523294465                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                1489396348                       # num instructions producing a value
system.cpu.iew.wb_consumers                1920808747                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.878137                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.775401                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts      1006176660                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls              29                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts          16276166                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples   1204408845                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.510932                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.544476                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    715098033     59.37%     59.37% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1    159881136     13.27%     72.65% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2     79829015      6.63%     79.28% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     52096588      4.33%     83.60% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4     28578407      2.37%     85.97% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5     19544658      1.62%     87.60% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6     20010855      1.66%     89.26% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7     23112076      1.92%     91.18% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8    106258077      8.82%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total   1204408845                       # Number of insts commited each cycle
system.cpu.commit.committedInsts           1819780126                       # Number of instructions committed
system.cpu.commit.committedOps             1819780126                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                      605324165                       # Number of memory references committed
system.cpu.commit.loads                     444595663                       # Number of loads committed
system.cpu.commit.membars                           0                       # Number of memory barriers committed
system.cpu.commit.branches                  214632552                       # Number of branches committed
system.cpu.commit.fp_insts                     805525                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                1718967519                       # Number of committed integer instructions.
system.cpu.commit.function_calls             16767440                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass     83736345      4.60%      4.60% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu       1129914149     62.09%     66.69% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult              75      0.00%     66.69% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv                0      0.00%     66.69% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd         805244      0.04%     66.74% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp             13      0.00%     66.74% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt            100      0.00%     66.74% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult            11      0.00%     66.74% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv             24      0.00%     66.74% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     66.74% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     66.74% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     66.74% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     66.74% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     66.74% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     66.74% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     66.74% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     66.74% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     66.74% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     66.74% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     66.74% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     66.74% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     66.74% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     66.74% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     66.74% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     66.74% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     66.74% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     66.74% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     66.74% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.74% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.74% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead       444595663     24.43%     91.17% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite      160728502      8.83%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total        1819780126                       # Class of committed instruction
system.cpu.commit.bw_lim_events             106258077                       # number cycles where commit BW limit reached
system.cpu.rob.rob_reads                   3838328354                       # The number of ROB reads
system.cpu.rob.rob_writes                  5791077348                       # The number of ROB writes
system.cpu.timesIdled                             692                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                           73350                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                  1736043781                       # Number of Instructions Simulated
system.cpu.committedOps                    1736043781                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               0.773892                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.773892                       # CPI: Total CPI of All Threads
system.cpu.ipc                               1.292171                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         1.292171                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads               3468538615                       # number of integer regfile reads
system.cpu.int_regfile_writes              2022734233                       # number of integer regfile writes
system.cpu.fp_regfile_reads                     46009                       # number of floating regfile reads
system.cpu.fp_regfile_writes                      540                       # number of floating regfile writes
system.cpu.misc_regfile_reads                      25                       # number of misc regfile reads
system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
system.cpu.dcache.tags.replacements           9208722                       # number of replacements
system.cpu.dcache.tags.tagsinuse          4087.471997                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           713777147                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           9212818                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             77.476527                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle        5130746500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data  4087.471997                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.997918                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.997918                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0          709                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1         2958                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2          425                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3            4                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses        1473023486                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses       1473023486                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data    558278644                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       558278644                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data    155498498                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total      155498498                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data            5                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total            5                       # number of LoadLockedReq hits
system.cpu.dcache.demand_hits::cpu.data     713777142                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        713777142                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    713777142                       # number of overall hits
system.cpu.dcache.overall_hits::total       713777142                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data     12898182                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total      12898182                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      5230004                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      5230004                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data            1                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total            1                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data     18128186                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total       18128186                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data     18128186                       # number of overall misses
system.cpu.dcache.overall_misses::total      18128186                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 411532558500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 411532558500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 315240579886                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 315240579886                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data        72500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total        72500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 726773138386                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 726773138386                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 726773138386                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 726773138386                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    571176826                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    571176826                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data    160728502                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total    160728502                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data            6                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total            6                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    731905328                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    731905328                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    731905328                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    731905328                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.022582                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.022582                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.032539                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.032539                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.166667                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.166667                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.024768                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.024768                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.024768                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.024768                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31906.245275                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 31906.245275                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60275.399385                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 60275.399385                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        72500                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        72500                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 40090.781195                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 40090.781195                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 40090.781195                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 40090.781195                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs     15662934                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets      9568706                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs           1102908                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets           67982                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    14.201487                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets   140.753523                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      3728522                       # number of writebacks
system.cpu.dcache.writebacks::total           3728522                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data      5564399                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total      5564399                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data      3350970                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total      3350970                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      8915369                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      8915369                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      8915369                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      8915369                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7333783                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      7333783                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1879034                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total      1879034                       # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data            1                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total            1                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      9212817                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      9212817                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      9212817                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      9212817                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 183008143000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 183008143000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  84351384400                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  84351384400                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data        71500                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total        71500                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 267359527400                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 267359527400                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 267359527400                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 267359527400                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.012840                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.012840                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.011691                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.011691                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.166667                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.166667                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.012587                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.012587                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.012587                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.012587                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24954.125722                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24954.125722                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44890.823902                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44890.823902                       # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data        71500                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total        71500                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29020.388378                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 29020.388378                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29020.388378                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 29020.388378                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements                 1                       # number of replacements
system.cpu.icache.tags.tagsinuse           774.831914                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           422612882                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs               975                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs          433449.109744                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   774.831914                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.378336                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.378336                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          974                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           64                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4          909                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.475586                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         845229769                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        845229769                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst    422612882                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       422612882                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     422612882                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        422612882                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    422612882                       # number of overall hits
system.cpu.icache.overall_hits::total       422612882                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst         1515                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total          1515                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst         1515                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total           1515                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst         1515                       # number of overall misses
system.cpu.icache.overall_misses::total          1515                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    116523500                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    116523500                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    116523500                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    116523500                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    116523500                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    116523500                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    422614397                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    422614397                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    422614397                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    422614397                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    422614397                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    422614397                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000004                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000004                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000004                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000004                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000004                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000004                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76913.201320                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 76913.201320                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 76913.201320                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 76913.201320                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 76913.201320                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 76913.201320                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs          961                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 8                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs   120.125000                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst          540                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total          540                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst          540                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total          540                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst          540                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total          540                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst          975                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total          975                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst          975                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total          975                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst          975                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total          975                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     82864500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total     82864500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst     82864500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total     82864500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst     82864500                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total     82864500                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000002                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000002                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000002                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 84989.230769                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 84989.230769                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84989.230769                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 84989.230769                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84989.230769                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 84989.230769                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements          1929005                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        31411.908280                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs           14583396                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs          1958793                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             7.445093                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle      28154888000                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 14369.814431                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst    26.748786                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 17015.345063                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.438532                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.000816                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.519267                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.958615                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        29788                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0          159                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          974                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2          615                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3        17485                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        10555                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.909058                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses        151217969                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses       151217969                       # Number of data accesses
system.cpu.l2cache.Writeback_hits::writebacks      3728522                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      3728522                       # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data      1106786                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total      1106786                       # number of ReadExReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data      6145298                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total      6145298                       # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.data      7252084                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         7252084                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.data      7252084                       # number of overall hits
system.cpu.l2cache.overall_hits::total        7252084                       # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data       772262                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       772262                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          975                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total          975                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data      1188472                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total      1188472                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst          975                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data      1960734                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total       1961709                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst          975                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data      1960734                       # number of overall misses
system.cpu.l2cache.overall_misses::total      1961709                       # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  69352569000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  69352569000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     81396500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total     81396500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 106533689500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 106533689500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst     81396500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 175886258500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 175967655000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst     81396500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 175886258500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 175967655000                       # number of overall miss cycles
system.cpu.l2cache.Writeback_accesses::writebacks      3728522                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      3728522                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data      1879048                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total      1879048                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          975                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total          975                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      7333770                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total      7333770                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst          975                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      9212818                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      9213793                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst          975                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      9212818                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      9213793                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.410986                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.410986                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst            1                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total            1                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.162055                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.162055                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst            1                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.212827                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.212910                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst            1                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.212827                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.212910                       # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89804.456260                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 89804.456260                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83483.589744                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83483.589744                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 89639.208580                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 89639.208580                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83483.589744                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89704.293647                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 89701.201860                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83483.589744                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89704.293647                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 89701.201860                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks      1024254                       # number of writebacks
system.cpu.l2cache.writebacks::total          1024254                       # number of writebacks
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          241                       # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total          241                       # number of CleanEvict MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       772262                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       772262                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          975                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total          975                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data      1188472                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total      1188472                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst          975                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data      1960734                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total      1961709                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst          975                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data      1960734                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total      1961709                       # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  61629949000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  61629949000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     71646500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     71646500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  94648969500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  94648969500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     71646500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 156278918500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 156350565000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     71646500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 156278918500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 156350565000                       # number of overall MSHR miss cycles
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.410986                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.410986                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.162055                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.162055                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.212827                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.212910                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.212827                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.212910                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79804.456260                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79804.456260                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73483.589744                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73483.589744                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79639.208580                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79639.208580                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73483.589744                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 79704.293647                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 79701.201860                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73483.589744                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 79704.293647                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79701.201860                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadResp       7334745                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback      4752776                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict      6384952                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq      1879048                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp      1879048                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq          975                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq      7333770                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1951                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     27634358                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total          27636309                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        62400                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    828245760                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          828308160                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                     1929005                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples     20351521                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        1.094784                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.292917                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1           18422516     90.52%     90.52% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2            1929005      9.48%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total       20351521                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy    12939780000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          1.9                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy       1462500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy   13819227000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          2.1                       # Layer utilization (%)
system.membus.trans_dist::ReadResp            1189447                       # Transaction distribution
system.membus.trans_dist::Writeback           1024254                       # Transaction distribution
system.membus.trans_dist::CleanEvict           903687                       # Transaction distribution
system.membus.trans_dist::ReadExReq            772262                       # Transaction distribution
system.membus.trans_dist::ReadExResp           772262                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq       1189447                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      5851359                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                5851359                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    191101632                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               191101632                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoop_fanout::samples           3889650                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                 3889650    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total             3889650                       # Request fanout histogram
system.membus.reqLayer0.occupancy          8475841500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               1.3                       # Layer utilization (%)
system.membus.respLayer1.occupancy        10684260000                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              1.6                       # Layer utilization (%)

---------- End Simulation Statistics   ----------