path: root/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.669557                       # Number of seconds simulated
sim_ticks                                669556582000                       # Number of ticks simulated
final_tick                               669556582000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 160543                       # Simulator instruction rate (inst/s)
host_op_rate                                   160543                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               61918292                       # Simulator tick rate (ticks/s)
host_mem_usage                                 299292                       # Number of bytes of host memory used
host_seconds                                 10813.55                       # Real time elapsed on the host
sim_insts                                  1736043781                       # Number of instructions simulated
sim_ops                                    1736043781                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst             60864                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data         125490304                       # Number of bytes read from this memory
system.physmem.bytes_read::total            125551168                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst        60864                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           60864                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     65555584                       # Number of bytes written to this memory
system.physmem.bytes_written::total          65555584                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst                951                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data            1960786                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               1961737                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1024306                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1024306                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst                90902                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data            187423001                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total               187513903                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst           90902                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total              90902                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks          97908953                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total               97908953                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks          97908953                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst               90902                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data           187423001                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              285422856                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                       1961737                       # Number of read requests accepted
system.physmem.writeReqs                      1024306                       # Number of write requests accepted
system.physmem.readBursts                     1961737                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                    1024306                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                125467392                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     83776                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  65553984                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                 125551168                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               65555584                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                     1309                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0              118679                       # Per bank write bursts
system.physmem.perBankRdBursts::1              113901                       # Per bank write bursts
system.physmem.perBankRdBursts::2              116111                       # Per bank write bursts
system.physmem.perBankRdBursts::3              117641                       # Per bank write bursts
system.physmem.perBankRdBursts::4              117753                       # Per bank write bursts
system.physmem.perBankRdBursts::5              117515                       # Per bank write bursts
system.physmem.perBankRdBursts::6              119854                       # Per bank write bursts
system.physmem.perBankRdBursts::7              124644                       # Per bank write bursts
system.physmem.perBankRdBursts::8              127345                       # Per bank write bursts
system.physmem.perBankRdBursts::9              130108                       # Per bank write bursts
system.physmem.perBankRdBursts::10             128796                       # Per bank write bursts
system.physmem.perBankRdBursts::11             130507                       # Per bank write bursts
system.physmem.perBankRdBursts::12             126297                       # Per bank write bursts
system.physmem.perBankRdBursts::13             125432                       # Per bank write bursts
system.physmem.perBankRdBursts::14             122623                       # Per bank write bursts
system.physmem.perBankRdBursts::15             123222                       # Per bank write bursts
system.physmem.perBankWrBursts::0               61508                       # Per bank write bursts
system.physmem.perBankWrBursts::1               61766                       # Per bank write bursts
system.physmem.perBankWrBursts::2               60825                       # Per bank write bursts
system.physmem.perBankWrBursts::3               61511                       # Per bank write bursts
system.physmem.perBankWrBursts::4               61967                       # Per bank write bursts
system.physmem.perBankWrBursts::5               63434                       # Per bank write bursts
system.physmem.perBankWrBursts::6               64481                       # Per bank write bursts
system.physmem.perBankWrBursts::7               65996                       # Per bank write bursts
system.physmem.perBankWrBursts::8               65770                       # Per bank write bursts
system.physmem.perBankWrBursts::9               66159                       # Per bank write bursts
system.physmem.perBankWrBursts::10              65809                       # Per bank write bursts
system.physmem.perBankWrBursts::11              66083                       # Per bank write bursts
system.physmem.perBankWrBursts::12              64701                       # Per bank write bursts
system.physmem.perBankWrBursts::13              64659                       # Per bank write bursts
system.physmem.perBankWrBursts::14              65023                       # Per bank write bursts
system.physmem.perBankWrBursts::15              64589                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    669556486500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                 1961737                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                1024306                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                   1618471                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    241016                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     69944                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                     30981                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                        15                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    26250                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    27792                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    49335                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    56790                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    59383                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    60583                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    61041                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    61153                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    61320                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    61428                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    61507                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    61573                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    62350                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    63649                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    65159                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    62772                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    61732                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                    60239                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      166                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                       46                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                       18                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        3                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples      1769592                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      107.945804                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean      82.951779                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     137.536097                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127        1374979     77.70%     77.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255       270914     15.31%     93.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        53662      3.03%     96.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511        21295      1.20%     97.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639        12785      0.72%     97.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         6489      0.37%     98.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         4949      0.28%     98.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         3948      0.22%     98.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        20571      1.16%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total        1769592                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         60107                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        32.574625                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      148.683386                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-511           59945     99.73%     99.73% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::512-1023          118      0.20%     99.93% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-1535           10      0.02%     99.94% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1536-2047            6      0.01%     99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-2559            8      0.01%     99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2560-3071            5      0.01%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::3072-3583            3      0.00%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::3584-4095            1      0.00%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::4096-4607            1      0.00%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::4608-5119            3      0.00%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::6656-7167            1      0.00%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::8192-8703            1      0.00%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::9216-9727            1      0.00%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::10240-10751            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::11776-12287            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::14848-15359            2      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           60107                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         60107                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        17.040960                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       16.998792                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        1.235687                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16              31915     53.10%     53.10% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17               1364      2.27%     55.37% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18              21027     34.98%     90.35% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19               4732      7.87%     98.22% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20                816      1.36%     99.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21                161      0.27%     99.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22                 44      0.07%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23                 14      0.02%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24                  8      0.01%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::25                  1      0.00%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26                  3      0.00%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::27                  3      0.00%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28                  1      0.00%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32                  3      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::33                  1      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::34                  2      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::35                  1      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36                  1      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::37                  1      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::38                  4      0.01%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::39                  1      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40                  1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::41                  2      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::46                  1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           60107                       # Writes before turning the bus around for reads
system.physmem.totQLat                    40555708000                       # Total ticks spent queuing
system.physmem.totMemAccLat               77313733000                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   9802140000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       20687.17                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  39437.17                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                         187.39                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                          97.91                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                      187.51                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                       97.91                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           2.23                       # Data bus utilization in percentage
system.physmem.busUtilRead                       1.46                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.76                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.10                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        24.98                       # Average write queue length when enqueuing
system.physmem.readRowHits                     792895                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    422217                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   40.44                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  41.22                       # Row buffer hit rate for writes
system.physmem.avgGap                       224228.68                       # Average gap between requests
system.physmem.pageHitRate                      40.71                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                 6483387960                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                 3537562875                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                7379541000                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy               3249642240                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy            43732091520                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy           304280359155                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           134820686250                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             503483271000                       # Total energy per rank (pJ)
system.physmem_0.averagePower              751.966482                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   222309059500                       # Time in different power states
system.physmem_0.memoryStateTime::REF     22357920000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT    424888778500                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                 6894704880                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                 3761991750                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                7911610200                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy               3387698640                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy            43732091520                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy           311328000180                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           128638545000                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             505654642170                       # Total energy per rank (pJ)
system.physmem_1.averagePower              755.209486                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   211980924500                       # Time in different power states
system.physmem_1.memoryStateTime::REF     22357920000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT    435216639250                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu.branchPred.lookups               409355418                       # Number of BP lookups
system.cpu.branchPred.condPredicted         318166975                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect          15963047                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups            282312141                       # Number of BTB lookups
system.cpu.branchPred.BTBHits               278580615                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             98.678227                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                26172204                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect                 20                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dtb.fetch_hits                           0                       # ITB hits
system.cpu.dtb.fetch_misses                         0                       # ITB misses
system.cpu.dtb.fetch_acv                            0                       # ITB acv
system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
system.cpu.dtb.read_hits                    644928587                       # DTB read hits
system.cpu.dtb.read_misses                   12158902                       # DTB read misses
system.cpu.dtb.read_acv                             0                       # DTB read access violations
system.cpu.dtb.read_accesses                657087489                       # DTB read accesses
system.cpu.dtb.write_hits                   218092717                       # DTB write hits
system.cpu.dtb.write_misses                   7512154                       # DTB write misses
system.cpu.dtb.write_acv                            0                       # DTB write access violations
system.cpu.dtb.write_accesses               225604871                       # DTB write accesses
system.cpu.dtb.data_hits                    863021304                       # DTB hits
system.cpu.dtb.data_misses                   19671056                       # DTB misses
system.cpu.dtb.data_acv                             0                       # DTB access violations
system.cpu.dtb.data_accesses                882692360                       # DTB accesses
system.cpu.itb.fetch_hits                   420625120                       # ITB hits
system.cpu.itb.fetch_misses                        37                       # ITB misses
system.cpu.itb.fetch_acv                            0                       # ITB acv
system.cpu.itb.fetch_accesses               420625157                       # ITB accesses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.read_acv                             0                       # DTB read access violations
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.write_acv                            0                       # DTB write access violations
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.data_hits                            0                       # DTB hits
system.cpu.itb.data_misses                          0                       # DTB misses
system.cpu.itb.data_acv                             0                       # DTB access violations
system.cpu.itb.data_accesses                        0                       # DTB accesses
system.cpu.workload.num_syscalls                   29                       # Number of system calls
system.cpu.numCycles                       1339113165                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles          431760554                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                     3410003764                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                   409355418                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches          304752819                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     884588278                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                45380492                       # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles                   25                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles          1660                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles           27                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                 420625120                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes               8288982                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples         1339040790                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              2.546602                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.150665                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                714026661     53.32%     53.32% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                 47659433      3.56%     56.88% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 24224234      1.81%     58.69% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                 45105968      3.37%     62.06% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                142792146     10.66%     72.72% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                 65943853      4.92%     77.65% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                 43594254      3.26%     80.90% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                 29429342      2.20%     83.10% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                226264899     16.90%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total           1339040790                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.305691                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        2.546464                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                353769612                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles             403558275                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 524215531                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles              34807834                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles               22689538                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved             62027781                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                   752                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts             3256129377                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                  2069                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles               22689538                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                372008249                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles               212535269                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles           7646                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 537155328                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles             194644760                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts             3173788478                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents               1809495                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents               20462310                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents              148566154                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents               30882701                       # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands          2371842618                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            4117718959                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       4117582524                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups            136434                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps            1376202963                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                995639655                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts                143                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts            142                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  99637264                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads            717251547                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores           272457871                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads          90453848                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores         58428187                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                 2884203449                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded                 122                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                2620051581                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued           1544935                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined      1148159789                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined    502731368                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved             93                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples    1339040790                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         1.956663                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        2.148213                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           535540081     39.99%     39.99% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1           169652118     12.67%     52.66% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2           157969981     11.80%     64.46% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3           149186997     11.14%     75.60% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4           125999252      9.41%     85.01% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5            84166081      6.29%     91.30% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6            68019052      5.08%     96.38% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7            34101039      2.55%     98.92% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8            14406189      1.08%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total      1339040790                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                13157777     35.84%     35.84% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%     35.84% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     35.84% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     35.84% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     35.84% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     35.84% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     35.84% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     35.84% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     35.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     35.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     35.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     35.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     35.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     35.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     35.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     35.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     35.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     35.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     35.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     35.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     35.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     35.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     35.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     35.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     35.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     35.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     35.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     35.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     35.84% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead               18965028     51.65%     87.49% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite               4592425     12.51%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu            1716938805     65.53%     65.53% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                  113      0.00%     65.53% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     65.53% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd              896154      0.03%     65.56% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                  19      0.00%     65.56% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                 163      0.00%     65.56% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                 30      0.00%     65.56% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                  26      0.00%     65.56% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     65.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     65.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     65.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     65.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     65.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     65.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     65.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     65.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     65.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     65.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     65.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     65.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     65.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     65.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     65.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     65.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     65.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     65.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     65.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     65.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     65.56% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead            671533572     25.63%     91.20% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite           230682699      8.80%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total             2620051581                       # Type of FU issued
system.cpu.iq.rate                           1.956557                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                    36715230                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.014013                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         6615464746                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes        4031257680                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses   2518620612                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads             1939371                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes            1248863                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses       886699                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses             2655799836                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                  966975                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads         69396280                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads    272655884                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses       373351                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation       145486                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores    111729369                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads          229                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked       6306976                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles               22689538                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles               149806110                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles              21267531                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts          3035207367                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts           6595956                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts             717251547                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts            272457871                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts                122                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                 801675                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents              20722786                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents         145486                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect       10633585                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect      8701131                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts             19334716                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts            2574896999                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts             657087498                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts          45154582                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                     151003796                       # number of nop insts executed
system.cpu.iew.exec_refs                    882692437                       # number of memory reference insts executed
system.cpu.iew.exec_branches                315488895                       # Number of branches executed
system.cpu.iew.exec_stores                  225604939                       # Number of stores executed
system.cpu.iew.exec_rate                     1.922837                       # Inst execution rate
system.cpu.iew.wb_sent                     2549331117                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                    2519507311                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                1487495376                       # num instructions producing a value
system.cpu.iew.wb_consumers                1918378348                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.881475                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.775392                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts       998666714                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls              29                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts          15962339                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples   1201055691                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.515150                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.548433                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    712334289     59.31%     59.31% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1    159635442     13.29%     72.60% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2     79514551      6.62%     79.22% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     52029279      4.33%     83.55% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4     28475742      2.37%     85.92% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5     19476450      1.62%     87.55% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6     19964545      1.66%     89.21% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7     23047887      1.92%     91.13% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8    106577506      8.87%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total   1201055691                       # Number of insts commited each cycle
system.cpu.commit.committedInsts           1819780126                       # Number of instructions committed
system.cpu.commit.committedOps             1819780126                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                      605324165                       # Number of memory references committed
system.cpu.commit.loads                     444595663                       # Number of loads committed
system.cpu.commit.membars                           0                       # Number of memory barriers committed
system.cpu.commit.branches                  214632552                       # Number of branches committed
system.cpu.commit.fp_insts                     805525                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                1718967519                       # Number of committed integer instructions.
system.cpu.commit.function_calls             16767440                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass     83736345      4.60%      4.60% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu       1129914149     62.09%     66.69% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult              75      0.00%     66.69% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv                0      0.00%     66.69% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd         805244      0.04%     66.74% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp             13      0.00%     66.74% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt            100      0.00%     66.74% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult            11      0.00%     66.74% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv             24      0.00%     66.74% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     66.74% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     66.74% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     66.74% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     66.74% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     66.74% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     66.74% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     66.74% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     66.74% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     66.74% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     66.74% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     66.74% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     66.74% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     66.74% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     66.74% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     66.74% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     66.74% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     66.74% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     66.74% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     66.74% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.74% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.74% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead       444595663     24.43%     91.17% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite      160728502      8.83%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total        1819780126                       # Class of committed instruction
system.cpu.commit.bw_lim_events             106577506                       # number cycles where commit BW limit reached
system.cpu.rob.rob_reads                   3827145825                       # The number of ROB reads
system.cpu.rob.rob_writes                  5775013033                       # The number of ROB writes
system.cpu.timesIdled                             710                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                           72375                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                  1736043781                       # Number of Instructions Simulated
system.cpu.committedOps                    1736043781                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               0.771359                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.771359                       # CPI: Total CPI of All Threads
system.cpu.ipc                               1.296413                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         1.296413                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads               3463596666                       # number of integer regfile reads
system.cpu.int_regfile_writes              2019349968                       # number of integer regfile writes
system.cpu.fp_regfile_reads                     39643                       # number of floating regfile reads
system.cpu.fp_regfile_writes                      588                       # number of floating regfile writes
system.cpu.misc_regfile_reads                      25                       # number of misc regfile reads
system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
system.cpu.dcache.tags.replacements           9207223                       # number of replacements
system.cpu.dcache.tags.tagsinuse          4087.441459                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           712346742                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           9211319                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             77.333848                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle        5127954500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data  4087.441459                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.997911                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.997911                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0          707                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1         2960                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2          425                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3            4                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses        1470153653                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses       1470153653                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data    556848599                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       556848599                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data    155498140                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total      155498140                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data            3                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total            3                       # number of LoadLockedReq hits
system.cpu.dcache.demand_hits::cpu.data     712346739                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        712346739                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    712346739                       # number of overall hits
system.cpu.dcache.overall_hits::total       712346739                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data     12894062                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total      12894062                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      5230362                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      5230362                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data            1                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total            1                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data     18124424                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total       18124424                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data     18124424                       # number of overall misses
system.cpu.dcache.overall_misses::total      18124424                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 412011773000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 412011773000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 315105865697                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 315105865697                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data        72500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total        72500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 727117638697                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 727117638697                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 727117638697                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 727117638697                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    569742661                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    569742661                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data    160728502                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total    160728502                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data            4                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total            4                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    730471163                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    730471163                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    730471163                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    730471163                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.022631                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.022631                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.032542                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.032542                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.250000                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.250000                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.024812                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.024812                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.024812                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.024812                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31953.605698                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 31953.605698                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60245.517556                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 60245.517556                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        72500                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        72500                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 40118.110164                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 40118.110164                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 40118.110164                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 40118.110164                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs     15661523                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets      9569226                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs           1103711                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets           68026                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    14.189877                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets   140.670126                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      3727748                       # number of writebacks
system.cpu.dcache.writebacks::total           3727748                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data      5561934                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total      5561934                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data      3351172                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total      3351172                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      8913106                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      8913106                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      8913106                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      8913106                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7332128                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      7332128                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1879190                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total      1879190                       # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data            1                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total            1                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      9211318                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      9211318                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      9211318                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      9211318                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 182959853500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 182959853500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  84331903655                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  84331903655                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data        71500                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total        71500                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 267291757155                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 267291757155                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 267291757155                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 267291757155                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.012869                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.012869                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.011692                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.011692                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.250000                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.250000                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.012610                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.012610                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.012610                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.012610                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24953.172326                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24953.172326                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44876.730748                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44876.730748                       # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data        71500                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total        71500                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29017.753719                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 29017.753719                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29017.753719                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 29017.753719                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements                 1                       # number of replacements
system.cpu.icache.tags.tagsinuse           755.106219                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           420623640                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs               951                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs          442296.151420                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   755.106219                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.368704                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.368704                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          950                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           64                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4          886                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.463867                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         841251191                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        841251191                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst    420623640                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       420623640                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     420623640                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        420623640                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    420623640                       # number of overall hits
system.cpu.icache.overall_hits::total       420623640                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst         1480                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total          1480                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst         1480                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total           1480                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst         1480                       # number of overall misses
system.cpu.icache.overall_misses::total          1480                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    114807500                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    114807500                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    114807500                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    114807500                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    114807500                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    114807500                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    420625120                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    420625120                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    420625120                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    420625120                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    420625120                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    420625120                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000004                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000004                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000004                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000004                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000004                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000004                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77572.635135                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 77572.635135                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 77572.635135                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 77572.635135                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 77572.635135                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 77572.635135                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs          288                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 5                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    57.600000                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst          529                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total          529                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst          529                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total          529                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst          529                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total          529                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst          951                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total          951                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst          951                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total          951                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst          951                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total          951                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     79672000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total     79672000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst     79672000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total     79672000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst     79672000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total     79672000                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000002                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000002                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000002                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83777.076761                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83777.076761                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83777.076761                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 83777.076761                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83777.076761                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 83777.076761                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements          1929031                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        31408.547403                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs           14580190                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs          1958818                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             7.443361                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle      28140218000                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 14352.760847                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst    25.833600                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 17029.952956                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.438012                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.000788                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.519713                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.958513                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        29787                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0          156                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          975                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2          615                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3        17547                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        10494                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.909027                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses        151193976                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses       151193976                       # Number of data accesses
system.cpu.l2cache.Writeback_hits::writebacks      3727748                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      3727748                       # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data      1106790                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total      1106790                       # number of ReadExReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data      6143743                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total      6143743                       # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.data      7250533                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         7250533                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.data      7250533                       # number of overall hits
system.cpu.l2cache.overall_hits::total        7250533                       # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data       772416                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       772416                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          951                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total          951                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data      1188370                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total      1188370                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst          951                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data      1960786                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total       1961737                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst          951                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data      1960786                       # number of overall misses
system.cpu.l2cache.overall_misses::total      1961737                       # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  69332440500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  69332440500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     78240000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total     78240000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 106503228500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 106503228500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst     78240000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 175835669000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 175913909000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst     78240000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 175835669000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 175913909000                       # number of overall miss cycles
system.cpu.l2cache.Writeback_accesses::writebacks      3727748                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      3727748                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data      1879206                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total      1879206                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          951                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total          951                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      7332113                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total      7332113                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst          951                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      9211319                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      9212270                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst          951                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      9211319                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      9212270                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.411033                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.411033                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst            1                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total            1                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.162077                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.162077                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst            1                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.212867                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.212948                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst            1                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.212867                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.212948                       # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89760.492403                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 89760.492403                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82271.293375                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82271.293375                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 89621.269891                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 89621.269891                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82271.293375                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89676.114069                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 89672.524401                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82271.293375                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89676.114069                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 89672.524401                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks      1024306                       # number of writebacks
system.cpu.l2cache.writebacks::total          1024306                       # number of writebacks
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          241                       # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total          241                       # number of CleanEvict MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       772416                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       772416                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          951                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total          951                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data      1188370                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total      1188370                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst          951                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data      1960786                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total      1961737                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst          951                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data      1960786                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total      1961737                       # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  61608280500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  61608280500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     68730000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     68730000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  94619528500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  94619528500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     68730000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 156227809000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 156296539000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     68730000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 156227809000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 156296539000                       # number of overall MSHR miss cycles
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.411033                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.411033                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.162077                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.162077                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.212867                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.212948                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.212867                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.212948                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79760.492403                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79760.492403                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72271.293375                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72271.293375                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79621.269891                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79621.269891                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72271.293375                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 79676.114069                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 79672.524401                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72271.293375                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 79676.114069                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79672.524401                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.snoop_filter.tot_requests     18419494                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests      9207224                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops         1279                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1279                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp       7333064                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback      4752054                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict      6384201                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq      1879206                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp      1879206                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq          951                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq      7332113                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1903                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     27629861                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total          27631764                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        60864                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    828100288                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          828161152                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                     1929031                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples     20348525                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        0.000063                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.007928                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0           20347246     99.99%     99.99% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1               1279      0.01%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total       20348525                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy    12937495000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          1.9                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy       1426500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy   13816978500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          2.1                       # Layer utilization (%)
system.membus.trans_dist::ReadResp            1189321                       # Transaction distribution
system.membus.trans_dist::Writeback           1024306                       # Transaction distribution
system.membus.trans_dist::CleanEvict           903687                       # Transaction distribution
system.membus.trans_dist::ReadExReq            772416                       # Transaction distribution
system.membus.trans_dist::ReadExResp           772416                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq       1189321                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      5851467                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                5851467                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    191106752                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               191106752                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoop_fanout::samples           3889730                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                 3889730    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total             3889730                       # Request fanout histogram
system.membus.reqLayer0.occupancy          8475633500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               1.3                       # Layer utilization (%)
system.membus.respLayer1.occupancy        10684578250                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              1.6                       # Layer utilization (%)

---------- End Simulation Statistics   ----------