path: root/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  1.095875                       # Number of seconds simulated
sim_ticks                                1095875470500                       # Number of ticks simulated
final_tick                               1095875470500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 232088                       # Simulator instruction rate (inst/s)
host_op_rate                                   250040                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                              164667871                       # Simulator tick rate (ticks/s)
host_mem_usage                                 318056                       # Number of bytes of host memory used
host_seconds                                  6655.07                       # Real time elapsed on the host
sim_insts                                  1544563087                       # Number of instructions simulated
sim_ops                                    1664032480                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst         131539072                       # Number of bytes read from this memory
system.physmem.bytes_read::total            131539072                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst        50432                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           50432                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     66963456                       # Number of bytes written to this memory
system.physmem.bytes_written::total          66963456                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst            2055298                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               2055298                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1046304                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1046304                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst            120031040                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total               120031040                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst           46020                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total              46020                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks          61104987                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total               61104987                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks          61104987                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst           120031040                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              181136026                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                       2055298                       # Number of read requests accepted
system.physmem.writeReqs                      1046304                       # Number of write requests accepted
system.physmem.readBursts                     2055298                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                    1046304                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                131453056                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     86016                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  66961856                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                 131539072                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               66963456                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                     1344                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0              127944                       # Per bank write bursts
system.physmem.perBankRdBursts::1              125151                       # Per bank write bursts
system.physmem.perBankRdBursts::2              122313                       # Per bank write bursts
system.physmem.perBankRdBursts::3              124176                       # Per bank write bursts
system.physmem.perBankRdBursts::4              123203                       # Per bank write bursts
system.physmem.perBankRdBursts::5              123365                       # Per bank write bursts
system.physmem.perBankRdBursts::6              123797                       # Per bank write bursts
system.physmem.perBankRdBursts::7              124247                       # Per bank write bursts
system.physmem.perBankRdBursts::8              131879                       # Per bank write bursts
system.physmem.perBankRdBursts::9              134089                       # Per bank write bursts
system.physmem.perBankRdBursts::10             132451                       # Per bank write bursts
system.physmem.perBankRdBursts::11             133680                       # Per bank write bursts
system.physmem.perBankRdBursts::12             133764                       # Per bank write bursts
system.physmem.perBankRdBursts::13             133810                       # Per bank write bursts
system.physmem.perBankRdBursts::14             129795                       # Per bank write bursts
system.physmem.perBankRdBursts::15             130290                       # Per bank write bursts
system.physmem.perBankWrBursts::0               65788                       # Per bank write bursts
system.physmem.perBankWrBursts::1               64108                       # Per bank write bursts
system.physmem.perBankWrBursts::2               62418                       # Per bank write bursts
system.physmem.perBankWrBursts::3               62855                       # Per bank write bursts
system.physmem.perBankWrBursts::4               62808                       # Per bank write bursts
system.physmem.perBankWrBursts::5               62982                       # Per bank write bursts
system.physmem.perBankWrBursts::6               64271                       # Per bank write bursts
system.physmem.perBankWrBursts::7               65268                       # Per bank write bursts
system.physmem.perBankWrBursts::8               67081                       # Per bank write bursts
system.physmem.perBankWrBursts::9               67609                       # Per bank write bursts
system.physmem.perBankWrBursts::10              67274                       # Per bank write bursts
system.physmem.perBankWrBursts::11              67626                       # Per bank write bursts
system.physmem.perBankWrBursts::12              67000                       # Per bank write bursts
system.physmem.perBankWrBursts::13              67431                       # Per bank write bursts
system.physmem.perBankWrBursts::14              66125                       # Per bank write bursts
system.physmem.perBankWrBursts::15              65635                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    1095875382500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                 2055298                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                1046304                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                   1922424                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    131512                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                        18                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    33528                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    34841                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    57203                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    60757                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    61403                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    61327                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    61251                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    61258                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    61259                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    61367                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    61289                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    61334                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    62306                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    61683                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    61440                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    62194                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    60945                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                    60798                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                       90                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                       13                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        3                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples      1911965                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      103.774418                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean      81.877172                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     125.825249                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127        1485376     77.69%     77.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255       306998     16.06%     93.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        52789      2.76%     96.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511        21060      1.10%     97.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639        13283      0.69%     98.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         6873      0.36%     98.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         5659      0.30%     98.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         4134      0.22%     99.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        15793      0.83%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total        1911965                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         60795                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        33.737117                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      161.571664                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023          60754     99.93%     99.93% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047           14      0.02%     99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-3071           14      0.02%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::3072-4095            5      0.01%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::4096-5119            3      0.00%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::9216-10239            1      0.00%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::12288-13311            2      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::14336-15359            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::22528-23551            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           60795                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         60795                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        17.209951                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       17.175292                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        1.091996                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16              25805     42.45%     42.45% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17               1192      1.96%     44.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18              29551     48.61%     93.01% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19               3811      6.27%     99.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20                363      0.60%     99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21                 60      0.10%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22                 11      0.02%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23                  2      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           60795                       # Writes before turning the bus around for reads
system.physmem.totQLat                    38124649000                       # Total ticks spent queuing
system.physmem.totMemAccLat               76636286500                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                  10269770000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       18561.59                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  37311.59                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                         119.95                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                          61.10                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                      120.03                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                       61.10                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           1.41                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.94                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.48                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        24.69                       # Average write queue length when enqueuing
system.physmem.readRowHits                     779774                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    408484                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   37.96                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  39.04                       # Row buffer hit rate for writes
system.physmem.avgGap                       353325.60                       # Average gap between requests
system.physmem.pageHitRate                      38.33                       # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE     306310282500                       # Time in different power states
system.physmem.memoryStateTime::REF       36593440000                       # Time in different power states
system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
system.physmem.memoryStateTime::ACT      752968660500                       # Time in different power states
system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
system.membus.throughput                    181136026                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq             1255348                       # Transaction distribution
system.membus.trans_dist::ReadResp            1255348                       # Transaction distribution
system.membus.trans_dist::Writeback           1046304                       # Transaction distribution
system.membus.trans_dist::ReadExReq            799950                       # Transaction distribution
system.membus.trans_dist::ReadExResp           799950                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      5156900                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                5156900                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    198502528                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total           198502528                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus              198502528                       # Total data (bytes)
system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy         12227667000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               1.1                       # Layer utilization (%)
system.membus.respLayer1.occupancy        19360882250                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              1.8                       # Layer utilization (%)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.branchPred.lookups               239641872                       # Number of BP lookups
system.cpu.branchPred.condPredicted         186303374                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect          14594643                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups            130836287                       # Number of BTB lookups
system.cpu.branchPred.BTBHits               121989290                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             93.238117                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                15653729                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect                 15                       # Number of incorrect RAS predictions.
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                   46                       # Number of system calls
system.cpu.numCycles                       2191750941                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                  1544563087                       # Number of instructions committed
system.cpu.committedOps                    1664032480                       # Number of ops (including micro ops) committed
system.cpu.discardedOps                      42066132                       # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
system.cpu.cpi                               1.419010                       # CPI: cycles per instruction
system.cpu.ipc                               0.704717                       # IPC: instructions per cycle
system.cpu.tickCycles                      1808188284                       # Number of cycles that the object actually ticked
system.cpu.idleCycles                       383562657                       # Total number of cycles that the object has spent stopped
system.cpu.icache.tags.replacements                29                       # number of replacements
system.cpu.icache.tags.tagsinuse           661.141376                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           464847257                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs               820                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs          566886.898780                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   661.141376                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.322823                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.322823                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          791                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           32                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2            5                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4          754                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.386230                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         929696974                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        929696974                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst    464847257                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       464847257                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     464847257                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        464847257                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    464847257                       # number of overall hits
system.cpu.icache.overall_hits::total       464847257                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst          820                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total           820                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst          820                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total            820                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst          820                       # number of overall misses
system.cpu.icache.overall_misses::total           820                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst     58324499                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total     58324499                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst     58324499                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total     58324499                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst     58324499                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total     58324499                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    464848077                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    464848077                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    464848077                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    464848077                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    464848077                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    464848077                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000002                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000002                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000002                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000002                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000002                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000002                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71127.437805                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 71127.437805                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 71127.437805                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 71127.437805                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 71127.437805                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 71127.437805                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst          820                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total          820                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst          820                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total          820                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst          820                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total          820                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     56360501                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total     56360501                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst     56360501                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total     56360501                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst     56360501                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total     56360501                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000002                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000002                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000002                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68732.318293                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68732.318293                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68732.318293                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 68732.318293                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68732.318293                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 68732.318293                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.throughput               755014954                       # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq        7336391                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       7336391                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback      3700895                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq      1890876                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp      1890876                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1640                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     22153789                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total          22155429                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        52480                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    827349888                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total      827402368                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus         827402368                       # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy    10164976000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.9                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy       1391999                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy   14185372245                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          1.3                       # Layer utilization (%)
system.cpu.l2cache.tags.replacements          2022594                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        31252.258926                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            8984184                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs          2052369                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             4.377470                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle      58953869250                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 14968.183746                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 16284.075180                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.456793                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.496951                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.953743                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        29775                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           91                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1           31                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1248                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3        12849                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        15556                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.908661                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses        107368541                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses       107368541                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst      6081037                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        6081037                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks      3700895                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      3700895                       # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.inst      1090926                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total      1090926                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst      7171963                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         7171963                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst      7171963                       # number of overall hits
system.cpu.l2cache.overall_hits::total        7171963                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst      1255354                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total      1255354                       # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.inst       799950                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       799950                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst      2055304                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total       2055304                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst      2055304                       # number of overall misses
system.cpu.l2cache.overall_misses::total      2055304                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 100122250500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 100122250500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst  64358555750                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  64358555750                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 164480806250                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 164480806250                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 164480806250                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 164480806250                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst      7336391                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      7336391                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks      3700895                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      3700895                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.inst      1890876                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total      1890876                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst      9227267                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      9227267                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst      9227267                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      9227267                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.171113                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.171113                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.423058                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.423058                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.222742                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.222742                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.222742                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.222742                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79756.188693                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 79756.188693                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 80453.223014                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80453.223014                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80027.483161                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 80027.483161                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80027.483161                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 80027.483161                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks      1046304                       # number of writebacks
system.cpu.l2cache.writebacks::total          1046304                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            6                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total            6                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            6                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total            6                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            6                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total            6                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst      1255348                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total      1255348                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst       799950                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       799950                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst      2055298                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total      2055298                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst      2055298                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total      2055298                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst  84333554000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total  84333554000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst  54273221250                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  54273221250                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 138606775250                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 138606775250                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 138606775250                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 138606775250                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.171112                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.171112                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.423058                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.423058                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.222742                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.222742                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.222742                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.222742                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67179.422758                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67179.422758                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 67845.766923                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67845.766923                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67438.772991                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67438.772991                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67438.772991                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67438.772991                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements           9222351                       # number of replacements
system.cpu.dcache.tags.tagsinuse          4085.559894                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           624001258                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           9226447                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             67.631804                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle        9703664000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.inst  4085.559894                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.inst     0.997451                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.997451                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0          283                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1         1314                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2         2438                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3           61                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses        1276381727                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses       1276381727                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.inst    453655688                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       453655688                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.inst    170345448                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total      170345448                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.inst           61                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total           61                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.inst           61                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total           61                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.inst     624001136                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        624001136                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.inst    624001136                       # number of overall hits
system.cpu.dcache.overall_hits::total       624001136                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.inst      7335783                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       7335783                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.inst      2240599                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      2240599                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.inst      9576382                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        9576382                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.inst      9576382                       # number of overall misses
system.cpu.dcache.overall_misses::total       9576382                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.inst 183307188995                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 183307188995                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.inst 101248592250                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 101248592250                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.inst 284555781245                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 284555781245                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.inst 284555781245                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 284555781245                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.inst    460991471                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    460991471                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.inst    172586047                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total    172586047                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.inst           61                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total           61                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.inst           61                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total           61                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.inst    633577518                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    633577518                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.inst    633577518                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    633577518                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.015913                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.015913                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.012983                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.012983                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.inst     0.015115                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.015115                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.inst     0.015115                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.015115                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 24988.087706                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 24988.087706                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 45188.180594                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 45188.180594                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29714.330657                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 29714.330657                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29714.330657                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 29714.330657                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      3700895                       # number of writebacks
system.cpu.dcache.writebacks::total           3700895                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.inst          212                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total          212                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.inst       349723                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total       349723                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.inst       349935                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total       349935                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.inst       349935                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total       349935                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.inst      7335571                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      7335571                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.inst      1890876                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total      1890876                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.inst      9226447                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      9226447                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.inst      9226447                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      9226447                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 168217924005                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 168217924005                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst  77187221250                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  77187221250                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 245405145255                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 245405145255                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 245405145255                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 245405145255                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.015913                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.015913                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.010956                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.010956                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.014562                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.014562                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.014562                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.014562                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 22931.810490                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22931.810490                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 40820.879450                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40820.879450                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26598.011700                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 26598.011700                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26598.011700                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 26598.011700                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------