path: root/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  1.108725                       # Number of seconds simulated
sim_ticks                                1108725388000                       # Number of ticks simulated
final_tick                               1108725388000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 160331                       # Simulator instruction rate (inst/s)
host_op_rate                                   172733                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                              115089854                       # Simulator tick rate (ticks/s)
host_mem_usage                                 301444                       # Number of bytes of host memory used
host_seconds                                  9633.56                       # Real time elapsed on the host
sim_insts                                  1544563087                       # Number of instructions simulated
sim_ops                                    1664032480                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst             50368                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data         131507968                       # Number of bytes read from this memory
system.physmem.bytes_read::total            131558336                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst        50368                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           50368                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     66970688                       # Number of bytes written to this memory
system.physmem.bytes_written::total          66970688                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst                787                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data            2054812                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               2055599                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1046417                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1046417                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst                45429                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data            118611849                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total               118657277                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst           45429                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total              45429                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks          60403314                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total               60403314                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks          60403314                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst               45429                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data           118611849                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              179060592                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                       2055599                       # Number of read requests accepted
system.physmem.writeReqs                      1046417                       # Number of write requests accepted
system.physmem.readBursts                     2055599                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                    1046417                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                131472320                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     86016                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  66969088                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                 131558336                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               66970688                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                     1344                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0              127971                       # Per bank write bursts
system.physmem.perBankRdBursts::1              125115                       # Per bank write bursts
system.physmem.perBankRdBursts::2              122192                       # Per bank write bursts
system.physmem.perBankRdBursts::3              124223                       # Per bank write bursts
system.physmem.perBankRdBursts::4              123351                       # Per bank write bursts
system.physmem.perBankRdBursts::5              123340                       # Per bank write bursts
system.physmem.perBankRdBursts::6              123758                       # Per bank write bursts
system.physmem.perBankRdBursts::7              124120                       # Per bank write bursts
system.physmem.perBankRdBursts::8              131994                       # Per bank write bursts
system.physmem.perBankRdBursts::9              134060                       # Per bank write bursts
system.physmem.perBankRdBursts::10             132574                       # Per bank write bursts
system.physmem.perBankRdBursts::11             133683                       # Per bank write bursts
system.physmem.perBankRdBursts::12             133864                       # Per bank write bursts
system.physmem.perBankRdBursts::13             133891                       # Per bank write bursts
system.physmem.perBankRdBursts::14             129793                       # Per bank write bursts
system.physmem.perBankRdBursts::15             130326                       # Per bank write bursts
system.physmem.perBankWrBursts::0               65785                       # Per bank write bursts
system.physmem.perBankWrBursts::1               64106                       # Per bank write bursts
system.physmem.perBankWrBursts::2               62369                       # Per bank write bursts
system.physmem.perBankWrBursts::3               62872                       # Per bank write bursts
system.physmem.perBankWrBursts::4               62855                       # Per bank write bursts
system.physmem.perBankWrBursts::5               62943                       # Per bank write bursts
system.physmem.perBankWrBursts::6               64256                       # Per bank write bursts
system.physmem.perBankWrBursts::7               65177                       # Per bank write bursts
system.physmem.perBankWrBursts::8               67064                       # Per bank write bursts
system.physmem.perBankWrBursts::9               67603                       # Per bank write bursts
system.physmem.perBankWrBursts::10              67361                       # Per bank write bursts
system.physmem.perBankWrBursts::11              67637                       # Per bank write bursts
system.physmem.perBankWrBursts::12              67067                       # Per bank write bursts
system.physmem.perBankWrBursts::13              67487                       # Per bank write bursts
system.physmem.perBankWrBursts::14              66154                       # Per bank write bursts
system.physmem.perBankWrBursts::15              65656                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    1108725299500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                 2055599                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                1046417                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                   1922438                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    131799                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                        18                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    32284                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    33556                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    57018                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    60831                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    61268                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    61505                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    61466                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    61474                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    61478                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    61526                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    61560                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    61560                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    62022                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    62349                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    61672                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    62578                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    61195                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                    60970                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                       79                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                       11                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples      1917383                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      103.495400                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean      81.766538                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     125.134212                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127        1491936     77.81%     77.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255       306042     15.96%     93.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        52771      2.75%     96.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511        21239      1.11%     97.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639        13137      0.69%     98.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         7295      0.38%     98.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         5316      0.28%     98.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         4195      0.22%     99.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        15452      0.81%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total        1917383                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         60970                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        33.645219                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      157.122880                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023          60927     99.93%     99.93% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047           17      0.03%     99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-3071           12      0.02%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::3072-4095            6      0.01%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::4096-5119            3      0.00%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::9216-10239            2      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::12288-13311            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::13312-14335            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::22528-23551            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           60970                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         60970                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        17.162408                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       17.127431                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        1.097398                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16              27276     44.74%     44.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17               1165      1.91%     46.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18              28420     46.61%     93.26% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19               3653      5.99%     99.25% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20                385      0.63%     99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21                 61      0.10%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22                  7      0.01%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23                  3      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           60970                       # Writes before turning the bus around for reads
system.physmem.totQLat                    38268969000                       # Total ticks spent queuing
system.physmem.totMemAccLat               76786250250                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                  10271275000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       18629.12                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  37379.12                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                         118.58                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                          60.40                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                      118.66                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                       60.40                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           1.40                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.93                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.47                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        24.62                       # Average write queue length when enqueuing
system.physmem.readRowHits                     776845                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    406412                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   37.82                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  38.84                       # Row buffer hit rate for writes
system.physmem.avgGap                       357420.88                       # Average gap between requests
system.physmem.pageHitRate                      38.16                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                 7070973840                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                 3858170250                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                7753512000                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy               3307152240                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy            72416401200                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy           416204777970                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           300142086750                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             810753074250                       # Total energy per rank (pJ)
system.physmem_0.averagePower              731.249224                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   496624730250                       # Time in different power states
system.physmem_0.memoryStateTime::REF     37022700000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT    575075912250                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                 7424434080                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                 4051030500                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                8269419600                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy               3473467920                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy            72416401200                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy           425140731810                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           292303530750                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             813079015860                       # Total energy per rank (pJ)
system.physmem_1.averagePower              733.347080                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   483537101750                       # Time in different power states
system.physmem_1.memoryStateTime::REF     37022700000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT    588165429250                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu.branchPred.lookups               240158127                       # Number of BP lookups
system.cpu.branchPred.condPredicted         186758642                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect          14604059                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups            133657061                       # Number of BTB lookups
system.cpu.branchPred.BTBHits               122306338                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             91.507577                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                15659556                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect                 15                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.walks                         0                       # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                   46                       # Number of system calls
system.cpu.numCycles                       2217450776                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                  1544563087                       # Number of instructions committed
system.cpu.committedOps                    1664032480                       # Number of ops (including micro ops) committed
system.cpu.discardedOps                      40093383                       # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
system.cpu.cpi                               1.435649                       # CPI: cycles per instruction
system.cpu.ipc                               0.696549                       # IPC: instructions per cycle
system.cpu.tickCycles                      1838812013                       # Number of cycles that the object actually ticked
system.cpu.idleCycles                       378638763                       # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements           9223724                       # number of replacements
system.cpu.dcache.tags.tagsinuse          4085.606596                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           624087400                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           9227820                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             67.631076                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle        9776044000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data  4085.606596                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.997463                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.997463                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0          257                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1         1296                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2         2482                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3           61                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses        1276555670                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses       1276555670                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data    453740634                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       453740634                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data    170346644                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total      170346644                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data           61                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total           61                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data           61                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total           61                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data     624087278                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        624087278                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    624087278                       # number of overall hits
system.cpu.dcache.overall_hits::total       624087278                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      7337122                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       7337122                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      2239403                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      2239403                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data      9576525                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        9576525                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      9576525                       # number of overall misses
system.cpu.dcache.overall_misses::total       9576525                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 183400270746                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 183400270746                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 101399706750                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 101399706750                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 284799977496                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 284799977496                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 284799977496                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 284799977496                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    461077756                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    461077756                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data    172586047                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total    172586047                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data           61                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total           61                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data           61                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total           61                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    633663803                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    633663803                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    633663803                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    633663803                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.015913                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.015913                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.012976                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.012976                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.015113                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.015113                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.015113                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.015113                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24996.213876                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 24996.213876                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45279.794101                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 45279.794101                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 29739.386416                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 29739.386416                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 29739.386416                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 29739.386416                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      3701129                       # number of writebacks
system.cpu.dcache.writebacks::total           3701129                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data          221                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total          221                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data       348484                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total       348484                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data       348705                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total       348705                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data       348705                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total       348705                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7336901                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      7336901                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1890919                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total      1890919                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      9227820                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      9227820                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      9227820                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      9227820                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 168309061254                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 168309061254                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  77322111500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  77322111500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 245631172754                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 245631172754                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 245631172754                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 245631172754                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.015913                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.015913                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.010956                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.010956                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.014563                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.014563                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.014563                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.014563                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22940.075279                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22940.075279                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40891.286988                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40891.286988                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26618.548341                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 26618.548341                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26618.548341                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 26618.548341                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements                29                       # number of replacements
system.cpu.icache.tags.tagsinuse           661.153981                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           466170177                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs               820                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs          568500.215854                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   661.153981                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.322829                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.322829                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          791                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           32                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2            5                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4          754                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.386230                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         932342814                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        932342814                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst    466170177                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       466170177                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     466170177                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        466170177                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    466170177                       # number of overall hits
system.cpu.icache.overall_hits::total       466170177                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst          820                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total           820                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst          820                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total            820                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst          820                       # number of overall misses
system.cpu.icache.overall_misses::total           820                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst     58360249                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total     58360249                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst     58360249                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total     58360249                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst     58360249                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total     58360249                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    466170997                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    466170997                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    466170997                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    466170997                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    466170997                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    466170997                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000002                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000002                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000002                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000002                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000002                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000002                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71171.035366                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 71171.035366                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 71171.035366                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 71171.035366                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 71171.035366                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 71171.035366                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst          820                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total          820                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst          820                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total          820                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst          820                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total          820                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     56400751                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total     56400751                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst     56400751                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total     56400751                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst     56400751                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total     56400751                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000002                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000002                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000002                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68781.403659                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68781.403659                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68781.403659                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 68781.403659                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68781.403659                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 68781.403659                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements          2022895                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        31254.140512                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            8985448                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs          2052670                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             4.377444                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle      59502848750                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 14999.285776                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst    26.862616                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 16227.992121                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.457742                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.000820                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.495239                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.953801                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        29775                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           91                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1           31                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1247                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3        12850                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        15556                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.908661                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses        107381741                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses       107381741                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst           32                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data      6082181                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        6082213                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks      3701129                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      3701129                       # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data      1090823                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total      1090823                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst           32                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      7173004                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         7173036                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst           32                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      7173004                       # number of overall hits
system.cpu.l2cache.overall_hits::total        7173036                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst          788                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data      1254720                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total      1255508                       # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       800096                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       800096                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst          788                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data      2054816                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total       2055604                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst          788                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data      2054816                       # number of overall misses
system.cpu.l2cache.overall_misses::total      2055604                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     55257250                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 100145150750                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 100200408000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  64467346000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  64467346000                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst     55257250                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 164612496750                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 164667754000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst     55257250                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 164612496750                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 164667754000                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst          820                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data      7336901                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      7337721                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks      3701129                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      3701129                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data      1890919                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total      1890919                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst          820                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      9227820                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      9228640                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst          820                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      9227820                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      9228640                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.960976                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.171015                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.171103                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.423125                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.423125                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.960976                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.222676                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.222742                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.960976                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.222676                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.222742                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70123.413706                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79814.740141                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 79808.657531                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80574.513558                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80574.513558                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70123.413706                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80110.577662                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 80106.749160                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70123.413706                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80110.577662                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 80106.749160                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks      1046417                       # number of writebacks
system.cpu.l2cache.writebacks::total          1046417                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            1                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data            4                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total            5                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data            4                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total            5                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data            4                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total            5                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          787                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data      1254716                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total      1255503                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       800096                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       800096                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst          787                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data      2054812                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total      2055599                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst          787                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data      2054812                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total      2055599                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     45360250                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  84287306750                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total  84332667000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  54391877500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  54391877500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     45360250                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 138679184250                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 138724544500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     45360250                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 138679184250                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 138724544500                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.959756                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.171014                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.171103                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.423125                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.423125                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.959756                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.222676                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.222741                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.959756                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.222676                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.222741                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57636.912325                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67176.402270                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67170.422532                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67981.689072                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67981.689072                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57636.912325                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67489.962220                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67486.189913                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57636.912325                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67489.962220                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67486.189913                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq        7337721                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       7337721                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback      3701129                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq      1890919                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp      1890919                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1640                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     22156769                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total          22158409                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        52480                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    827452736                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          827505216                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples     12929769                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean               5                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::3                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::5           12929769    100.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::6                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            5                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total       12929769                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy    10166013500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.9                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy       1389749                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy   14186681246                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          1.3                       # Layer utilization (%)
system.membus.trans_dist::ReadReq             1255503                       # Transaction distribution
system.membus.trans_dist::ReadResp            1255503                       # Transaction distribution
system.membus.trans_dist::Writeback           1046417                       # Transaction distribution
system.membus.trans_dist::ReadExReq            800096                       # Transaction distribution
system.membus.trans_dist::ReadExResp           800096                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      5157615                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                5157615                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    198529024                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               198529024                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoop_fanout::samples           3102016                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                 3102016    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total             3102016                       # Request fanout histogram
system.membus.reqLayer0.occupancy         12126859000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               1.1                       # Layer utilization (%)
system.membus.respLayer1.occupancy        19430032500                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              1.8                       # Layer utilization (%)

---------- End Simulation Statistics   ----------