path: root/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  1.121265                       # Number of seconds simulated
sim_ticks                                1121265462500                       # Number of ticks simulated
final_tick                               1121265462500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 175724                       # Simulator instruction rate (inst/s)
host_op_rate                                   189316                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                              127565822                       # Simulator tick rate (ticks/s)
host_mem_usage                                 306448                       # Number of bytes of host memory used
host_seconds                                  8789.70                       # Real time elapsed on the host
sim_insts                                  1544563088                       # Number of instructions simulated
sim_ops                                    1664032481                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst             50816                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data         131531264                       # Number of bytes read from this memory
system.physmem.bytes_read::total            131582080                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst        50816                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           50816                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     66976320                       # Number of bytes written to this memory
system.physmem.bytes_written::total          66976320                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst                794                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data            2055176                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               2055970                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1046505                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1046505                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst                45320                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data            117306087                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total               117351407                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst           45320                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total              45320                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks          59732795                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total               59732795                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks          59732795                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst               45320                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data           117306087                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              177084202                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                       2055970                       # Number of read requests accepted
system.physmem.writeReqs                      1046505                       # Number of write requests accepted
system.physmem.readBursts                     2055970                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                    1046505                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                131497344                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     84736                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  66974720                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                 131582080                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               66976320                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                     1324                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0              128088                       # Per bank write bursts
system.physmem.perBankRdBursts::1              125235                       # Per bank write bursts
system.physmem.perBankRdBursts::2              122283                       # Per bank write bursts
system.physmem.perBankRdBursts::3              124122                       # Per bank write bursts
system.physmem.perBankRdBursts::4              123237                       # Per bank write bursts
system.physmem.perBankRdBursts::5              123404                       # Per bank write bursts
system.physmem.perBankRdBursts::6              123754                       # Per bank write bursts
system.physmem.perBankRdBursts::7              124260                       # Per bank write bursts
system.physmem.perBankRdBursts::8              132002                       # Per bank write bursts
system.physmem.perBankRdBursts::9              134077                       # Per bank write bursts
system.physmem.perBankRdBursts::10             132455                       # Per bank write bursts
system.physmem.perBankRdBursts::11             133729                       # Per bank write bursts
system.physmem.perBankRdBursts::12             133726                       # Per bank write bursts
system.physmem.perBankRdBursts::13             133924                       # Per bank write bursts
system.physmem.perBankRdBursts::14             129890                       # Per bank write bursts
system.physmem.perBankRdBursts::15             130460                       # Per bank write bursts
system.physmem.perBankWrBursts::0               65849                       # Per bank write bursts
system.physmem.perBankWrBursts::1               64148                       # Per bank write bursts
system.physmem.perBankWrBursts::2               62390                       # Per bank write bursts
system.physmem.perBankWrBursts::3               62849                       # Per bank write bursts
system.physmem.perBankWrBursts::4               62818                       # Per bank write bursts
system.physmem.perBankWrBursts::5               62997                       # Per bank write bursts
system.physmem.perBankWrBursts::6               64238                       # Per bank write bursts
system.physmem.perBankWrBursts::7               65252                       # Per bank write bursts
system.physmem.perBankWrBursts::8               67098                       # Per bank write bursts
system.physmem.perBankWrBursts::9               67598                       # Per bank write bursts
system.physmem.perBankWrBursts::10              67270                       # Per bank write bursts
system.physmem.perBankWrBursts::11              67670                       # Per bank write bursts
system.physmem.perBankWrBursts::12              67009                       # Per bank write bursts
system.physmem.perBankWrBursts::13              67470                       # Per bank write bursts
system.physmem.perBankWrBursts::14              66159                       # Per bank write bursts
system.physmem.perBankWrBursts::15              65665                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    1121265368000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                 2055970                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                1046505                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                   1926795                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    127832                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                        19                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    32223                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    33685                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    56905                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    60965                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    61436                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    61459                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    61451                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    61451                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    61467                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    61525                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    61499                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    61509                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    62354                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    61776                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    61856                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    62659                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    61196                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                    60967                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                       93                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                       11                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples      1920747                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      103.329698                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean      81.701744                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     124.647307                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127        1495902     77.88%     77.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255       305625     15.91%     93.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        52698      2.74%     96.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511        21305      1.11%     97.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639        13173      0.69%     98.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         7131      0.37%     98.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         5450      0.28%     98.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         5094      0.27%     99.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        14369      0.75%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total        1920747                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         60965                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        33.654375                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      161.846066                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023          60925     99.93%     99.93% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047           15      0.02%     99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-3071           10      0.02%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::3072-4095            7      0.01%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::4096-5119            3      0.00%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::10240-11263            1      0.00%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::12288-13311            2      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::13312-14335            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::22528-23551            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           60965                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         60965                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        17.165259                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       17.130353                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        1.096188                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16              27136     44.51%     44.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17               1324      2.17%     46.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18              28285     46.40%     93.08% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19               3807      6.24%     99.32% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20                355      0.58%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21                 47      0.08%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22                  9      0.01%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23                  1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::25                  1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           60965                       # Writes before turning the bus around for reads
system.physmem.totQLat                    38466601000                       # Total ticks spent queuing
system.physmem.totMemAccLat               76991213500                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                  10273230000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       18721.77                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  37471.77                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                         117.28                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                          59.73                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                      117.35                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                       59.73                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           1.38                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.92                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.47                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        24.95                       # Average write queue length when enqueuing
system.physmem.readRowHits                     774547                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    405822                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   37.70                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  38.78                       # Row buffer hit rate for writes
system.physmem.avgGap                       361409.96                       # Average gap between requests
system.physmem.pageHitRate                      38.06                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                 7084922040                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                 3865780875                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                7755875400                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy               3308305680                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy            73235182800                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy           422966689965                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           301732094250                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             819948851010                       # Total energy per rank (pJ)
system.physmem_0.averagePower              731.275041                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   499232206000                       # Time in different power states
system.physmem_0.memoryStateTime::REF     37441300000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT    584588629000                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                 7435910160                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                 4057292250                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                8269996800                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy               3472884720                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy            73235182800                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy           431711081055                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           294061575750                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             822243923535                       # Total energy per rank (pJ)
system.physmem_1.averagePower              733.321912                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   486423236500                       # Time in different power states
system.physmem_1.memoryStateTime::REF     37441300000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT    597397500000                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu.branchPred.lookups               240144458                       # Number of BP lookups
system.cpu.branchPred.condPredicted         186748856                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect          14594265                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups            132793559                       # Number of BTB lookups
system.cpu.branchPred.BTBHits               122289853                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             92.090199                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                15658823                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect                 15                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.walks                         0                       # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                   46                       # Number of system calls
system.cpu.numCycles                       2242530925                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                  1544563088                       # Number of instructions committed
system.cpu.committedOps                    1664032481                       # Number of ops (including micro ops) committed
system.cpu.discardedOps                      40067412                       # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
system.cpu.cpi                               1.451887                       # CPI: cycles per instruction
system.cpu.ipc                               0.688759                       # IPC: instructions per cycle
system.cpu.tickCycles                      1838970368                       # Number of cycles that the object actually ticked
system.cpu.idleCycles                       403560557                       # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements           9223420                       # number of replacements
system.cpu.dcache.tags.tagsinuse          4085.640559                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           624065637                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           9227516                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             67.630946                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle        9814734000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data  4085.640559                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.997471                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.997471                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0          252                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1         1219                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2         2564                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3           61                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses        1276541490                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses       1276541490                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data    453733959                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       453733959                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data    170331555                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total      170331555                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data            1                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total             1                       # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data           61                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total           61                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data           61                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total           61                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data     624065514                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        624065514                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    624065515                       # number of overall hits
system.cpu.dcache.overall_hits::total       624065515                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      7336856                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       7336856                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      2254492                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      2254492                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data            2                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total            2                       # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data      9591348                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        9591348                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      9591350                       # number of overall misses
system.cpu.dcache.overall_misses::total       9591350                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 192473949996                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 192473949996                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 109728776250                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 109728776250                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 302202726246                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 302202726246                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 302202726246                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 302202726246                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    461070815                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    461070815                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data    172586047                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total    172586047                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data            3                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total            3                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data           61                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total           61                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data           61                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total           61                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    633656862                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    633656862                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    633656865                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    633656865                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.015913                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.015913                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.013063                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.013063                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.666667                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.666667                       # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.015137                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.015137                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.015137                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.015137                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26233.845941                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 26233.845941                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48671.175702                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 48671.175702                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 31507.847098                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 31507.847098                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 31507.840528                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 31507.840528                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      3700612                       # number of writebacks
system.cpu.dcache.writebacks::total           3700612                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data          212                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total          212                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data       363621                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total       363621                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data       363833                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total       363833                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data       363833                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total       363833                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7336644                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      7336644                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1890871                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total      1890871                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data            1                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total            1                       # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      9227515                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      9227515                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      9227516                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      9227516                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 181052332504                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 181052332504                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  83984263000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  83984263000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data        73750                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total        73750                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 265036595504                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 265036595504                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 265036669254                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 265036669254                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.015912                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.015912                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.010956                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.010956                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.333333                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.333333                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.014562                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.014562                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.014562                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.014562                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24677.813521                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24677.813521                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44415.649190                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44415.649190                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        73750                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        73750                       # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28722.423697                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 28722.423697                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28722.428577                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 28722.428577                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements                35                       # number of replacements
system.cpu.icache.tags.tagsinuse           662.614734                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           466141021                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs               828                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs          562972.247585                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   662.614734                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.323542                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.323542                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          793                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           32                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2            7                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4          754                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.387207                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         932284526                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        932284526                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst    466141021                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       466141021                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     466141021                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        466141021                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    466141021                       # number of overall hits
system.cpu.icache.overall_hits::total       466141021                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst          828                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total           828                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst          828                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total            828                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst          828                       # number of overall misses
system.cpu.icache.overall_misses::total           828                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst     63773749                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total     63773749                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst     63773749                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total     63773749                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst     63773749                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total     63773749                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    466141849                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    466141849                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    466141849                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    466141849                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    466141849                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    466141849                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000002                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000002                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000002                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000002                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000002                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000002                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77021.435990                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 77021.435990                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 77021.435990                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 77021.435990                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 77021.435990                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 77021.435990                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst          828                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total          828                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst          828                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total          828                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst          828                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total          828                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     62196251                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total     62196251                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst     62196251                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total     62196251                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst     62196251                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total     62196251                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000002                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000002                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000002                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75116.245169                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75116.245169                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75116.245169                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 75116.245169                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75116.245169                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 75116.245169                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements          2023265                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        31261.991003                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            8984313                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs          2053040                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             4.376102                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle      59841737750                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 14971.940870                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst    26.910061                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 16263.140072                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.456907                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.000821                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.496312                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.954040                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        29775                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           91                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1           31                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1247                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3        12852                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        15554                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.908661                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses        107375559                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses       107375559                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst           33                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data      6081577                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        6081610                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks      3700612                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      3700612                       # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data      1090759                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total      1090759                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst           33                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      7172336                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         7172369                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst           33                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      7172336                       # number of overall hits
system.cpu.l2cache.overall_hits::total        7172369                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst          795                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data      1255068                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total      1255863                       # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       800112                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       800112                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst          795                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data      2055180                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total       2055975                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst          795                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data      2055180                       # number of overall misses
system.cpu.l2cache.overall_misses::total      2055975                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     61020250                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 109853349250                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 109914369500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  70575135000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  70575135000                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst     61020250                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 180428484250                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 180489504500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst     61020250                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 180428484250                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 180489504500                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst          828                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data      7336645                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      7337473                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks      3700612                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      3700612                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data      1890871                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total      1890871                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst          828                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      9227516                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      9228344                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst          828                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      9227516                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      9228344                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.960145                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.171068                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.171157                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.423145                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.423145                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.960145                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.222723                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.222789                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.960145                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.222723                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.222789                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76755.031447                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 87527.806661                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 87520.987162                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88206.569830                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88206.569830                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76755.031447                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87792.059211                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 87787.791437                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76755.031447                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87792.059211                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 87787.791437                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks      1046505                       # number of writebacks
system.cpu.l2cache.writebacks::total          1046505                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            1                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data            4                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total            5                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data            4                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total            5                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data            4                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total            5                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          794                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data      1255064                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total      1255858                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       800112                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       800112                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst          794                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data      2055176                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total      2055970                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst          794                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data      2055176                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total      2055970                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     51069250                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  93985038750                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total  94036108000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  60466755500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  60466755500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     51069250                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 154451794250                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 154502863500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     51069250                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 154451794250                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 154502863500                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.958937                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.171068                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.171157                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.423145                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.423145                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.958937                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.222723                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.222789                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.958937                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.222723                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.222789                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64318.954660                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 74884.658272                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 74877.978243                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 75572.864174                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 75572.864174                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64318.954660                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 75152.587540                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75148.403673                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64318.954660                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75152.587540                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 75148.403673                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq        7337473                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       7337473                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback      3700612                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq      1890871                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp      1890871                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1656                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     22155644                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total          22157300                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        52992                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    827400192                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          827453184                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples     12928956                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean               3                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::3           12928956    100.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            3                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            3                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total       12928956                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy    10165090000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.9                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy       1409749                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy   14190252246                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          1.3                       # Layer utilization (%)
system.membus.trans_dist::ReadReq             1255858                       # Transaction distribution
system.membus.trans_dist::ReadResp            1255858                       # Transaction distribution
system.membus.trans_dist::Writeback           1046505                       # Transaction distribution
system.membus.trans_dist::ReadExReq            800112                       # Transaction distribution
system.membus.trans_dist::ReadExResp           800112                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      5158445                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                5158445                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    198558400                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               198558400                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoop_fanout::samples           3102475                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                 3102475    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total             3102475                       # Request fanout histogram
system.membus.reqLayer0.occupancy          7945005500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.7                       # Layer utilization (%)
system.membus.respLayer1.occupancy        11244435500                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              1.0                       # Layer utilization (%)

---------- End Simulation Statistics   ----------