path: root/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  1.130744                       # Number of seconds simulated
sim_ticks                                1130744162500                       # Number of ticks simulated
final_tick                               1130744162500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 210155                       # Simulator instruction rate (inst/s)
host_op_rate                                   226410                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                              153850224                       # Simulator tick rate (ticks/s)
host_mem_usage                                 274312                       # Number of bytes of host memory used
host_seconds                                  7349.64                       # Real time elapsed on the host
sim_insts                                  1544563088                       # Number of instructions simulated
sim_ops                                    1664032481                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 1130744162500                       # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst             50240                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data         132094976                       # Number of bytes read from this memory
system.physmem.bytes_read::total            132145216                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst        50240                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           50240                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     67850112                       # Number of bytes written to this memory
system.physmem.bytes_written::total          67850112                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst                785                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data            2063984                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               2064769                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1060158                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1060158                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst                44431                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data            116821276                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total               116865707                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst           44431                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total              44431                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks          60004831                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total               60004831                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks          60004831                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst               44431                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data           116821276                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              176870538                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                       2064769                       # Number of read requests accepted
system.physmem.writeReqs                      1060158                       # Number of write requests accepted
system.physmem.readBursts                     2064769                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                    1060158                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                132060352                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     84864                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  67848640                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                 132145216                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               67850112                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                     1326                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0              128520                       # Per bank write bursts
system.physmem.perBankRdBursts::1              125806                       # Per bank write bursts
system.physmem.perBankRdBursts::2              122672                       # Per bank write bursts
system.physmem.perBankRdBursts::3              124571                       # Per bank write bursts
system.physmem.perBankRdBursts::4              123572                       # Per bank write bursts
system.physmem.perBankRdBursts::5              123679                       # Per bank write bursts
system.physmem.perBankRdBursts::6              124365                       # Per bank write bursts
system.physmem.perBankRdBursts::7              124958                       # Per bank write bursts
system.physmem.perBankRdBursts::8              132489                       # Per bank write bursts
system.physmem.perBankRdBursts::9              134780                       # Per bank write bursts
system.physmem.perBankRdBursts::10             133233                       # Per bank write bursts
system.physmem.perBankRdBursts::11             134506                       # Per bank write bursts
system.physmem.perBankRdBursts::12             134518                       # Per bank write bursts
system.physmem.perBankRdBursts::13             134594                       # Per bank write bursts
system.physmem.perBankRdBursts::14             130540                       # Per bank write bursts
system.physmem.perBankRdBursts::15             130640                       # Per bank write bursts
system.physmem.perBankWrBursts::0               66781                       # Per bank write bursts
system.physmem.perBankWrBursts::1               64941                       # Per bank write bursts
system.physmem.perBankWrBursts::2               63173                       # Per bank write bursts
system.physmem.perBankWrBursts::3               63584                       # Per bank write bursts
system.physmem.perBankWrBursts::4               63558                       # Per bank write bursts
system.physmem.perBankWrBursts::5               63644                       # Per bank write bursts
system.physmem.perBankWrBursts::6               65047                       # Per bank write bursts
system.physmem.perBankWrBursts::7               66055                       # Per bank write bursts
system.physmem.perBankWrBursts::8               67972                       # Per bank write bursts
system.physmem.perBankWrBursts::9               68438                       # Per bank write bursts
system.physmem.perBankWrBursts::10              68161                       # Per bank write bursts
system.physmem.perBankWrBursts::11              68586                       # Per bank write bursts
system.physmem.perBankWrBursts::12              68040                       # Per bank write bursts
system.physmem.perBankWrBursts::13              68530                       # Per bank write bursts
system.physmem.perBankWrBursts::14              67159                       # Per bank write bursts
system.physmem.perBankWrBursts::15              66466                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    1130744067500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                 2064769                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                1060158                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                   1931837                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    131592                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                        14                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    32506                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    33515                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    57459                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    62386                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    62542                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    62618                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    62533                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    62474                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    62468                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    62484                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    62514                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    62444                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    62521                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    62600                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    62677                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    62255                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    62124                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                    61991                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                       32                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples      1925169                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      103.839212                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean      81.850367                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     126.421931                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127        1496084     77.71%     77.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255       309482     16.08%     93.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        52255      2.71%     96.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511        20716      1.08%     97.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639        12793      0.66%     98.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         7748      0.40%     98.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         5753      0.30%     98.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         5054      0.26%     99.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        15284      0.79%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total        1925169                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         61990                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        33.244314                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::gmean       23.928422                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      148.698604                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023          61952     99.94%     99.94% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047           16      0.03%     99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-3071            7      0.01%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::3072-4095            5      0.01%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::4096-5119            5      0.01%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::9216-10239            2      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::14336-15359            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::15360-16383            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::17408-18431            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           61990                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         61990                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        17.101710                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       17.070337                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        1.034747                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16              28322     45.69%     45.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17               1015      1.64%     47.33% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18              30732     49.58%     96.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19               1873      3.02%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20                 43      0.07%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21                  5      0.01%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           61990                       # Writes before turning the bus around for reads
system.physmem.totQLat                    38536102500                       # Total ticks spent queuing
system.physmem.totMemAccLat               77225658750                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                  10317215000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       18675.63                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  37425.63                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                         116.79                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                          60.00                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                      116.87                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                       60.00                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           1.38                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.91                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.47                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        25.42                       # Average write queue length when enqueuing
system.physmem.readRowHits                     775929                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    422476                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   37.60                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  39.85                       # Row buffer hit rate for writes
system.physmem.avgGap                       361846.55                       # Average gap between requests
system.physmem.pageHitRate                      38.37                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                 7091695800                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                 3869476875                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                7785421800                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy               3348753840                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy            73854608880                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy           423921506085                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           306584736000                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             826456199280                       # Total energy per rank (pJ)
system.physmem_0.averagePower              730.896688                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   507283799000                       # Time in different power states
system.physmem_0.memoryStateTime::REF     37757980000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT    585701078500                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                 7462581840                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                 4071845250                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                8309316600                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy               3520920960                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy            73854608880                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy           432965070225                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           298651785000                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             828836128755                       # Total energy per rank (pJ)
system.physmem_1.averagePower              733.001436                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   494051909000                       # Time in different power states
system.physmem_1.memoryStateTime::REF     37757980000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT    598934101500                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.pwrStateResidencyTicks::UNDEFINED 1130744162500                       # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups               240019432                       # Number of BP lookups
system.cpu.branchPred.condPredicted         186610009                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect          14528957                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups            131647101                       # Number of BTB lookups
system.cpu.branchPred.BTBHits               122324380                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             92.918400                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                15657431                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect                 15                       # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups             535                       # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits                232                       # Number of indirect target hits.
system.cpu.branchPred.indirectMisses              303                       # Number of indirect misses.
system.cpu.branchPredindirectMispredicted          162                       # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1130744162500                       # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1130744162500                       # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1130744162500                       # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1130744162500                       # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks                         0                       # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                   46                       # Number of system calls
system.cpu.pwrStateResidencyTicks::ON    1130744162500                       # Cumulative time (in ticks) in various power states
system.cpu.numCycles                       2261488325                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                  1544563088                       # Number of instructions committed
system.cpu.committedOps                    1664032481                       # Number of ops (including micro ops) committed
system.cpu.discardedOps                      41363718                       # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
system.cpu.cpi                               1.464161                       # CPI: cycles per instruction
system.cpu.ipc                               0.682985                       # IPC: instructions per cycle
system.cpu.op_class_0::No_OpClass                   0      0.00%      0.00% # Class of committed instruction
system.cpu.op_class_0::IntAlu              1030178776     61.91%     61.91% # Class of committed instruction
system.cpu.op_class_0::IntMult                 700322      0.04%     61.95% # Class of committed instruction
system.cpu.op_class_0::IntDiv                       0      0.00%     61.95% # Class of committed instruction
system.cpu.op_class_0::FloatAdd                     0      0.00%     61.95% # Class of committed instruction
system.cpu.op_class_0::FloatCmp                     0      0.00%     61.95% # Class of committed instruction
system.cpu.op_class_0::FloatCvt                     0      0.00%     61.95% # Class of committed instruction
system.cpu.op_class_0::FloatMult                    0      0.00%     61.95% # Class of committed instruction
system.cpu.op_class_0::FloatDiv                     0      0.00%     61.95% # Class of committed instruction
system.cpu.op_class_0::FloatSqrt                    0      0.00%     61.95% # Class of committed instruction
system.cpu.op_class_0::SimdAdd                      0      0.00%     61.95% # Class of committed instruction
system.cpu.op_class_0::SimdAddAcc                   0      0.00%     61.95% # Class of committed instruction
system.cpu.op_class_0::SimdAlu                      0      0.00%     61.95% # Class of committed instruction
system.cpu.op_class_0::SimdCmp                      0      0.00%     61.95% # Class of committed instruction
system.cpu.op_class_0::SimdCvt                      0      0.00%     61.95% # Class of committed instruction
system.cpu.op_class_0::SimdMisc                     0      0.00%     61.95% # Class of committed instruction
system.cpu.op_class_0::SimdMult                     0      0.00%     61.95% # Class of committed instruction
system.cpu.op_class_0::SimdMultAcc                  0      0.00%     61.95% # Class of committed instruction
system.cpu.op_class_0::SimdShift                    0      0.00%     61.95% # Class of committed instruction
system.cpu.op_class_0::SimdShiftAcc                 0      0.00%     61.95% # Class of committed instruction
system.cpu.op_class_0::SimdSqrt                     0      0.00%     61.95% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAdd                 0      0.00%     61.95% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAlu                 0      0.00%     61.95% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCmp                 0      0.00%     61.95% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCvt                 0      0.00%     61.95% # Class of committed instruction
system.cpu.op_class_0::SimdFloatDiv                 0      0.00%     61.95% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMisc                3      0.00%     61.95% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMult                0      0.00%     61.95% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMultAcc             0      0.00%     61.95% # Class of committed instruction
system.cpu.op_class_0::SimdFloatSqrt                0      0.00%     61.95% # Class of committed instruction
system.cpu.op_class_0::MemRead              458306334     27.54%     89.49% # Class of committed instruction
system.cpu.op_class_0::MemWrite             174847046     10.51%    100.00% # Class of committed instruction
system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
system.cpu.op_class_0::total               1664032481                       # Class of committed instruction
system.cpu.tickCycles                      1844743027                       # Number of cycles that the object actually ticked
system.cpu.idleCycles                       416745298                       # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1130744162500                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements           9220102                       # number of replacements
system.cpu.dcache.tags.tagsinuse          4085.712457                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           624495296                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           9224198                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             67.701853                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle        9823555500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data  4085.712457                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.997488                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.997488                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0          239                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1         1231                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2         2563                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3           63                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses        1277391740                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses       1277391740                       # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1130744162500                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data    454164183                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       454164183                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data    170330990                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total      170330990                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data            1                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total             1                       # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data           61                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total           61                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data           61                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total           61                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data     624495173                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        624495173                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    624495174                       # number of overall hits
system.cpu.dcache.overall_hits::total       624495174                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      7333416                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       7333416                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      2255057                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      2255057                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data            2                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total            2                       # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data      9588473                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        9588473                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      9588475                       # number of overall misses
system.cpu.dcache.overall_misses::total       9588475                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 192638967000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 192638967000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 111261397000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 111261397000                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 303900364000                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 303900364000                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 303900364000                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 303900364000                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    461497599                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    461497599                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data    172586047                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total    172586047                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data            3                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total            3                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data           61                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total           61                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data           61                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total           61                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    634083646                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    634083646                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    634083649                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    634083649                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.015890                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.015890                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.013066                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.013066                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.666667                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.666667                       # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.015122                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.015122                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.015122                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.015122                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26268.653926                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 26268.653926                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 49338.618492                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 49338.618492                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 31694.344240                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 31694.344240                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 31694.337629                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 31694.337629                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks      3670051                       # number of writebacks
system.cpu.dcache.writebacks::total           3670051                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data           49                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total           49                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data       364227                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total       364227                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data       364276                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total       364276                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data       364276                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total       364276                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7333367                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      7333367                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1890830                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total      1890830                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data            1                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total            1                       # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      9224197                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      9224197                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      9224198                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      9224198                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 185303496000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 185303496000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  86626211500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  86626211500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data        75000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total        75000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 271929707500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 271929707500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 271929782500                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 271929782500                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.015890                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.015890                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.010956                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.010956                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.333333                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.333333                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.014547                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.014547                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.014547                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.014547                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25268.542540                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25268.542540                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45813.855027                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45813.855027                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        75000                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        75000                       # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29480.041189                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 29480.041189                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29480.046124                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 29480.046124                       # average overall mshr miss latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1130744162500                       # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements                33                       # number of replacements
system.cpu.icache.tags.tagsinuse           660.343836                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           466264831                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs               822                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs          567232.154501                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   660.343836                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.322434                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.322434                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          789                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           32                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2            6                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4          751                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.385254                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         932532128                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        932532128                       # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1130744162500                       # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst    466264831                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       466264831                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     466264831                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        466264831                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    466264831                       # number of overall hits
system.cpu.icache.overall_hits::total       466264831                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst          822                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total           822                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst          822                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total            822                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst          822                       # number of overall misses
system.cpu.icache.overall_misses::total           822                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst     62977000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total     62977000                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst     62977000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total     62977000                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst     62977000                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total     62977000                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    466265653                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    466265653                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    466265653                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    466265653                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    466265653                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    466265653                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000002                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000002                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000002                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000002                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000002                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000002                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76614.355231                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 76614.355231                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 76614.355231                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 76614.355231                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 76614.355231                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 76614.355231                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks           33                       # number of writebacks
system.cpu.icache.writebacks::total                33                       # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst          822                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total          822                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst          822                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total          822                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst          822                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total          822                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     62155000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total     62155000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst     62155000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total     62155000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst     62155000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total     62155000                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000002                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000002                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000002                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75614.355231                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75614.355231                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75614.355231                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 75614.355231                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75614.355231                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 75614.355231                       # average overall mshr miss latency
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1130744162500                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements          2032337                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        31884.361365                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs           16378235                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs          2065105                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             7.930945                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle      54418076000                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks    10.408988                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst    25.813492                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 31848.138885                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.000318                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.000788                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.971928                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.973033                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        32768                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           48                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          912                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2876                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         7195                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        21737                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses        149613593                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses       149613593                       # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1130744162500                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks      3670051                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total      3670051                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks           33                       # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total           33                       # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data      1078506                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total      1078506                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst           37                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total           37                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data      6081702                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total      6081702                       # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst           37                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      7160208                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         7160245                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst           37                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      7160208                       # number of overall hits
system.cpu.l2cache.overall_hits::total        7160245                       # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data       812324                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       812324                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          785                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total          785                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data      1251666                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total      1251666                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst          785                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data      2063990                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total       2064775                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst          785                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data      2063990                       # number of overall misses
system.cpu.l2cache.overall_misses::total      2064775                       # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  72440693500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  72440693500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     60501000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total     60501000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 110442540000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 110442540000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst     60501000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 182883233500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 182943734500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst     60501000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 182883233500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 182943734500                       # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks      3670051                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total      3670051                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks           33                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total           33                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data      1890830                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total      1890830                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          822                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total          822                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      7333368                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total      7333368                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst          822                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      9224198                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      9225020                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst          822                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      9224198                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      9225020                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.429612                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.429612                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.954988                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.954988                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.170681                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.170681                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.954988                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.223758                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.223823                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.954988                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.223758                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.223823                       # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89177.093746                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 89177.093746                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77071.337580                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77071.337580                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 88236.430485                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 88236.430485                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77071.337580                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 88606.647077                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 88602.261505                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77071.337580                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88606.647077                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 88602.261505                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.writebacks::writebacks      1060158                       # number of writebacks
system.cpu.l2cache.writebacks::total          1060158                       # number of writebacks
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data            6                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total            6                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data            6                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total            6                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data            6                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total            6                       # number of overall MSHR hits
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          215                       # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total          215                       # number of CleanEvict MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       812324                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       812324                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          785                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total          785                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data      1251660                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total      1251660                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst          785                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data      2063984                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total      2064769                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst          785                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data      2063984                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total      2064769                       # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  64317453500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  64317453500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     52651000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     52651000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  97925523500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  97925523500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     52651000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 162242977000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 162295628000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     52651000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 162242977000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 162295628000                       # number of overall MSHR miss cycles
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.429612                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.429612                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.954988                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.954988                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.170680                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.170680                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.954988                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.223758                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.223823                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.954988                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.223758                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.223823                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79177.093746                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79177.093746                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67071.337580                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67071.337580                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78236.520701                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78236.520701                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67071.337580                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78606.702862                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 78602.317257                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67071.337580                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78606.702862                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78602.317257                       # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests     18445155                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests      9220147                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests         1594                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops         1445                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1439                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            6                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1130744162500                       # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp       7334190                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty      4730209                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean           33                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict      6522230                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq      1890830                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp      1890830                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq          822                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq      7333368                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1677                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     27668498                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total          27670175                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        54720                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    825231936                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          825286656                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                     2032337                       # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic              67850112                       # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples     11257357                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        0.000272                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.016509                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0           11254306     99.97%     99.97% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1               3045      0.03%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  6      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total       11257357                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy    12892661500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          1.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy       1233000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy   13836299994                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          1.2                       # Layer utilization (%)
system.membus.snoop_filter.tot_requests       4095876                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests      2031264                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 1130744162500                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp            1252445                       # Transaction distribution
system.membus.trans_dist::WritebackDirty      1060158                       # Transaction distribution
system.membus.trans_dist::CleanEvict           970949                       # Transaction distribution
system.membus.trans_dist::ReadExReq            812324                       # Transaction distribution
system.membus.trans_dist::ReadExResp           812324                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq       1252445                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      6160645                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                6160645                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    199995328                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               199995328                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples           2064769                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                 2064769    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total             2064769                       # Request fanout histogram
system.membus.reqLayer0.occupancy          8803577000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.8                       # Layer utilization (%)
system.membus.respLayer1.occupancy        11289358000                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              1.0                       # Layer utilization (%)

---------- End Simulation Statistics   ----------