path: root/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.533691                       # Number of seconds simulated
sim_ticks                                533690503000                       # Number of ticks simulated
final_tick                               533690503000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 128085                       # Simulator instruction rate (inst/s)
host_op_rate                                   142888                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               44256929                       # Simulator tick rate (ticks/s)
host_mem_usage                                 275676                       # Number of bytes of host memory used
host_seconds                                 12058.91                       # Real time elapsed on the host
sim_insts                                  1544563023                       # Number of instructions simulated
sim_ops                                    1723073835                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst             47744                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data         143713600                       # Number of bytes read from this memory
system.physmem.bytes_read::total            143761344                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst        47744                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           47744                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     70434112                       # Number of bytes written to this memory
system.physmem.bytes_written::total          70434112                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst                746                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data            2245525                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               2246271                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1100533                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1100533                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst                89460                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data            269282663                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total               269372123                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst           89460                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total              89460                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks         131975577                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total              131975577                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks         131975577                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst               89460                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data           269282663                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              401347700                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                       2246271                       # Number of read requests accepted
system.physmem.writeReqs                      1100533                       # Number of write requests accepted
system.physmem.readBursts                     2246271                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                    1100533                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                143722048                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     39296                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  70432960                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                 143761344                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               70434112                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      614                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0              139609                       # Per bank write bursts
system.physmem.perBankRdBursts::1              136206                       # Per bank write bursts
system.physmem.perBankRdBursts::2              133832                       # Per bank write bursts
system.physmem.perBankRdBursts::3              136344                       # Per bank write bursts
system.physmem.perBankRdBursts::4              135019                       # Per bank write bursts
system.physmem.perBankRdBursts::5              135288                       # Per bank write bursts
system.physmem.perBankRdBursts::6              136231                       # Per bank write bursts
system.physmem.perBankRdBursts::7              136121                       # Per bank write bursts
system.physmem.perBankRdBursts::8              143692                       # Per bank write bursts
system.physmem.perBankRdBursts::9              146373                       # Per bank write bursts
system.physmem.perBankRdBursts::10             144432                       # Per bank write bursts
system.physmem.perBankRdBursts::11             146294                       # Per bank write bursts
system.physmem.perBankRdBursts::12             145666                       # Per bank write bursts
system.physmem.perBankRdBursts::13             146070                       # Per bank write bursts
system.physmem.perBankRdBursts::14             142065                       # Per bank write bursts
system.physmem.perBankRdBursts::15             142415                       # Per bank write bursts
system.physmem.perBankWrBursts::0               69121                       # Per bank write bursts
system.physmem.perBankWrBursts::1               67439                       # Per bank write bursts
system.physmem.perBankWrBursts::2               65729                       # Per bank write bursts
system.physmem.perBankWrBursts::3               66294                       # Per bank write bursts
system.physmem.perBankWrBursts::4               66241                       # Per bank write bursts
system.physmem.perBankWrBursts::5               66403                       # Per bank write bursts
system.physmem.perBankWrBursts::6               67965                       # Per bank write bursts
system.physmem.perBankWrBursts::7               68773                       # Per bank write bursts
system.physmem.perBankWrBursts::8               70328                       # Per bank write bursts
system.physmem.perBankWrBursts::9               70962                       # Per bank write bursts
system.physmem.perBankWrBursts::10              70540                       # Per bank write bursts
system.physmem.perBankWrBursts::11              70927                       # Per bank write bursts
system.physmem.perBankWrBursts::12              70302                       # Per bank write bursts
system.physmem.perBankWrBursts::13              70806                       # Per bank write bursts
system.physmem.perBankWrBursts::14              69598                       # Per bank write bursts
system.physmem.perBankWrBursts::15              69087                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           1                       # Number of times write queue was full causing retry
system.physmem.totGap                    533690432500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                 2246271                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                1100533                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                   1620463                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    446151                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                    135620                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                     43412                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                        10                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                     48877                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                     49049                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                     49091                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                     49066                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                     49073                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                     49089                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                     49084                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                     49051                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                     49094                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                     49119                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                    49113                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                    49182                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                    49203                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                    49260                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                    49489                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    49964                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    50324                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    52085                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    51901                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    51517                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    52884                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    52174                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     2402                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                      373                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                       43                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                       10                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        4                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        3                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        3                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples      2077885                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      103.053834                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean      79.951836                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     184.653120                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::64-65        1660855     79.93%     79.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-129       226890     10.92%     90.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192-193        69105      3.33%     94.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-257        37676      1.81%     95.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320-321        25011      1.20%     97.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-385        12112      0.58%     97.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448-449         8272      0.40%     98.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-513         8103      0.39%     98.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576-577         4494      0.22%     98.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-641         3425      0.16%     98.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704-705         2747      0.13%     99.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-769         2032      0.10%     99.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832-833         1669      0.08%     99.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-897         1441      0.07%     99.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960-961         1240      0.06%     99.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1025         1051      0.05%     99.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088-1089          987      0.05%     99.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152-1153          902      0.04%     99.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216-1217          711      0.03%     99.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280-1281          682      0.03%     99.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344-1345          694      0.03%     99.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408-1409         3096      0.15%     99.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472-1473          406      0.02%     99.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536-1537          291      0.01%     99.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600-1601          190      0.01%     99.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664-1665          185      0.01%     99.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728-1729          205      0.01%     99.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1792-1793          473      0.02%     99.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856-1857          132      0.01%     99.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920-1921          131      0.01%     99.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984-1985          122      0.01%     99.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2048-2049          122      0.01%     99.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112-2113          103      0.00%     99.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176-2177          129      0.01%     99.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240-2241           71      0.00%     99.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304-2305           83      0.00%     99.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368-2369           90      0.00%     99.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2432-2433           83      0.00%     99.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496-2497           94      0.00%     99.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2560-2561           68      0.00%     99.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2624-2625           57      0.00%     99.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688-2689           64      0.00%     99.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2752-2753           70      0.00%     99.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816-2817           60      0.00%     99.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880-2881           55      0.00%     99.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2944-2945           48      0.00%     99.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3008-3009           43      0.00%     99.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3072-3073           58      0.00%     99.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3136-3137           55      0.00%     99.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3200-3201           43      0.00%     99.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3264-3265           33      0.00%     99.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3328-3329           30      0.00%     99.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3392-3393           32      0.00%     99.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456-3457           24      0.00%     99.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3520-3521           28      0.00%     99.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3584-3585           19      0.00%     99.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3648-3649           34      0.00%     99.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3712-3713           24      0.00%     99.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3776-3777           26      0.00%     99.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3840-3841           14      0.00%     99.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3904-3905           19      0.00%     99.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3968-3969           24      0.00%     99.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4032-4033           24      0.00%     99.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4096-4097           17      0.00%     99.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4160-4161           19      0.00%     99.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4224-4225           19      0.00%     99.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4288-4289           21      0.00%     99.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4352-4353           13      0.00%     99.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4416-4417           17      0.00%     99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4480-4481           15      0.00%     99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4544-4545           21      0.00%     99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4608-4609           12      0.00%     99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4672-4673           20      0.00%     99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4736-4737           12      0.00%     99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4800-4801           14      0.00%     99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4864-4865           13      0.00%     99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4928-4929           16      0.00%     99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4992-4993           16      0.00%     99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5056-5057           27      0.00%     99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5120-5121           36      0.00%     99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5184-5185           17      0.00%     99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5248-5249           14      0.00%     99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5312-5313           16      0.00%     99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5376-5377          187      0.01%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5440-5441            3      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5504-5505            6      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5568-5569            8      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5632-5633            2      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5696-5697           12      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5760-5761            7      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5824-5825            2      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5888-5889            1      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5952-5953            2      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6016-6017            4      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6080-6081            9      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6144-6145            3      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6208-6209           13      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6272-6273            6      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6336-6337            2      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6400-6401            5      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6464-6465            1      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6528-6529            4      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6592-6593            9      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6656-6657           34      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6720-6721            1      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6784-6785            5      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6912-6913            5      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6976-6977            1      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7040-7041            3      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7104-7105            1      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7168-7169           26      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7296-7297            2      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7424-7425            4      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7488-7489            1      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7552-7553            4      0.00%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7616-7617            2      0.00%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7680-7681            1      0.00%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7808-7809            4      0.00%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7872-7873            3      0.00%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7936-7937            3      0.00%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8000-8001            1      0.00%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8064-8065            2      0.00%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8128-8129            1      0.00%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8192-8193           83      0.00%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total        2077885                       # Bytes accessed per row activation
system.physmem.totQLat                    32824703500                       # Total ticks spent queuing
system.physmem.totMemAccLat              104040704750                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                  11228285000                       # Total ticks spent in databus transfers
system.physmem.totBankLat                 59987716250                       # Total ticks spent accessing banks
system.physmem.avgQLat                       14616.97                       # Average queueing delay per DRAM burst
system.physmem.avgBankLat                    26712.77                       # Average bank access latency per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  46329.74                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                         269.30                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                         131.97                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                      269.37                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                      131.98                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           3.13                       # Data bus utilization in percentage
system.physmem.busUtilRead                       2.10                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      1.03                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         0.19                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        10.08                       # Average write queue length when enqueuing
system.physmem.readRowHits                     931610                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    336677                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   41.48                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  30.59                       # Row buffer hit rate for writes
system.physmem.avgGap                       159462.71                       # Average gap between requests
system.physmem.pageHitRate                      37.90                       # Row buffer hit rate, read and write combined
system.physmem.prechargeAllPercent               5.89                       # Percentage of time for which DRAM has all the banks in precharge state
system.membus.throughput                    401347580                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq             1419678                       # Transaction distribution
system.membus.trans_dist::ReadResp            1419677                       # Transaction distribution
system.membus.trans_dist::Writeback           1100533                       # Transaction distribution
system.membus.trans_dist::ReadExReq            826593                       # Transaction distribution
system.membus.trans_dist::ReadExResp           826593                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      5593074                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                5593074                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    214195392                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total           214195392                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus              214195392                       # Total data (bytes)
system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy         12924294750                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               2.4                       # Layer utilization (%)
system.membus.respLayer1.occupancy        21079818750                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              3.9                       # Layer utilization (%)
system.cpu.branchPred.lookups               303467870                       # Number of BP lookups
system.cpu.branchPred.condPredicted         249715061                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect          15195903                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups            175178105                       # Number of BTB lookups
system.cpu.branchPred.BTBHits               161776963                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             92.349990                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                17540871                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect                204                       # Number of incorrect RAS predictions.
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                   46                       # Number of system calls
system.cpu.numCycles                       1067381007                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles          299148062                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                     2189533318                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                   303467870                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches          179317834                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     435752088                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                88086251                       # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles              164106751                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                    5                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles           339                       # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines                 289566494                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes               5997594                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples          968963067                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              2.499628                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.206367                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                533211067     55.03%     55.03% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                 25485631      2.63%     57.66% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 39032754      4.03%     61.69% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                 48282665      4.98%     66.67% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                 43767932      4.52%     71.19% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                 46382840      4.79%     75.97% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                 38389210      3.96%     79.94% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                 18960850      1.96%     81.89% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                175450118     18.11%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            968963067                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.284311                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        2.051314                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                331377153                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles             141962670                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 405350137                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles              20317948                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles               69955159                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved             46017147                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                   694                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts             2369104960                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                  2426                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles               69955159                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                354884990                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                70530339                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles          17935                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 400511119                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              73063525                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts             2306250708                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                150920                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                5011927                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents              60136403                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents                4                       # Number of times there has been no free registers
system.cpu.rename.RenamedOperands          2282159345                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups           10649371145                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       9763416611                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups               460                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps            1706319930                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                575839415                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts                404                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts            401                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                 160989021                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads            624749088                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores           220784728                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads          85932352                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores         70842412                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                 2202316968                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded                 440                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                2018777354                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued           4015619                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined       474672323                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined   1127531541                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved            270                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     968963067                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         2.083441                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.906294                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           286087063     29.53%     29.53% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1           153648666     15.86%     45.38% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2           160841319     16.60%     61.98% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3           120316001     12.42%     74.40% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4           123517924     12.75%     87.15% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5            73816539      7.62%     94.76% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6            38325528      3.96%     98.72% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7             9889728      1.02%     99.74% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8             2520299      0.26%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       968963067                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                  895423      3.74%      3.74% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                   5601      0.02%      3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%      3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%      3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%      3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%      3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%      3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%      3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%      3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%      3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%      3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%      3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%      3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%      3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%      3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead               18274862     76.27%     80.03% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite               4786167     19.97%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu            1236899038     61.27%     61.27% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult               924736      0.05%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   2      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt              48      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               1      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc             21      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              8      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead            587872837     29.12%     90.44% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite           193080663      9.56%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total             2018777354                       # Type of FU issued
system.cpu.iq.rate                           1.891337                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                    23962053                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.011870                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         5034495136                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes        2677178912                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses   1957310102                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                 311                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes                694                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses          129                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses             2042739250                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                     157                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads         64569425                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads    138822319                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses       268987                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation       192391                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores     45937683                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads            5                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked       4778132                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles               69955159                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                33483642                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles               1603224                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts          2202317539                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts           7879544                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts             624749088                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts            220784728                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts                378                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                 478707                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                 97428                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents         192391                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect        8138332                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect      9600465                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts             17738797                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts            1988042975                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts             574015030                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts          30734379                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                           131                       # number of nop insts executed
system.cpu.iew.exec_refs                    764217607                       # number of memory reference insts executed
system.cpu.iew.exec_branches                238311346                       # Number of branches executed
system.cpu.iew.exec_stores                  190202577                       # Number of stores executed
system.cpu.iew.exec_rate                     1.862543                       # Inst execution rate
system.cpu.iew.wb_sent                     1965731650                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                    1957310231                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                1295404026                       # num instructions producing a value
system.cpu.iew.wb_consumers                2059270839                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.833750                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.629060                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts       479343339                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls             170                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts          15195240                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    899007908                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.916639                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.718451                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    410513863     45.66%     45.66% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1    193235979     21.49%     67.16% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2     72768373      8.09%     75.25% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     35278706      3.92%     79.18% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4     18862057      2.10%     81.27% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5     30820454      3.43%     84.70% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6     19957331      2.22%     86.92% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7     11398634      1.27%     88.19% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8    106172511     11.81%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    899007908                       # Number of insts commited each cycle
system.cpu.commit.committedInsts           1544563041                       # Number of instructions committed
system.cpu.commit.committedOps             1723073853                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                      660773814                       # Number of memory references committed
system.cpu.commit.loads                     485926769                       # Number of loads committed
system.cpu.commit.membars                          62                       # Number of memory barriers committed
system.cpu.commit.branches                  213462426                       # Number of branches committed
system.cpu.commit.fp_insts                         36                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                1536941841                       # Number of committed integer instructions.
system.cpu.commit.function_calls             13665177                       # Number of function calls committed.
system.cpu.commit.bw_lim_events             106172511                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                   2995251990                       # The number of ROB reads
system.cpu.rob.rob_writes                  4474939624                       # The number of ROB writes
system.cpu.timesIdled                         1152982                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                        98417940                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                  1544563023                       # Number of Instructions Simulated
system.cpu.committedOps                    1723073835                       # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total            1544563023                       # Number of Instructions Simulated
system.cpu.cpi                               0.691057                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.691057                       # CPI: Total CPI of All Threads
system.cpu.ipc                               1.447059                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         1.447059                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads               9956212388                       # number of integer regfile reads
system.cpu.int_regfile_writes              1937181821                       # number of integer regfile writes
system.cpu.fp_regfile_reads                       130                       # number of floating regfile reads
system.cpu.fp_regfile_writes                      139                       # number of floating regfile writes
system.cpu.misc_regfile_reads               737624314                       # number of misc regfile reads
system.cpu.misc_regfile_writes                    124                       # number of misc regfile writes
system.cpu.toL2Bus.throughput              1605146644                       # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq        7709082                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       7709081                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback      3782685                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq      1893414                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp      1893414                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1548                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     22986128                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total          22987676                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        49536                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    856601984                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total      856651520                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus         856651520                       # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy    10475431595                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          2.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy       1294249                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy   14768966243                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          2.8                       # Layer utilization (%)
system.cpu.icache.tags.replacements                22                       # number of replacements
system.cpu.icache.tags.tagsinuse           628.527972                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           289565308                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs               774                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs          374115.385013                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   628.527972                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.306898                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.306898                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst    289565308                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       289565308                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     289565308                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        289565308                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    289565308                       # number of overall hits
system.cpu.icache.overall_hits::total       289565308                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst         1186                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total          1186                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst         1186                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total           1186                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst         1186                       # number of overall misses
system.cpu.icache.overall_misses::total          1186                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst     82924749                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total     82924749                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst     82924749                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total     82924749                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst     82924749                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total     82924749                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    289566494                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    289566494                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    289566494                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    289566494                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    289566494                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    289566494                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000004                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000004                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000004                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000004                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000004                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000004                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69919.687184                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 69919.687184                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 69919.687184                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 69919.687184                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 69919.687184                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 69919.687184                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs          202                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 4                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    50.500000                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst          412                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total          412                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst          412                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total          412                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst          412                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total          412                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst          774                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total          774                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst          774                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total          774                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst          774                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total          774                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     57029751                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total     57029751                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst     57029751                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total     57029751                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst     57029751                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total     57029751                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000003                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000003                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000003                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000003                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000003                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000003                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73681.848837                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73681.848837                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73681.848837                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 73681.848837                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73681.848837                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 73681.848837                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements          2213583                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        31532.604049                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            9247674                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs          2243357                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             4.122248                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle      21623958250                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 14306.578053                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst    20.421352                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 17205.604643                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.436602                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.000623                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.525073                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.962299                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst           27                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data      6289369                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        6289396                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks      3782685                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      3782685                       # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data      1066821                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total      1066821                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst           27                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      7356190                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         7356217                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst           27                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      7356190                       # number of overall hits
system.cpu.l2cache.overall_hits::total        7356217                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst          747                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data      1418939                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total      1419686                       # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       826593                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       826593                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst          747                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data      2245532                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total       2246279                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst          747                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data      2245532                       # number of overall misses
system.cpu.l2cache.overall_misses::total      2246279                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     55980750                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 125563538750                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 125619519500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  76414651500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  76414651500                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst     55980750                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 201978190250                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 202034171000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst     55980750                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 201978190250                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 202034171000                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst          774                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data      7708308                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      7709082                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks      3782685                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      3782685                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data      1893414                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total      1893414                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst          774                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      9601722                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      9602496                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst          774                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      9601722                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      9602496                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.965116                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.184079                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.184158                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.436562                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.436562                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.965116                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.233868                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.233927                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.965116                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.233868                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.233927                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74940.763052                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 88491.146378                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 88484.016536                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 92445.316498                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 92445.316498                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74940.763052                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89946.698711                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 89941.708488                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74940.763052                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89946.698711                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 89941.708488                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks      1100533                       # number of writebacks
system.cpu.l2cache.writebacks::total          1100533                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            1                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data            7                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total            8                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data            7                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total            8                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data            7                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total            8                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          746                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data      1418932                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total      1419678                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       826593                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       826593                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst          746                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data      2245525                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total      2246271                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst          746                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data      2245525                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total      2246271                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     46519250                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 107766607500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 107813126750                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  66030369000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  66030369000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     46519250                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 173796976500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 173843495750                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     46519250                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 173796976500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 173843495750                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.963824                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.184078                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.184157                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.436562                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.436562                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.963824                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.233867                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.233926                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.963824                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.233867                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.233926                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62358.243968                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 75949.099393                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 75941.957789                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79882.564938                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79882.564938                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62358.243968                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77397.034769                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77392.040297                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62358.243968                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77397.034769                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77392.040297                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements           9597625                       # number of replacements
system.cpu.dcache.tags.tagsinuse          4088.040332                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           656028832                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           9601721                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             68.324088                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle        3547188250                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data  4088.040332                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.998057                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.998057                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data    489072771                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       489072771                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data    166955934                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total      166955934                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data           66                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total           66                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data           61                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total           61                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data     656028705                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        656028705                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    656028705                       # number of overall hits
system.cpu.dcache.overall_hits::total       656028705                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data     11514039                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total      11514039                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      5630113                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      5630113                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data            3                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total            3                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data     17144152                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total       17144152                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data     17144152                       # number of overall misses
system.cpu.dcache.overall_misses::total      17144152                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 363445631238                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 363445631238                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 307798034677                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 307798034677                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       225500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total       225500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 671243665915                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 671243665915                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 671243665915                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 671243665915                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    500586810                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    500586810                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data    172586047                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total    172586047                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data           69                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total           69                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data           61                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total           61                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    673172857                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    673172857                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    673172857                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    673172857                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.023001                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.023001                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.032622                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.032622                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.043478                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.043478                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.025468                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.025468                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.025468                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.025468                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31565.433402                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 31565.433402                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54669.956833                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 54669.956833                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 75166.666667                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 75166.666667                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 39152.923161                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 39152.923161                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 39152.923161                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 39152.923161                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs     24614592                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets      3988980                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs           1212230                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets           65133                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    20.305216                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets    61.243609                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      3782685                       # number of writebacks
system.cpu.dcache.writebacks::total           3782685                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data      3805731                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total      3805731                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data      3736699                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total      3736699                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            3                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total            3                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      7542430                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      7542430                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      7542430                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      7542430                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7708308                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      7708308                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1893414                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total      1893414                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      9601722                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      9601722                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      9601722                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      9601722                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 198054864257                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 198054864257                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  89469568032                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  89469568032                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 287524432289                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 287524432289                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 287524432289                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 287524432289                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.015399                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.015399                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.010971                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.010971                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.014263                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.014263                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.014263                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.014263                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25693.688454                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25693.688454                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47253.040292                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47253.040292                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29945.090296                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 29945.090296                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29945.090296                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 29945.090296                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------