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|
---------- Begin Simulation Statistics ----------
sim_seconds 0.787540 # Number of seconds simulated
sim_ticks 787540181500 # Number of ticks simulated
final_tick 787540181500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 265954 # Simulator instruction rate (inst/s)
host_op_rate 286525 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 135604104 # Simulator tick rate (ticks/s)
host_mem_usage 328428 # Number of bytes of host memory used
host_seconds 5807.64 # Real time elapsed on the host
sim_insts 1544563024 # Number of instructions simulated
sim_ops 1664032416 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 65088 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 236130432 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.l2cache.prefetcher 63765312 # Number of bytes read from this memory
system.physmem.bytes_read::total 299960832 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 65088 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 65088 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 104600704 # Number of bytes written to this memory
system.physmem.bytes_written::total 104600704 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 1017 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 3689538 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.l2cache.prefetcher 996333 # Number of read requests responded to by this memory
system.physmem.num_reads::total 4686888 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1634386 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1634386 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 82647 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 299832869 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.l2cache.prefetcher 80967693 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 380883210 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 82647 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 82647 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 132819514 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 132819514 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 132819514 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 82647 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 299832869 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.l2cache.prefetcher 80967693 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 513702723 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 4686888 # Number of read requests accepted
system.physmem.writeReqs 1634386 # Number of write requests accepted
system.physmem.readBursts 4686888 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 1634386 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 299458048 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 502784 # Total number of bytes read from write queue
system.physmem.bytesWritten 104597376 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 299960832 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 104600704 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 7856 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 26 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 302302 # Per bank write bursts
system.physmem.perBankRdBursts::1 301952 # Per bank write bursts
system.physmem.perBankRdBursts::2 285792 # Per bank write bursts
system.physmem.perBankRdBursts::3 288384 # Per bank write bursts
system.physmem.perBankRdBursts::4 288196 # Per bank write bursts
system.physmem.perBankRdBursts::5 285903 # Per bank write bursts
system.physmem.perBankRdBursts::6 281854 # Per bank write bursts
system.physmem.perBankRdBursts::7 277846 # Per bank write bursts
system.physmem.perBankRdBursts::8 294690 # Per bank write bursts
system.physmem.perBankRdBursts::9 300083 # Per bank write bursts
system.physmem.perBankRdBursts::10 291836 # Per bank write bursts
system.physmem.perBankRdBursts::11 298648 # Per bank write bursts
system.physmem.perBankRdBursts::12 299589 # Per bank write bursts
system.physmem.perBankRdBursts::13 298339 # Per bank write bursts
system.physmem.perBankRdBursts::14 293778 # Per bank write bursts
system.physmem.perBankRdBursts::15 289840 # Per bank write bursts
system.physmem.perBankWrBursts::0 103932 # Per bank write bursts
system.physmem.perBankWrBursts::1 101641 # Per bank write bursts
system.physmem.perBankWrBursts::2 99135 # Per bank write bursts
system.physmem.perBankWrBursts::3 99721 # Per bank write bursts
system.physmem.perBankWrBursts::4 98850 # Per bank write bursts
system.physmem.perBankWrBursts::5 98703 # Per bank write bursts
system.physmem.perBankWrBursts::6 102612 # Per bank write bursts
system.physmem.perBankWrBursts::7 104045 # Per bank write bursts
system.physmem.perBankWrBursts::8 105476 # Per bank write bursts
system.physmem.perBankWrBursts::9 104249 # Per bank write bursts
system.physmem.perBankWrBursts::10 101862 # Per bank write bursts
system.physmem.perBankWrBursts::11 102612 # Per bank write bursts
system.physmem.perBankWrBursts::12 102593 # Per bank write bursts
system.physmem.perBankWrBursts::13 102283 # Per bank write bursts
system.physmem.perBankWrBursts::14 104155 # Per bank write bursts
system.physmem.perBankWrBursts::15 102465 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 787540140500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 4686888 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 1634386 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 2728191 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 1051856 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 328268 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 233236 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 157524 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 89904 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 39917 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 24410 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 17981 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 4434 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 1760 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 828 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 462 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 250 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 9 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 24307 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 26803 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 55730 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 73031 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 84525 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 93506 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 99632 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 103284 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 105231 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 105756 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 106392 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 107277 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 108481 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 109650 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 110259 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 109107 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 102133 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 101095 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 4500 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 1820 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 869 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 440 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 230 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 126 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 76 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 37 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 20 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 8 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 5 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 3 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 5 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 3 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 4260550 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 94.836056 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 78.812158 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 102.756680 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 3400540 79.81% 79.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 663329 15.57% 95.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 94665 2.22% 97.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 34624 0.81% 98.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 22478 0.53% 98.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 12365 0.29% 99.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 7339 0.17% 99.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 5272 0.12% 99.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 19938 0.47% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 4260550 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 97975 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 47.757050 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 99.440701 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-255 95549 97.52% 97.52% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::256-511 1198 1.22% 98.75% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::512-767 700 0.71% 99.46% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::768-1023 381 0.39% 99.85% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-1279 109 0.11% 99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1280-1535 28 0.03% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1536-1791 2 0.00% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1792-2047 1 0.00% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-2303 1 0.00% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2304-2559 1 0.00% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2816-3071 2 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::3328-3583 2 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::4608-4863 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 97975 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 97975 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 16.681133 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 16.640632 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 1.211305 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16 70258 71.71% 71.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17 1952 1.99% 73.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18 17579 17.94% 91.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19 5262 5.37% 97.02% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20 1746 1.78% 98.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21 657 0.67% 99.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22 283 0.29% 99.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23 119 0.12% 99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24 69 0.07% 99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::25 29 0.03% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26 11 0.01% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::27 8 0.01% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::31 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 97975 # Writes before turning the bus around for reads
system.physmem.totQLat 162188930459 # Total ticks spent queuing
system.physmem.totMemAccLat 249920780459 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 23395160000 # Total ticks spent in databus transfers
system.physmem.avgQLat 34662.92 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 53412.92 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 380.24 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 132.82 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 380.88 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 132.82 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 4.01 # Data bus utilization in percentage
system.physmem.busUtilRead 2.97 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 1.04 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.44 # Average read queue length when enqueuing
system.physmem.avgWrQLen 24.99 # Average write queue length when enqueuing
system.physmem.readRowHits 1713351 # Number of row buffer hits during reads
system.physmem.writeRowHits 339452 # Number of row buffer hits during writes
system.physmem.readRowHitRate 36.62 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 20.77 # Row buffer hit rate for writes
system.physmem.avgGap 124585.67 # Average gap between requests
system.physmem.pageHitRate 32.52 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 15118214580 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 8035491255 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 16509315060 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 4221095580 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 59433229440.000015 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 64449448560 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 1619596800 # Energy for precharge background per rank (pJ)
system.physmem_0.actPowerDownEnergy 222781261830 # Energy for active power-down per rank (pJ)
system.physmem_0.prePowerDownEnergy 36127794240 # Energy for precharge power-down per rank (pJ)
system.physmem_0.selfRefreshEnergy 16128721335 # Energy for self refresh per rank (pJ)
system.physmem_0.totalEnergy 444435904680 # Total energy per rank (pJ)
system.physmem_0.averagePower 564.334256 # Core power per rank (mW)
system.physmem_0.totalIdleTime 641954026654 # Total Idle time Per DRAM Rank
system.physmem_0.memoryStateTime::IDLE 1425644900 # Time in different power states
system.physmem_0.memoryStateTime::REF 25162536000 # Time in different power states
system.physmem_0.memoryStateTime::SREF 59321643250 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 94080310817 # Time in different power states
system.physmem_0.memoryStateTime::ACT 118997964696 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 488552081837 # Time in different power states
system.physmem_1.actEnergy 15302205240 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 8133295995 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 16898973420 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 4310127900 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 58889273040.000015 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 64896379290 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 1612760640 # Energy for precharge background per rank (pJ)
system.physmem_1.actPowerDownEnergy 219232237770 # Energy for active power-down per rank (pJ)
system.physmem_1.prePowerDownEnergy 35640720960 # Energy for precharge power-down per rank (pJ)
system.physmem_1.selfRefreshEnergy 18160779360 # Energy for self refresh per rank (pJ)
system.physmem_1.totalEnergy 443087552175 # Total energy per rank (pJ)
system.physmem_1.averagePower 562.622143 # Core power per rank (mW)
system.physmem_1.totalIdleTime 640996653350 # Total Idle time Per DRAM Rank
system.physmem_1.memoryStateTime::IDLE 1453270191 # Time in different power states
system.physmem_1.memoryStateTime::REF 24933432000 # Time in different power states
system.physmem_1.memoryStateTime::SREF 67412776000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 92813399032 # Time in different power states
system.physmem_1.memoryStateTime::ACT 120155386459 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 480771917818 # Time in different power states
system.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups 286296319 # Number of BP lookups
system.cpu.branchPred.condPredicted 223413056 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 14631953 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 158681776 # Number of BTB lookups
system.cpu.branchPred.BTBHits 150365310 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 94.759029 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 16643535 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 63 # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups 3038 # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits 1928 # Number of indirect target hits.
system.cpu.branchPred.indirectMisses 1110 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 135 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 46 # Number of system calls
system.cpu.pwrStateResidencyTicks::ON 787540181500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 1575080364 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles 13929690 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 2067600144 # Number of instructions fetch has processed
system.cpu.fetch.Branches 286296319 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 167010773 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 1546402654 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 29288795 # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles 390 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.IcacheWaitRetryStallCycles 943 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 656982335 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 916 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 1574978074 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.406414 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 1.233446 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 492512848 31.27% 31.27% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 465448024 29.55% 60.82% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 101428874 6.44% 67.26% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 515588328 32.74% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 1574978074 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.181766 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.312695 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 74681637 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 577546655 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 849949420 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 58156641 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 14643721 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 42204470 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 713 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 2037236907 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 52506596 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 14643721 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 139754890 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 492363005 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 15806 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 837855661 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 90344991 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 1976429927 # Number of instructions processed by rename
system.cpu.rename.SquashedInsts 26743123 # Number of squashed instructions processed by rename
system.cpu.rename.ROBFullEvents 45374465 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 126519 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 1703162 # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents 29238118 # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands 1985901380 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 9128373257 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 2432925820 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 137 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1674898945 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 311002435 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 176 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 174 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 111413296 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 542580071 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 199306810 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 26873371 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 29046971 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 1948011764 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 231 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 1857503284 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 13502415 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 283979579 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 647409512 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 61 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 1574978074 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.179384 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.151840 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 622116780 39.50% 39.50% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 325952300 20.70% 60.20% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 378187133 24.01% 84.21% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 219716912 13.95% 98.16% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 28998763 1.84% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 6186 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 1574978074 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 166073423 40.98% 40.98% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 2008 0.00% 40.98% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 40.98% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 40.98% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 40.98% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 40.98% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 40.98% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 40.98% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 40.98% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMisc 0 0.00% 40.98% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 40.98% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 40.98% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 40.98% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 40.98% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 40.98% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 40.98% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 40.98% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 40.98% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 40.98% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 40.98% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 40.98% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 40.98% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 40.98% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 40.98% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 40.98% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 40.98% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 40.98% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 40.98% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 40.98% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.98% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 40.98% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 191445503 47.24% 88.22% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 47741848 11.78% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMemRead 19 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMemWrite 31 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 1138255860 61.28% 61.28% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 800923 0.04% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 30 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 22 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 532128426 28.65% 89.97% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 186317966 10.03% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMemRead 33 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMemWrite 24 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 1857503284 # Type of FU issued
system.cpu.iq.rate 1.179307 # Inst issue rate
system.cpu.iq.fu_busy_cnt 405262832 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.218176 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 5708749627 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 2232004447 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 1805721857 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 262 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 240 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 70 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 2262765960 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 156 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 17817152 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 84273737 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 66671 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 13339 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 24459765 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 4534666 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 4848313 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 14643721 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 25440287 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 1476217 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 1948012141 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 542580071 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 199306810 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 169 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 159536 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 1315183 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 13339 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 7701795 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 8704622 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 16406417 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 1827836046 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 516947496 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 29667238 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 146 # number of nop insts executed
system.cpu.iew.exec_refs 698700973 # number of memory reference insts executed
system.cpu.iew.exec_branches 229547821 # Number of branches executed
system.cpu.iew.exec_stores 181753477 # Number of stores executed
system.cpu.iew.exec_rate 1.160472 # Inst execution rate
system.cpu.iew.wb_sent 1808752239 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 1805721927 # cumulative count of insts written-back
system.cpu.iew.wb_producers 1169243033 # num instructions producing a value
system.cpu.iew.wb_consumers 1689661119 # num instructions consuming a value
system.cpu.iew.wb_rate 1.146432 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.691999 # average fanout of values written-back
system.cpu.commit.commitSquashedInsts 258080144 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 14631277 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 1535484809 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.083718 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.009601 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 955186516 62.21% 62.21% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 250636789 16.32% 78.53% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 110101292 7.17% 85.70% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 55286350 3.60% 89.30% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 29268667 1.91% 91.21% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 34069623 2.22% 93.43% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 24728092 1.61% 95.04% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 18117164 1.18% 96.22% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 58090316 3.78% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 1535484809 # Number of insts commited each cycle
system.cpu.commit.committedInsts 1544563042 # Number of instructions committed
system.cpu.commit.committedOps 1664032434 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 633153379 # Number of memory references committed
system.cpu.commit.loads 458306334 # Number of loads committed
system.cpu.commit.membars 62 # Number of memory barriers committed
system.cpu.commit.branches 213462427 # Number of branches committed
system.cpu.commit.fp_insts 36 # Number of committed floating point instructions.
system.cpu.commit.int_insts 1477900421 # Number of committed integer instructions.
system.cpu.commit.function_calls 13665177 # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu 1030178730 61.91% 61.91% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult 700322 0.04% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMisc 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc 3 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead 458306322 27.54% 89.49% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 174847021 10.51% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMemRead 12 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMemWrite 24 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 1664032434 # Class of committed instruction
system.cpu.commit.bw_lim_events 58090316 # number cycles where commit BW limit reached
system.cpu.rob.rob_reads 3399506472 # The number of ROB reads
system.cpu.rob.rob_writes 3883723576 # The number of ROB writes
system.cpu.timesIdled 829 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 102290 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1544563024 # Number of Instructions Simulated
system.cpu.committedOps 1664032416 # Number of Ops (including micro ops) Simulated
system.cpu.cpi 1.019758 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.019758 # CPI: Total CPI of All Threads
system.cpu.ipc 0.980625 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.980625 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 2175817673 # number of integer regfile reads
system.cpu.int_regfile_writes 1261583983 # number of integer regfile writes
system.cpu.fp_regfile_reads 40 # number of floating regfile reads
system.cpu.fp_regfile_writes 52 # number of floating regfile writes
system.cpu.cc_regfile_reads 6965793426 # number of cc regfile reads
system.cpu.cc_regfile_writes 551861251 # number of cc regfile writes
system.cpu.misc_regfile_reads 675850688 # number of misc regfile reads
system.cpu.misc_regfile_writes 124 # number of misc regfile writes
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 17003339 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.963435 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 638067140 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 17003851 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 37.524861 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 82999500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 511.963435 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999929 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999929 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 379 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 1335713311 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 1335713311 # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 469350712 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 469350712 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 168716268 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 168716268 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 57 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 57 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 638066980 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 638066980 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 638066980 # number of overall hits
system.cpu.dcache.overall_hits::total 638066980 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 17417847 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 17417847 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 3869779 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 3869779 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 21287626 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 21287626 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 21287628 # number of overall misses
system.cpu.dcache.overall_misses::total 21287628 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 440481080000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 440481080000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 157197656848 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 157197656848 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 217500 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 217500 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 597678736848 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 597678736848 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 597678736848 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 597678736848 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 486768559 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 486768559 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 2 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 2 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 659354606 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 659354606 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 659354608 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 659354608 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035783 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.035783 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022422 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.022422 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.065574 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.065574 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.032286 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.032286 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.032286 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.032286 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25289.065864 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 25289.065864 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40621.869323 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 40621.869323 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 54375 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 54375 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 28076.345237 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 28076.345237 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 28076.342599 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 28076.342599 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 21218402 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 3791861 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 939506 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 67507 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.584637 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 56.169893 # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks 17003339 # number of writebacks
system.cpu.dcache.writebacks::total 17003339 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3151564 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 3151564 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1132202 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 1132202 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 4283766 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 4283766 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 4283766 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 4283766 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14266283 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 14266283 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737577 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 2737577 # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 17003860 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 17003860 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 17003861 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 17003861 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 354100253000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 354100253000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 121015069211 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 121015069211 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 75000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 75000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 475115322211 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 475115322211 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 475115397211 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 475115397211 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029308 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029308 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015862 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015862 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025789 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.025789 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025789 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.025789 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24820.778685 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24820.778685 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44205.174580 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44205.174580 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 75000 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 75000 # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27941.615740 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 27941.615740 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27941.618507 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 27941.618507 # average overall mshr miss latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 587 # number of replacements
system.cpu.icache.tags.tagsinuse 445.528749 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 656980742 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 1074 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 611713.912477 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 445.528749 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.870173 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.870173 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 487 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 443 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.951172 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 1313965738 # Number of tag accesses
system.cpu.icache.tags.data_accesses 1313965738 # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 656980742 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 656980742 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 656980742 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 656980742 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 656980742 # number of overall hits
system.cpu.icache.overall_hits::total 656980742 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1590 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1590 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1590 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1590 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1590 # number of overall misses
system.cpu.icache.overall_misses::total 1590 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 127348986 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 127348986 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 127348986 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 127348986 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 127348986 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 127348986 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 656982332 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 656982332 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 656982332 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 656982332 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 656982332 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 656982332 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 80093.701887 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 80093.701887 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 80093.701887 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 80093.701887 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 80093.701887 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 80093.701887 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 20708 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 276 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 187 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 9 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs 110.737968 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 30.666667 # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks 587 # number of writebacks
system.cpu.icache.writebacks::total 587 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 515 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 515 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 515 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 515 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 515 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 515 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1075 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 1075 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 1075 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 1075 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 1075 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 1075 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 91881989 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 91881989 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 91881989 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 91881989 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 91881989 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 91881989 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 85471.617674 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 85471.617674 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 85471.617674 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 85471.617674 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 85471.617674 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 85471.617674 # average overall mshr miss latency
system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.prefetcher.num_hwpf_issued 11608007 # number of hwpf issued
system.cpu.l2cache.prefetcher.pfIdentified 11635645 # number of prefetch candidates identified
system.cpu.l2cache.prefetcher.pfBufferHit 18478 # number of redundant prefetches already in prefetch queue
system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu.l2cache.prefetcher.pfSpanPage 4655443 # number of prefetches not generated due to page crossing
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 4648753 # number of replacements
system.cpu.l2cache.tags.tagsinuse 15870.733376 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 13264824 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 4664667 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 2.843681 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 15649.436196 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 221.297180 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.955166 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.013507 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.968673 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1022 130 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024 15784 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::0 6 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::1 105 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::3 19 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 423 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 4048 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 7174 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2624 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1515 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1022 0.007935 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.963379 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 561782498 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 561782498 # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 4829115 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 4829115 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 12153582 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 12153582 # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 1756982 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 1756982 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 57 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 57 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 11509164 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 11509164 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst 57 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 13266146 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 13266203 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 57 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 13266146 # number of overall hits
system.cpu.l2cache.overall_hits::total 13266203 # number of overall hits
system.cpu.l2cache.UpgradeReq_misses::cpu.data 10 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 10 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 980646 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 980646 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1018 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 1018 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 2757059 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 2757059 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 1018 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 3737705 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 3738723 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 1018 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 3737705 # number of overall misses
system.cpu.l2cache.overall_misses::total 3738723 # number of overall misses
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 212000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 212000 # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 104379369500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 104379369500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 90393500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 90393500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 256509677500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 256509677500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 90393500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 360889047000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 360979440500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 90393500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 360889047000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 360979440500 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 4829115 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 4829115 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 12153582 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 12153582 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 10 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 10 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 2737628 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 2737628 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1075 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 1075 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 14266223 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 14266223 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 1075 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 17003851 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 17004926 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 1075 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 17003851 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 17004926 # number of overall (read+write) accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.358210 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.358210 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.946977 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.946977 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.193258 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.193258 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.946977 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.219815 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.219861 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.946977 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.219815 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.219861 # miss rate for overall accesses
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 21200 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 21200 # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 106439.397601 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 106439.397601 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 88795.186640 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 88795.186640 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 93037.427745 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 93037.427745 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 88795.186640 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 96553.646422 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 96551.533906 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 88795.186640 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 96553.646422 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 96551.533906 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 318 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 2 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 159 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.unused_prefetches 58324 # number of HardPF blocks evicted w/o reference
system.cpu.l2cache.writebacks::writebacks 1634386 # number of writebacks
system.cpu.l2cache.writebacks::total 1634386 # number of writebacks
system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3928 # number of ReadExReq MSHR hits
system.cpu.l2cache.ReadExReq_mshr_hits::total 3928 # number of ReadExReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 45589 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total 45589 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 49517 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 49518 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 49517 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 49518 # number of overall MSHR hits
system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 1196489 # number of HardPFReq MSHR misses
system.cpu.l2cache.HardPFReq_mshr_misses::total 1196489 # number of HardPFReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 10 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 10 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 976718 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 976718 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1017 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1017 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 2711470 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 2711470 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 1017 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 3688188 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 3689205 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 1017 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 3688188 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 1196489 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 4885694 # number of overall MSHR misses
system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 84134366845 # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 84134366845 # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 152000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 152000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 98135216000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 98135216000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 84211500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 84211500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 237209473000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 237209473000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 84211500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 335344689000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 335428900500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 84211500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 335344689000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 84134366845 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 419563267345 # number of overall MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.356775 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.356775 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.946047 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.946047 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.190062 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.190062 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.946047 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216903 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.216949 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.946047 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216903 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.287311 # mshr miss rate for overall accesses
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 70317.710271 # average HardPFReq mshr miss latency
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 70317.710271 # average HardPFReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15200 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15200 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 100474.462434 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 100474.462434 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 82803.834808 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 82803.834808 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 87483.716582 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 87483.716582 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 82803.834808 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 90923.968355 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 90921.729885 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 82803.834808 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 90923.968355 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 70317.710271 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 85875.879117 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 34008864 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 17003947 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 21229 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 200156 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 200155 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 14267297 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 6463501 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 12174811 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 3014367 # Transaction distribution
system.cpu.toL2Bus.trans_dist::HardPFReq 1493474 # Transaction distribution
system.cpu.toL2Bus.trans_dist::HardPFResp 16 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 10 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 10 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 2737628 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 2737628 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 1075 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 14266223 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2736 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 51011077 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 51013813 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 106304 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2176461184 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 2176567488 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 6142243 # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic 104601728 # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples 23147163 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.009565 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.097331 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 22925769 99.04% 99.04% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 221393 0.96% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 23147163 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 34008359033 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 4.3 # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy 24049 # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 1612497 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 25505785487 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 3.2 # Layer utilization (%)
system.membus.snoop_filter.tot_requests 9335651 # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests 4669993 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 3710005 # Transaction distribution
system.membus.trans_dist::WritebackDirty 1634386 # Transaction distribution
system.membus.trans_dist::CleanEvict 3014367 # Transaction distribution
system.membus.trans_dist::UpgradeReq 10 # Transaction distribution
system.membus.trans_dist::ReadExReq 976882 # Transaction distribution
system.membus.trans_dist::ReadExResp 976882 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 3710006 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14022538 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 14022538 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 404561472 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 404561472 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples 4686898 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 4686898 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 4686898 # Request fanout histogram
system.membus.reqLayer0.occupancy 17643111757 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 2.2 # Layer utilization (%)
system.membus.respLayer1.occupancy 25454576781 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 3.2 # Layer utilization (%)
---------- End Simulation Statistics ----------
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