path: root/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.767804                       # Number of seconds simulated
sim_ticks                                767803843500                       # Number of ticks simulated
final_tick                               767803843500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 188017                       # Simulator instruction rate (inst/s)
host_op_rate                                   202560                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               93463451                       # Simulator tick rate (ticks/s)
host_mem_usage                                 313392                       # Number of bytes of host memory used
host_seconds                                  8215.02                       # Real time elapsed on the host
sim_insts                                  1544563024                       # Number of instructions simulated
sim_ops                                    1664032416                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst             65216                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data         235320384                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.l2cache.prefetcher     63711040                       # Number of bytes read from this memory
system.physmem.bytes_read::total            299096640                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst        65216                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           65216                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks    104697344                       # Number of bytes written to this memory
system.physmem.bytes_written::total         104697344                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst               1019                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data            3676881                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.l2cache.prefetcher       995485                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               4673385                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1635896                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1635896                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst                84938                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data            306485030                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.l2cache.prefetcher     82978277                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total               389548245                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst           84938                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total              84938                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks         136359495                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total              136359495                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks         136359495                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst               84938                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data           306485030                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.l2cache.prefetcher     82978277                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              525907740                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                       4673385                       # Number of read requests accepted
system.physmem.writeReqs                      1635896                       # Number of write requests accepted
system.physmem.readBursts                     4673385                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                    1635896                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                298598336                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                    498304                       # Total number of bytes read from write queue
system.physmem.bytesWritten                 104693696                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                 299096640                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys              104697344                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                     7786                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                      26                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0              301126                       # Per bank write bursts
system.physmem.perBankRdBursts::1              298685                       # Per bank write bursts
system.physmem.perBankRdBursts::2              284250                       # Per bank write bursts
system.physmem.perBankRdBursts::3              287696                       # Per bank write bursts
system.physmem.perBankRdBursts::4              287908                       # Per bank write bursts
system.physmem.perBankRdBursts::5              285921                       # Per bank write bursts
system.physmem.perBankRdBursts::6              280645                       # Per bank write bursts
system.physmem.perBankRdBursts::7              277366                       # Per bank write bursts
system.physmem.perBankRdBursts::8              293768                       # Per bank write bursts
system.physmem.perBankRdBursts::9              299240                       # Per bank write bursts
system.physmem.perBankRdBursts::10             292091                       # Per bank write bursts
system.physmem.perBankRdBursts::11             297828                       # Per bank write bursts
system.physmem.perBankRdBursts::12             299005                       # Per bank write bursts
system.physmem.perBankRdBursts::13             298032                       # Per bank write bursts
system.physmem.perBankRdBursts::14             293386                       # Per bank write bursts
system.physmem.perBankRdBursts::15             288652                       # Per bank write bursts
system.physmem.perBankWrBursts::0              103980                       # Per bank write bursts
system.physmem.perBankWrBursts::1              101811                       # Per bank write bursts
system.physmem.perBankWrBursts::2               99205                       # Per bank write bursts
system.physmem.perBankWrBursts::3               99712                       # Per bank write bursts
system.physmem.perBankWrBursts::4               99000                       # Per bank write bursts
system.physmem.perBankWrBursts::5               99026                       # Per bank write bursts
system.physmem.perBankWrBursts::6              102693                       # Per bank write bursts
system.physmem.perBankWrBursts::7              104157                       # Per bank write bursts
system.physmem.perBankWrBursts::8              105172                       # Per bank write bursts
system.physmem.perBankWrBursts::9              104159                       # Per bank write bursts
system.physmem.perBankWrBursts::10             102137                       # Per bank write bursts
system.physmem.perBankWrBursts::11             102620                       # Per bank write bursts
system.physmem.perBankWrBursts::12             102863                       # Per bank write bursts
system.physmem.perBankWrBursts::13             102594                       # Per bank write bursts
system.physmem.perBankWrBursts::14             104213                       # Per bank write bursts
system.physmem.perBankWrBursts::15             102497                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    767803802500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                 4673385                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                1635896                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                   2761676                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                   1029435                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                    325938                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                    231496                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                    148985                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                     81565                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                     37573                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                     23615                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                     17937                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      4209                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                     1691                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      802                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      456                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      219                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    25842                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    28487                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    55926                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    73202                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    85102                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    93551                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                   100017                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                   103625                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                   105684                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                   106315                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                   107141                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                   108142                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                   109489                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                   111392                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                   111204                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                   103853                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                   101152                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                   100444                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     3026                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                     1226                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      559                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      257                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      119                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                       52                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                       23                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                       15                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        5                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        3                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples      4243508                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean       95.037234                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean      78.939445                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     102.771916                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127        3380789     79.67%     79.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255       664864     15.67%     95.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        95298      2.25%     97.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511        35170      0.83%     98.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639        22966      0.54%     98.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767        12163      0.29%     99.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         7344      0.17%     99.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         5345      0.13%     99.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        19569      0.46%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total        4243508                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         97753                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        47.727814                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      100.001834                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-255           95363     97.56%     97.56% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::256-511          1154      1.18%     98.74% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::512-767           681      0.70%     99.43% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::768-1023          412      0.42%     99.85% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-1279          112      0.11%     99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1280-1535           14      0.01%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1536-1791            8      0.01%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1792-2047            2      0.00%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-2303            1      0.00%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2560-2815            2      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2816-3071            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::3328-3583            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::3840-4095            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::4096-4351            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           97753                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         97753                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        16.734412                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       16.690766                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        1.259650                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16              68350     69.92%     69.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17               1981      2.03%     71.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18              18352     18.77%     90.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19               5702      5.83%     96.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20               2016      2.06%     98.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21                741      0.76%     99.37% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22                311      0.32%     99.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23                155      0.16%     99.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24                 75      0.08%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::25                 43      0.04%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26                 16      0.02%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::27                  8      0.01%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::29                  2      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::35                  1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           97753                       # Writes before turning the bus around for reads
system.physmem.totQLat                   128478496877                       # Total ticks spent queuing
system.physmem.totMemAccLat              215958478127                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                  23327995000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       27537.41                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  46287.41                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                         388.90                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                         136.35                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                      389.55                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                      136.36                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           4.10                       # Data bus utilization in percentage
system.physmem.busUtilRead                       3.04                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      1.07                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.42                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        24.85                       # Average write queue length when enqueuing
system.physmem.readRowHits                    1710736                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    347188                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   36.67                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  21.22                       # Row buffer hit rate for writes
system.physmem.avgGap                       121694.34                       # Average gap between requests
system.physmem.pageHitRate                      32.66                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                15941658600                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                 8698325625                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy               17967846000                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy               5246104320                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy            50149101600                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy           414557114310                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy            97034832000                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             609594982455                       # Total energy per rank (pJ)
system.physmem_0.averagePower              793.947771                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   158900831773                       # Time in different power states
system.physmem_0.memoryStateTime::REF     25638600000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT    583262954477                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                16139254320                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                 8806140750                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy               18423607800                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy               5354132400                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy            50149101600                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy           410075734410                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           100965867000                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             609913838280                       # Total energy per rank (pJ)
system.physmem_1.averagePower              794.363055                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   165472936005                       # Time in different power states
system.physmem_1.memoryStateTime::REF     25638600000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT    576690946995                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu.branchPred.lookups               286292198                       # Number of BP lookups
system.cpu.branchPred.condPredicted         223415085                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect          14631198                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups            158639381                       # Number of BTB lookups
system.cpu.branchPred.BTBHits               150355883                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             94.778410                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                16642674                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect                 61                       # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups            3027                       # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits               1888                       # Number of indirect target hits.
system.cpu.branchPred.indirectMisses             1139                       # Number of indirect misses.
system.cpu.branchPredindirectMispredicted          136                       # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.walks                         0                       # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                   46                       # Number of system calls
system.cpu.numCycles                       1535607688                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles           13928755                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                     2067573004                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                   286292198                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches          167000445                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                    1506957925                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                29287239                       # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles                  183                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.IcacheWaitRetryStallCycles          992                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                 656968436                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                   958                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples         1535531474                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              1.442524                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             1.228151                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                453078112     29.51%     29.51% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                465445913     30.31%     59.82% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                101427094      6.61%     66.42% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                515580355     33.58%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total           1535531474                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.186436                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        1.346420                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 74706893                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles             538056624                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 849925630                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles              58199384                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles               14642943                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved             42203258                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                   730                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts             2037275151                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts              52500118                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles               14642943                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                139803593                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles               457092273                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles          13624                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 837854747                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              86124294                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts             1976468269                       # Number of instructions processed by rename
system.cpu.rename.SquashedInsts              26746953                       # Number of squashed instructions processed by rename
system.cpu.rename.ROBFullEvents              45300136                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                 126625                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents                1588286                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents               25069373                       # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands          1985943496                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            9128568325                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       2432995559                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups               145                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps            1674898945                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                311044551                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts                174                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts            175                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                 111502635                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads            542585286                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores           199312070                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads          26927303                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores         29234152                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                 1948047142                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded                 231                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                1857492479                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued          13497229                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined       284014957                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined    647584155                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved             61                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples    1535531474                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         1.209674                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.150607                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           582548107     37.94%     37.94% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1           326134076     21.24%     59.18% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2           378190631     24.63%     83.81% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3           219663672     14.31%     98.11% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            28988815      1.89%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5                6173      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total      1535531474                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu               166038532     40.99%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                   1976      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead              191466165     47.27%     88.26% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite              47567904     11.74%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu            1138257084     61.28%     61.28% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult               800920      0.04%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt              31      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc             22      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead            532121986     28.65%     89.97% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite           186312436     10.03%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total             1857492479                       # Type of FU issued
system.cpu.iq.rate                           1.209614                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                   405074577                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.218076                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         5669087998                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes        2232075127                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses   1805719723                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                 240                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes                252                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses           72                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses             2262566922                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                     134                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads         17809734                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads     84278952                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses        66732                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        13280                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores     24465025                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads      4505677                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked       4870984                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles               14642943                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                25375759                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles               1295309                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts          1948047519                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts             542585286                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts            199312070                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts                169                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                 159534                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents               1134383                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          13280                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect        7701154                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect      8705181                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts             16406335                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts            1827826675                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts             516940315                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts          29665804                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                           146                       # number of nop insts executed
system.cpu.iew.exec_refs                    698692225                       # number of memory reference insts executed
system.cpu.iew.exec_branches                229542687                       # Number of branches executed
system.cpu.iew.exec_stores                  181751910                       # Number of stores executed
system.cpu.iew.exec_rate                     1.190295                       # Inst execution rate
system.cpu.iew.wb_sent                     1808754463                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                    1805719795                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                1169207800                       # num instructions producing a value
system.cpu.iew.wb_consumers                1689618799                       # num instructions consuming a value
system.cpu.iew.wb_rate                       1.175899                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.691995                       # average fanout of values written-back
system.cpu.commit.commitSquashedInsts       258113026                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls             170                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts          14630522                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples   1496036001                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.112294                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.028030                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    915722932     61.21%     61.21% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1    250663462     16.76%     77.97% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2    110062832      7.36%     85.32% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     55282207      3.70%     89.02% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4     29306686      1.96%     90.98% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5     34079757      2.28%     93.25% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6     24721963      1.65%     94.91% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7     18129916      1.21%     96.12% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8     58066246      3.88%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total   1496036001                       # Number of insts commited each cycle
system.cpu.commit.committedInsts           1544563042                       # Number of instructions committed
system.cpu.commit.committedOps             1664032434                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                      633153379                       # Number of memory references committed
system.cpu.commit.loads                     458306334                       # Number of loads committed
system.cpu.commit.membars                          62                       # Number of memory barriers committed
system.cpu.commit.branches                  213462427                       # Number of branches committed
system.cpu.commit.fp_insts                         36                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                1477900421                       # Number of committed integer instructions.
system.cpu.commit.function_calls             13665177                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu       1030178730     61.91%     61.91% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult          700322      0.04%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv                0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd              0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp              0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt              0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv              0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc            3      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead       458306334     27.54%     89.49% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite      174847045     10.51%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total        1664032434                       # Class of committed instruction
system.cpu.commit.bw_lim_events              58066246                       # number cycles where commit BW limit reached
system.cpu.rob.rob_reads                   3360114616                       # The number of ROB reads
system.cpu.rob.rob_writes                  3883791528                       # The number of ROB writes
system.cpu.timesIdled                             840                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                           76214                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                  1544563024                       # Number of Instructions Simulated
system.cpu.committedOps                    1664032416                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               0.994202                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.994202                       # CPI: Total CPI of All Threads
system.cpu.ipc                               1.005832                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         1.005832                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads               2175815840                       # number of integer regfile reads
system.cpu.int_regfile_writes              1261595611                       # number of integer regfile writes
system.cpu.fp_regfile_reads                        42                       # number of floating regfile reads
system.cpu.fp_regfile_writes                       54                       # number of floating regfile writes
system.cpu.cc_regfile_reads                6965778765                       # number of cc regfile reads
system.cpu.cc_regfile_writes                551854660                       # number of cc regfile writes
system.cpu.misc_regfile_reads               675853701                       # number of misc regfile reads
system.cpu.misc_regfile_writes                    124                       # number of misc regfile writes
system.cpu.dcache.tags.replacements          17003710                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.964650                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           638076364                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs          17004222                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             37.524584                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle          78426500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.964650                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999931                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999931                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0          395                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          117                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses        1335728390                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses       1335728390                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data    469357603                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       469357603                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data    168718615                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total      168718615                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data           57                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total           57                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data           61                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total           61                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data     638076218                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        638076218                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    638076218                       # number of overall hits
system.cpu.dcache.overall_hits::total       638076218                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data     17418310                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total      17418310                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      3867432                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      3867432                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data            2                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total            2                       # number of SoftPFReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data            4                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total            4                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data     21285742                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total       21285742                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data     21285744                       # number of overall misses
system.cpu.dcache.overall_misses::total      21285744                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 411945425500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 411945425500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 148954509432                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 148954509432                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       196500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total       196500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 560899934932                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 560899934932                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 560899934932                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 560899934932                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    486775913                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    486775913                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data    172586047                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total    172586047                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data            2                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total            2                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data           61                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total           61                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data           61                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total           61                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    659361960                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    659361960                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    659361962                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    659361962                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.035783                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.035783                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.022409                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.022409                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data            1                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total            1                       # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.065574                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.065574                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.032282                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.032282                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.032282                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.032282                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23650.137442                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 23650.137442                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38515.094624                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 38515.094624                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        49125                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        49125                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 26350.969345                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 26350.969345                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 26350.966869                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 26350.966869                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs     20530392                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets      3397643                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs            943594                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets           67194                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    21.757654                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets    50.564678                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks     17003710                       # number of writebacks
system.cpu.dcache.writebacks::total          17003710                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data      3151672                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total      3151672                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1129843                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total      1129843                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            4                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total            4                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      4281515                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      4281515                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      4281515                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      4281515                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data     14266638                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total     14266638                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data      2737589                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total      2737589                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data            1                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total            1                       # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data     17004227                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total     17004227                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data     17004228                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total     17004228                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 331755520500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 331755520500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 115729212265                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 115729212265                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data        68000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total        68000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 447484732765                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 447484732765                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 447484800765                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 447484800765                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.029308                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.029308                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015862                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015862                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.500000                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.500000                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.025789                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.025789                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.025789                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.025789                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23253.938349                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23253.938349                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42274.136938                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42274.136938                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        68000                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        68000                       # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26316.087921                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 26316.087921                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26316.090373                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 26316.090373                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements               589                       # number of replacements
system.cpu.icache.tags.tagsinuse           444.836642                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           656966815                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs              1075                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs          611131.920930                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   444.836642                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.868822                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.868822                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          486                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           31                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1           14                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4          441                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.949219                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses        1313937945                       # Number of tag accesses
system.cpu.icache.tags.data_accesses       1313937945                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst    656966815                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       656966815                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     656966815                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        656966815                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    656966815                       # number of overall hits
system.cpu.icache.overall_hits::total       656966815                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst         1620                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total          1620                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst         1620                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total           1620                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst         1620                       # number of overall misses
system.cpu.icache.overall_misses::total          1620                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst     98788987                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total     98788987                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst     98788987                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total     98788987                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst     98788987                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total     98788987                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    656968435                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    656968435                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    656968435                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    656968435                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    656968435                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    656968435                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000002                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000002                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000002                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000002                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000002                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000002                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 60980.856173                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 60980.856173                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 60980.856173                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 60980.856173                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 60980.856173                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 60980.856173                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs        17260                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets          439                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs               183                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               8                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    94.316940                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets    54.875000                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.writebacks::writebacks          589                       # number of writebacks
system.cpu.icache.writebacks::total               589                       # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst          544                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total          544                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst          544                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total          544                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst          544                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total          544                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst         1076                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total         1076                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst         1076                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total         1076                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst         1076                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total         1076                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     73759491                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total     73759491                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst     73759491                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total     73759491                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst     73759491                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total     73759491                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000002                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000002                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000002                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68549.712825                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68549.712825                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68549.712825                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 68549.712825                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68549.712825                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 68549.712825                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.prefetcher.num_hwpf_issued     11611376                       # number of hwpf issued
system.cpu.l2cache.prefetcher.pfIdentified     11640224                       # number of prefetch candidates identified
system.cpu.l2cache.prefetcher.pfBufferHit        19566                       # number of redundant prefetches already in prefetch queue
system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu.l2cache.prefetcher.pfSpanPage      4656640                       # number of prefetches not generated due to page crossing
system.cpu.l2cache.tags.replacements          4706089                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        16099.754607                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs           22829126                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs          4722015                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             4.834615                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle      54111720000                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 13098.345143                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data     2.290302                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher  2999.119162                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.799460                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.000140                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.183052                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.982651                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1022          829                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024        15097                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::0            2                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::1          636                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::3          191                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0          453                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1         2943                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         4353                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5523                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4         1825                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1022     0.050598                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.921448                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses        552242422                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses       552242422                       # Number of data accesses
system.cpu.l2cache.WritebackDirty_hits::writebacks      4833112                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total      4833112                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks     12149903                       # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total     12149903                       # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data      1757087                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total      1757087                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst           56                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total           56                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data     11522367                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total     11522367                       # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst           56                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data     13279454                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total        13279510                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst           56                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data     13279454                       # number of overall hits
system.cpu.l2cache.overall_hits::total       13279510                       # number of overall hits
system.cpu.l2cache.UpgradeReq_misses::cpu.data            6                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total            6                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       980546                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       980546                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         1020                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total         1020                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data      2744222                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total      2744222                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst         1020                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data      3724768                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total       3725788                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         1020                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data      3724768                       # number of overall misses
system.cpu.l2cache.overall_misses::total      3725788                       # number of overall misses
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       121000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total       121000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  99083213500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  99083213500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     72272000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total     72272000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 234079710000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 234079710000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst     72272000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 333162923500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 333235195500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst     72272000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 333162923500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 333235195500                       # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks      4833112                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total      4833112                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks     12149903                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total     12149903                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data            6                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total            6                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data      2737633                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total      2737633                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         1076                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total         1076                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data     14266589                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total     14266589                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst         1076                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data     17004222                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total     17005298                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst         1076                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data     17004222                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total     17005298                       # number of overall (read+write) accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data            1                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.358173                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.358173                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.947955                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.947955                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.192353                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.192353                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.947955                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.219050                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.219096                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.947955                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.219050                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.219096                       # miss rate for overall accesses
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 20166.666667                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 20166.666667                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 101049.021158                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 101049.021158                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 70854.901961                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 70854.901961                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85299.115742                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85299.115742                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70854.901961                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89445.281827                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 89440.192383                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70854.901961                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89445.281827                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 89440.192383                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs           53                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                1                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs           53                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.unused_prefetches            56900                       # number of HardPF blocks evicted w/o reference
system.cpu.l2cache.writebacks::writebacks      1635896                       # number of writebacks
system.cpu.l2cache.writebacks::total          1635896                       # number of writebacks
system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data         3915                       # number of ReadExReq MSHR hits
system.cpu.l2cache.ReadExReq_mshr_hits::total         3915                       # number of ReadExReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            1                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data        45253                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total        45253                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data        49168                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total        49169                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data        49168                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total        49169                       # number of overall MSHR hits
system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher      1145204                       # number of HardPFReq MSHR misses
system.cpu.l2cache.HardPFReq_mshr_misses::total      1145204                       # number of HardPFReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            6                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total            6                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       976631                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       976631                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         1019                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total         1019                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data      2698969                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total      2698969                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         1019                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data      3675600                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total      3676619                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         1019                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data      3675600                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher      1145204                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total      4821823                       # number of overall MSHR misses
system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher  72434619378                       # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_latency::total  72434619378                       # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data        85000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total        85000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  92854351000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  92854351000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     66085000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     66085000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 215091513500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 215091513500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     66085000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 307945864500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 308011949500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     66085000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 307945864500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher  72434619378                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 380446568878                       # number of overall MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.356743                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.356743                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.947026                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.947026                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.189181                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.189181                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.947026                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.216158                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.216204                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.947026                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.216158                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.283548                       # mshr miss rate for overall accesses
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 63250.407244                       # average HardPFReq mshr miss latency
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 63250.407244                       # average HardPFReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14166.666667                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14166.666667                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95076.186400                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95076.186400                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64852.796860                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64852.796860                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79693.954803                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79693.954803                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64852.796860                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83781.114512                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 83775.868400                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64852.796860                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83781.114512                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 63250.407244                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78900.981823                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.snoop_filter.tot_requests     34009604                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests     17004315                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests        21284                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops      2918086                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops      2899299                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops        18787                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp      14267664                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty      6469008                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean     12171187                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict      5770180                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::HardPFReq      1436414                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::HardPFResp            9                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq            6                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp            6                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq      2737633                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp      2737633                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq         1076                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq     14266589                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         2740                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     51012175                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total          51014915                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       106496                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   2176508224                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total         2176614720                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                     8842499                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples     25847794                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        0.114446                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.320627                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0           22908415     88.63%     88.63% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1            2920592     11.30%     99.93% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2              18787      0.07%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total       25847794                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy    34009101529                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          4.4                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy        13538                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy       1613498                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy   25506339992                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          3.3                       # Layer utilization (%)
system.membus.trans_dist::ReadResp            3696594                       # Transaction distribution
system.membus.trans_dist::WritebackDirty      1635896                       # Transaction distribution
system.membus.trans_dist::CleanEvict          3001813                       # Transaction distribution
system.membus.trans_dist::UpgradeReq                6                       # Transaction distribution
system.membus.trans_dist::ReadExReq            976790                       # Transaction distribution
system.membus.trans_dist::ReadExResp           976790                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq       3696595                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port     13984484                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total               13984484                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    403793920                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               403793920                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoop_fanout::samples           9311100                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                 9311100    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total             9311100                       # Request fanout histogram
system.membus.reqLayer0.occupancy         17657610874                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               2.3                       # Layer utilization (%)
system.membus.respLayer1.occupancy        25413256779                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              3.3                       # Layer utilization (%)

---------- End Simulation Statistics   ----------