path: root/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.770752                       # Number of seconds simulated
sim_ticks                                770752376500                       # Number of ticks simulated
final_tick                               770752376500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 147248                       # Simulator instruction rate (inst/s)
host_op_rate                                   158637                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               73478006                       # Simulator tick rate (ticks/s)
host_mem_usage                                 329736                       # Number of bytes of host memory used
host_seconds                                 10489.57                       # Real time elapsed on the host
sim_insts                                  1544563024                       # Number of instructions simulated
sim_ops                                    1664032416                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 770752376500                       # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst             65664                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data         236002624                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.l2cache.prefetcher     63781504                       # Number of bytes read from this memory
system.physmem.bytes_read::total            299849792                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst        65664                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           65664                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks    104607936                       # Number of bytes written to this memory
system.physmem.bytes_written::total         104607936                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst               1026                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data            3687541                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.l2cache.prefetcher       996586                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               4685153                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1634499                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1634499                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst                85195                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data            306197725                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.l2cache.prefetcher     82752264                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total               389035183                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst           85195                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total              85195                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks         135721847                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total              135721847                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks         135721847                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst               85195                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data           306197725                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.l2cache.prefetcher     82752264                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              524757030                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                       4685154                       # Number of read requests accepted
system.physmem.writeReqs                      1634499                       # Number of write requests accepted
system.physmem.readBursts                     4685154                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                    1634499                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                299347712                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                    502144                       # Total number of bytes read from write queue
system.physmem.bytesWritten                 104604544                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                 299849856                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys              104607936                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                     7846                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                      26                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0              301314                       # Per bank write bursts
system.physmem.perBankRdBursts::1              301808                       # Per bank write bursts
system.physmem.perBankRdBursts::2              285079                       # Per bank write bursts
system.physmem.perBankRdBursts::3              287721                       # Per bank write bursts
system.physmem.perBankRdBursts::4              288732                       # Per bank write bursts
system.physmem.perBankRdBursts::5              286480                       # Per bank write bursts
system.physmem.perBankRdBursts::6              281880                       # Per bank write bursts
system.physmem.perBankRdBursts::7              278193                       # Per bank write bursts
system.physmem.perBankRdBursts::8              293719                       # Per bank write bursts
system.physmem.perBankRdBursts::9              299847                       # Per bank write bursts
system.physmem.perBankRdBursts::10             291529                       # Per bank write bursts
system.physmem.perBankRdBursts::11             297903                       # Per bank write bursts
system.physmem.perBankRdBursts::12             299405                       # Per bank write bursts
system.physmem.perBankRdBursts::13             299387                       # Per bank write bursts
system.physmem.perBankRdBursts::14             294305                       # Per bank write bursts
system.physmem.perBankRdBursts::15             290006                       # Per bank write bursts
system.physmem.perBankWrBursts::0              103629                       # Per bank write bursts
system.physmem.perBankWrBursts::1              101748                       # Per bank write bursts
system.physmem.perBankWrBursts::2               99222                       # Per bank write bursts
system.physmem.perBankWrBursts::3               99944                       # Per bank write bursts
system.physmem.perBankWrBursts::4               98990                       # Per bank write bursts
system.physmem.perBankWrBursts::5               98822                       # Per bank write bursts
system.physmem.perBankWrBursts::6              102440                       # Per bank write bursts
system.physmem.perBankWrBursts::7              104048                       # Per bank write bursts
system.physmem.perBankWrBursts::8              105134                       # Per bank write bursts
system.physmem.perBankWrBursts::9              103994                       # Per bank write bursts
system.physmem.perBankWrBursts::10             101818                       # Per bank write bursts
system.physmem.perBankWrBursts::11             102570                       # Per bank write bursts
system.physmem.perBankWrBursts::12             102850                       # Per bank write bursts
system.physmem.perBankWrBursts::13             102376                       # Per bank write bursts
system.physmem.perBankWrBursts::14             104237                       # Per bank write bursts
system.physmem.perBankWrBursts::15             102624                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    770752366000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                 4685154                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                1634499                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                   2776424                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                   1031022                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                    327510                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                    229431                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                    146630                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                     80164                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                     37430                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                     23802                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                     17710                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      4122                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                     1619                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      771                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      426                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      239                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        7                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    25690                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    28168                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    56471                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    73716                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    85142                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    93999                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                   100116                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                   103738                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                   105456                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                   106103                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                   107040                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                   108147                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                   109209                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                   110723                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                   110766                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                   103820                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                   100949                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                   100270                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     2888                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                     1126                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      505                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      211                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      109                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                       44                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                       28                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                       14                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        8                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples      4255173                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean       94.931559                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean      78.862227                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     102.833954                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127        3394354     79.77%     79.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255       663703     15.60%     95.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        94226      2.21%     97.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511        35436      0.83%     98.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639        22765      0.53%     98.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767        12171      0.29%     99.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         7342      0.17%     99.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         5345      0.13%     99.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        19831      0.47%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total        4255173                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         97794                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        47.827914                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev       99.473591                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-127           93707     95.82%     95.82% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::128-255          1671      1.71%     97.53% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::256-383           768      0.79%     98.31% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::384-511           406      0.42%     98.73% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::512-639           365      0.37%     99.10% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::640-767           337      0.34%     99.45% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::768-895           234      0.24%     99.69% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::896-1023          165      0.17%     99.86% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-1151           89      0.09%     99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1152-1279           24      0.02%     99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1280-1407           12      0.01%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1408-1535            4      0.00%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1664-1791            3      0.00%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-2175            1      0.00%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2176-2303            2      0.00%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2304-2431            1      0.00%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2688-2815            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2944-3071            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::3456-3583            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::3584-3711            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::3968-4095            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           97794                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         97794                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        16.713152                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       16.671812                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        1.223073                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16              68724     70.27%     70.27% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17               1896      1.94%     72.21% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18              18671     19.09%     91.31% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19               5634      5.76%     97.07% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20               1729      1.77%     98.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21                613      0.63%     99.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22                266      0.27%     99.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23                147      0.15%     99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24                 67      0.07%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::25                 30      0.03%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26                  9      0.01%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::27                  6      0.01%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28                  1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::38                  1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           97794                       # Writes before turning the bus around for reads
system.physmem.totQLat                   128325813562                       # Total ticks spent queuing
system.physmem.totMemAccLat              216025338562                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                  23386540000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       27435.83                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  46185.83                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                         388.38                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                         135.72                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                      389.04                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                      135.72                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           4.09                       # Data bus utilization in percentage
system.physmem.busUtilRead                       3.03                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      1.06                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.42                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        24.86                       # Average write queue length when enqueuing
system.physmem.readRowHits                    1715091                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    341475                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   36.67                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  20.89                       # Row buffer hit rate for writes
system.physmem.avgGap                       121961.18                       # Average gap between requests
system.physmem.pageHitRate                      32.58                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                15989112720                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                 8724218250                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy               18025846800                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy               5241069360                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy            50341337280                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy           417928675995                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy            95843265750                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             612093526155                       # Total energy per rank (pJ)
system.physmem_0.averagePower              794.157652                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   156909498029                       # Time in different power states
system.physmem_0.memoryStateTime::REF     25736880000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT    588099785971                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                16179556680                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                 8828131125                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy               18455494200                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy               5349602880                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy            50341337280                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy           412908393870                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           100247038500                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             612309554535                       # Total energy per rank (pJ)
system.physmem_1.averagePower              794.437909                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   164276600328                       # Time in different power states
system.physmem_1.memoryStateTime::REF     25736880000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT    580733308672                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.pwrStateResidencyTicks::UNDEFINED 770752376500                       # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups               286275195                       # Number of BP lookups
system.cpu.branchPred.condPredicted         223398341                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect          14628424                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups            157667483                       # Number of BTB lookups
system.cpu.branchPred.BTBHits               150349199                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             95.358406                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                16643020                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect                 63                       # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups            3069                       # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits               1906                       # Number of indirect target hits.
system.cpu.branchPred.indirectMisses             1163                       # Number of indirect misses.
system.cpu.branchPredindirectMispredicted          137                       # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 770752376500                       # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 770752376500                       # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 770752376500                       # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 770752376500                       # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks                         0                       # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                   46                       # Number of system calls
system.cpu.pwrStateResidencyTicks::ON    770752376500                       # Cumulative time (in ticks) in various power states
system.cpu.numCycles                       1541504754                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles           13925502                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                     2067484101                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                   286275195                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches          166994125                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                    1512857238                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                29281631                       # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles                  279                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.IcacheWaitRetryStallCycles         1018                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                 656940019                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                   946                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples         1541424852                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              1.436951                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             1.229037                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                459011037     29.78%     29.78% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                465435057     30.20%     59.97% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                101419068      6.58%     66.55% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                515559690     33.45%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total           1541424852                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.185712                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        1.341212                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 74709451                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles             544021839                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 849845592                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles              58207832                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles               14640138                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved             42201657                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                   726                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts             2037180089                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts              52484609                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles               14640138                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                139806563                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles               462600801                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles          15884                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 837785307                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              86576159                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts             1976384850                       # Number of instructions processed by rename
system.cpu.rename.SquashedInsts              26739549                       # Number of squashed instructions processed by rename
system.cpu.rename.ROBFullEvents              45323653                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                 126929                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents                1602638                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents               25499860                       # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands          1985860548                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            9128169124                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       2432875929                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups               133                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps            1674898945                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                310961603                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts                175                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts            175                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                 111534180                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads            542566077                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores           199303375                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads          26892889                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores         29237160                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                 1947969517                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded                 231                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                1857492369                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued          13496690                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined       283937332                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined    647289356                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved             61                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples    1541424852                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         1.205049                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.150817                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           588435916     38.17%     38.17% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1           326131475     21.16%     59.33% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2           378210554     24.54%     83.87% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3           219654013     14.25%     98.12% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            28986723      1.88%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5                6171      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total      1541424852                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu               166021321     40.99%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                   1993      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead              191489776     47.28%     88.26% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite              47539480     11.74%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu            1138243662     61.28%     61.28% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult               800931      0.04%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt              29      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc             22      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead            532135699     28.65%     89.97% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite           186312026     10.03%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total             1857492369                       # Type of FU issued
system.cpu.iq.rate                           1.204986                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                   405052570                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.218064                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         5674958613                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes        2231919871                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses   1805704142                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                 237                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes                230                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses           70                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses             2262544806                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                     133                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads         17811536                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads     84259743                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses        66618                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        13244                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores     24456330                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads      4512030                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked       4891489                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles               14640138                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                25364964                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles               1346928                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts          1947969899                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts             542566077                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts            199303375                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts                169                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                 159350                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents               1186169                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          13244                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect        7699482                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect      8703162                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts             16402644                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts            1827831567                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts             516957415                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts          29660802                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                           151                       # number of nop insts executed
system.cpu.iew.exec_refs                    698708795                       # number of memory reference insts executed
system.cpu.iew.exec_branches                229542425                       # Number of branches executed
system.cpu.iew.exec_stores                  181751380                       # Number of stores executed
system.cpu.iew.exec_rate                     1.185745                       # Inst execution rate
system.cpu.iew.wb_sent                     1808736265                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                    1805704212                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                1169174812                       # num instructions producing a value
system.cpu.iew.wb_consumers                1689572222                       # num instructions consuming a value
system.cpu.iew.wb_rate                       1.171391                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.691995                       # average fanout of values written-back
system.cpu.commit.commitSquashedInsts       258041892                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls             170                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts          14627747                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples   1501940299                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.107922                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.025263                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    921653315     61.36%     61.36% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1    250636600     16.69%     78.05% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2    110060462      7.33%     85.38% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     55269176      3.68%     89.06% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4     29319156      1.95%     91.01% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5     34080655      2.27%     93.28% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6     24723288      1.65%     94.93% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7     18133421      1.21%     96.13% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8     58064226      3.87%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total   1501940299                       # Number of insts commited each cycle
system.cpu.commit.committedInsts           1544563042                       # Number of instructions committed
system.cpu.commit.committedOps             1664032434                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                      633153379                       # Number of memory references committed
system.cpu.commit.loads                     458306334                       # Number of loads committed
system.cpu.commit.membars                          62                       # Number of memory barriers committed
system.cpu.commit.branches                  213462427                       # Number of branches committed
system.cpu.commit.fp_insts                         36                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                1477900421                       # Number of committed integer instructions.
system.cpu.commit.function_calls             13665177                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu       1030178730     61.91%     61.91% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult          700322      0.04%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv                0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd              0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp              0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt              0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv              0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc            3      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead       458306334     27.54%     89.49% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite      174847045     10.51%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total        1664032434                       # Class of committed instruction
system.cpu.commit.bw_lim_events              58064226                       # number cycles where commit BW limit reached
system.cpu.rob.rob_reads                   3365949800                       # The number of ROB reads
system.cpu.rob.rob_writes                  3883638365                       # The number of ROB writes
system.cpu.timesIdled                             837                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                           79902                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                  1544563024                       # Number of Instructions Simulated
system.cpu.committedOps                    1664032416                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               0.998020                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.998020                       # CPI: Total CPI of All Threads
system.cpu.ipc                               1.001984                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         1.001984                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads               2175818987                       # number of integer regfile reads
system.cpu.int_regfile_writes              1261576435                       # number of integer regfile writes
system.cpu.fp_regfile_reads                        42                       # number of floating regfile reads
system.cpu.fp_regfile_writes                       52                       # number of floating regfile writes
system.cpu.cc_regfile_reads                6965775009                       # number of cc regfile reads
system.cpu.cc_regfile_writes                551856674                       # number of cc regfile writes
system.cpu.misc_regfile_reads               675846934                       # number of misc regfile reads
system.cpu.misc_regfile_writes                    124                       # number of misc regfile writes
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 770752376500                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements          17003150                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.964340                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           638065664                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs          17003662                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             37.525191                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle          79206500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.964340                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999930                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999930                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0          406                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          106                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses        1335709608                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses       1335709608                       # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 770752376500                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data    469347574                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       469347574                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data    168717937                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total      168717937                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data           57                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total           57                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data           61                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total           61                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data     638065511                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        638065511                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    638065511                       # number of overall hits
system.cpu.dcache.overall_hits::total       638065511                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data     17419228                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total      17419228                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      3868110                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      3868110                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data            2                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total            2                       # number of SoftPFReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data            4                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total            4                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data     21287338                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total       21287338                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data     21287340                       # number of overall misses
system.cpu.dcache.overall_misses::total      21287340                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 416423435500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 416423435500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 150253086257                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 150253086257                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       199500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total       199500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 566676521757                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 566676521757                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 566676521757                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 566676521757                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    486766802                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    486766802                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data    172586047                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total    172586047                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data            2                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total            2                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data           61                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total           61                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data           61                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total           61                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    659352849                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    659352849                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    659352851                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    659352851                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.035786                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.035786                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.022413                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.022413                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data            1                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total            1                       # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.065574                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.065574                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.032285                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.032285                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.032285                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.032285                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23905.963887                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 23905.963887                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38844.057242                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 38844.057242                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        49875                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        49875                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 26620.356277                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 26620.356277                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 26620.353776                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 26620.353776                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs     20685246                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets      3452781                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs            946049                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets           67233                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    21.864878                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets    51.355450                       # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks     17003150                       # number of writebacks
system.cpu.dcache.writebacks::total          17003150                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data      3153076                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total      3153076                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1130592                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total      1130592                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            4                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total            4                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      4283668                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      4283668                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      4283668                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      4283668                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data     14266152                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total     14266152                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data      2737518                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total      2737518                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data            1                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total            1                       # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data     17003670                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total     17003670                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data     17003671                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total     17003671                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 335207977500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 335207977500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 116679674033                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 116679674033                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data        69000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total        69000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 451887651533                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 451887651533                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 451887720533                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 451887720533                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.029308                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.029308                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015862                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015862                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.500000                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.500000                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.025788                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.025788                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.025788                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.025788                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23496.733913                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23496.733913                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42622.431718                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42622.431718                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        69000                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        69000                       # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26575.889295                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 26575.889295                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26575.891790                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 26575.891790                       # average overall mshr miss latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 770752376500                       # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements               588                       # number of replacements
system.cpu.icache.tags.tagsinuse           444.874436                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           656938405                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs              1074                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs          611674.492551                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   444.874436                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.868895                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.868895                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          486                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           29                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1           14                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4          443                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.949219                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses        1313881106                       # Number of tag accesses
system.cpu.icache.tags.data_accesses       1313881106                       # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 770752376500                       # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst    656938405                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       656938405                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     656938405                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        656938405                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    656938405                       # number of overall hits
system.cpu.icache.overall_hits::total       656938405                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst         1611                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total          1611                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst         1611                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total           1611                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst         1611                       # number of overall misses
system.cpu.icache.overall_misses::total          1611                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    103785485                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    103785485                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    103785485                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    103785485                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    103785485                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    103785485                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    656940016                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    656940016                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    656940016                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    656940016                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    656940016                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    656940016                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000002                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000002                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000002                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000002                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000002                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000002                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64423.019863                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 64423.019863                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 64423.019863                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 64423.019863                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 64423.019863                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 64423.019863                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs        16825                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets          586                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs               185                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets              10                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    90.945946                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets    58.600000                       # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks          588                       # number of writebacks
system.cpu.icache.writebacks::total               588                       # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst          535                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total          535                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst          535                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total          535                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst          535                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total          535                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst         1076                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total         1076                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst         1076                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total         1076                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst         1076                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total         1076                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     75943989                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total     75943989                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst     75943989                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total     75943989                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst     75943989                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total     75943989                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000002                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000002                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000002                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70579.915428                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70579.915428                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70579.915428                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 70579.915428                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70579.915428                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 70579.915428                       # average overall mshr miss latency
system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 770752376500                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.prefetcher.num_hwpf_issued     11612917                       # number of hwpf issued
system.cpu.l2cache.prefetcher.pfIdentified     11641367                       # number of prefetch candidates identified
system.cpu.l2cache.prefetcher.pfBufferHit        19112                       # number of redundant prefetches already in prefetch queue
system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu.l2cache.prefetcher.pfSpanPage      4655505                       # number of prefetches not generated due to page crossing
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 770752376500                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements          4647068                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        15866.736257                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs           13267029                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs          4662976                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             2.845185                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 15646.626307                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher   220.109950                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.954994                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.013434                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.968429                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1022          143                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024        15765                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::0            5                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::1          115                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::3           23                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0          463                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1         4068                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         7095                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2886                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4         1253                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1022     0.008728                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.962219                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses        561777243                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses       561777243                       # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 770752376500                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks      4835234                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total      4835234                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks     12147319                       # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total     12147319                       # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data      1756866                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total      1756866                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst           49                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total           49                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data     11510992                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total     11510992                       # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst           49                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data     13267858                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total        13267907                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst           49                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data     13267858                       # number of overall hits
system.cpu.l2cache.overall_hits::total       13267907                       # number of overall hits
system.cpu.l2cache.UpgradeReq_misses::cpu.data            9                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total            9                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       980689                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       980689                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         1027                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total         1027                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data      2755115                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total      2755115                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst         1027                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data      3735804                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total       3736831                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         1027                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data      3735804                       # number of overall misses
system.cpu.l2cache.overall_misses::total      3736831                       # number of overall misses
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       191500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total       191500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 100034737999                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 100034737999                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     74500500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total     74500500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 237611587999                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 237611587999                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst     74500500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 337646325998                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 337720826498                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst     74500500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 337646325998                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 337720826498                       # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks      4835234                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total      4835234                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks     12147319                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total     12147319                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data            9                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total            9                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data      2737555                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total      2737555                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         1076                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total         1076                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data     14266107                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total     14266107                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst         1076                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data     17003662                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total     17004738                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst         1076                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data     17003662                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total     17004738                       # number of overall (read+write) accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data            1                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.358235                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.358235                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.954461                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.954461                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.193123                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.193123                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.954461                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.219706                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.219752                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.954461                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.219706                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.219752                       # miss rate for overall accesses
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 21277.777778                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 21277.777778                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 102004.547822                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 102004.547822                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 72541.869523                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 72541.869523                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86243.800349                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86243.800349                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72541.869523                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 90381.167213                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 90376.264406                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72541.869523                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 90381.167213                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 90376.264406                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs          351                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                5                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs    70.200000                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.unused_prefetches            58014                       # number of HardPF blocks evicted w/o reference
system.cpu.l2cache.writebacks::writebacks      1634499                       # number of writebacks
system.cpu.l2cache.writebacks::total          1634499                       # number of writebacks
system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data         3902                       # number of ReadExReq MSHR hits
system.cpu.l2cache.ReadExReq_mshr_hits::total         3902                       # number of ReadExReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data        45668                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total        45668                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data        49570                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total        49570                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data        49570                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total        49570                       # number of overall MSHR hits
system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher      1198249                       # number of HardPFReq MSHR misses
system.cpu.l2cache.HardPFReq_mshr_misses::total      1198249                       # number of HardPFReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            9                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total            9                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       976787                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       976787                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         1027                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total         1027                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data      2709447                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total      2709447                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         1027                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data      3686234                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total      3687261                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         1027                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data      3686234                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher      1198249                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total      4885510                       # number of overall MSHR misses
system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher  73218164638                       # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_latency::total  73218164638                       # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       137500                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       137500                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  93806338999                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  93806338999                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     68350500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     68350500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 218529981999                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 218529981999                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     68350500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 312336320998                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 312404671498                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     68350500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 312336320998                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher  73218164638                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 385622836136                       # number of overall MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.356810                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.356810                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.954461                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.954461                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.189922                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.189922                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.954461                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.216791                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.216837                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.954461                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.216791                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.287303                       # mshr miss rate for overall accesses
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 61104.298554                       # average HardPFReq mshr miss latency
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 61104.298554                       # average HardPFReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15277.777778                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15277.777778                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 96035.613700                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 96035.613700                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66553.554041                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66553.554041                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 80654.828088                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 80654.828088                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66553.554041                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84730.465021                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84725.402270                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66553.554041                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84730.465021                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 61104.298554                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78931.951042                       # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests     34008488                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests     17003756                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests        21185                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops       201663                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops       201662                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            1                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 770752376500                       # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp      14267181                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty      6469733                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean     12168504                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict      3012569                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::HardPFReq      1490485                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::HardPFResp           11                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq            9                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp            9                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq      2737555                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp      2737555                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq         1076                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq     14266107                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         2738                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     51010503                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total          51013241                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       106368                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   2176436672                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total         2176543040                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                     6137564                       # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic             104608640                       # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples     23142303                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        0.009630                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.097659                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0           22919446     99.04%     99.04% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1             222856      0.96%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  1      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total       23142303                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy    34007983525                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          4.4                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy        16538                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy       1611000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy   25505500994                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          3.3                       # Layer utilization (%)
system.membus.snoop_filter.tot_requests       9332231                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests      4668264                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 770752376500                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp            3708204                       # Transaction distribution
system.membus.trans_dist::WritebackDirty      1634499                       # Transaction distribution
system.membus.trans_dist::CleanEvict          3012569                       # Transaction distribution
system.membus.trans_dist::UpgradeReq                9                       # Transaction distribution
system.membus.trans_dist::ReadExReq            976948                       # Transaction distribution
system.membus.trans_dist::ReadExResp           976948                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq       3708206                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port     14017383                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total               14017383                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    404457664                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               404457664                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples           4685163                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                 4685163    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total             4685163                       # Request fanout histogram
system.membus.reqLayer0.occupancy         17662405597                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               2.3                       # Layer utilization (%)
system.membus.respLayer1.occupancy        25476549560                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              3.3                       # Layer utilization (%)

---------- End Simulation Statistics   ----------