path: root/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.771725                       # Number of seconds simulated
sim_ticks                                771725169000                       # Number of ticks simulated
final_tick                               771725169000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 137392                       # Simulator instruction rate (inst/s)
host_op_rate                                   148019                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               68646343                       # Simulator tick rate (ticks/s)
host_mem_usage                                 311812                       # Number of bytes of host memory used
host_seconds                                 11242.04                       # Real time elapsed on the host
sim_insts                                  1544563024                       # Number of instructions simulated
sim_ops                                    1664032416                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst             66304                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data         238609216                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.l2cache.prefetcher     63286144                       # Number of bytes read from this memory
system.physmem.bytes_read::total            301961664                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst        66304                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           66304                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks    104822848                       # Number of bytes written to this memory
system.physmem.bytes_written::total         104822848                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst               1036                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data            3728269                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.l2cache.prefetcher       988846                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               4718151                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1637857                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1637857                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst                85917                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data            309189366                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.l2cache.prefetcher     82006065                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total               391281347                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst           85917                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total              85917                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks         135829246                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total              135829246                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks         135829246                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst               85917                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data           309189366                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.l2cache.prefetcher     82006065                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              527110594                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                       4718151                       # Number of read requests accepted
system.physmem.writeReqs                      1637857                       # Number of write requests accepted
system.physmem.readBursts                     4718151                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                    1637857                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                301519872                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                    441792                       # Total number of bytes read from write queue
system.physmem.bytesWritten                 104820544                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                 301961664                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys              104822848                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                     6903                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                      19                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0              296668                       # Per bank write bursts
system.physmem.perBankRdBursts::1              294562                       # Per bank write bursts
system.physmem.perBankRdBursts::2              288307                       # Per bank write bursts
system.physmem.perBankRdBursts::3              292737                       # Per bank write bursts
system.physmem.perBankRdBursts::4              290232                       # Per bank write bursts
system.physmem.perBankRdBursts::5              289394                       # Per bank write bursts
system.physmem.perBankRdBursts::6              285167                       # Per bank write bursts
system.physmem.perBankRdBursts::7              280683                       # Per bank write bursts
system.physmem.perBankRdBursts::8              297292                       # Per bank write bursts
system.physmem.perBankRdBursts::9              302920                       # Per bank write bursts
system.physmem.perBankRdBursts::10             295430                       # Per bank write bursts
system.physmem.perBankRdBursts::11             301815                       # Per bank write bursts
system.physmem.perBankRdBursts::12             303322                       # Per bank write bursts
system.physmem.perBankRdBursts::13             302849                       # Per bank write bursts
system.physmem.perBankRdBursts::14             297025                       # Per bank write bursts
system.physmem.perBankRdBursts::15             292845                       # Per bank write bursts
system.physmem.perBankWrBursts::0              103942                       # Per bank write bursts
system.physmem.perBankWrBursts::1              102053                       # Per bank write bursts
system.physmem.perBankWrBursts::2               99317                       # Per bank write bursts
system.physmem.perBankWrBursts::3               99871                       # Per bank write bursts
system.physmem.perBankWrBursts::4               99169                       # Per bank write bursts
system.physmem.perBankWrBursts::5               98963                       # Per bank write bursts
system.physmem.perBankWrBursts::6              102735                       # Per bank write bursts
system.physmem.perBankWrBursts::7              104389                       # Per bank write bursts
system.physmem.perBankWrBursts::8              105226                       # Per bank write bursts
system.physmem.perBankWrBursts::9              104532                       # Per bank write bursts
system.physmem.perBankWrBursts::10             102159                       # Per bank write bursts
system.physmem.perBankWrBursts::11             102806                       # Per bank write bursts
system.physmem.perBankWrBursts::12             103028                       # Per bank write bursts
system.physmem.perBankWrBursts::13             102702                       # Per bank write bursts
system.physmem.perBankWrBursts::14             104263                       # Per bank write bursts
system.physmem.perBankWrBursts::15             102666                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    771725022000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                 4718151                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                1637857                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                   2774626                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                   1044189                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                    331696                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                    233512                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                    153773                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                     84990                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                     39149                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                     23715                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                     18258                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      4255                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                     1688                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      754                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      411                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      226                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        6                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    22760                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    24545                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    59860                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    75448                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    85202                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    93103                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    99273                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                   103279                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                   105460                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                   106422                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                   106536                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                   107239                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                   108154                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                   110632                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                   113547                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                   106733                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                   103419                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                   101598                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     2778                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                     1044                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      449                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      193                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                       83                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                       37                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                       13                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        4                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        3                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        5                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples      4287400                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean       94.775232                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean      78.917076                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     101.448471                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127        3413764     79.62%     79.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255       675374     15.75%     95.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        96809      2.26%     97.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511        35249      0.82%     98.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639        22885      0.53%     98.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767        12087      0.28%     99.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         7187      0.17%     99.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         5043      0.12%     99.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        19002      0.44%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total        4287400                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         98767                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        47.700609                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::gmean       32.313411                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev       98.282358                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-127           94950     96.14%     96.14% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::128-255          1367      1.38%     97.52% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::256-383           770      0.78%     98.30% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::384-511           428      0.43%     98.73% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::512-639           356      0.36%     99.09% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::640-767           374      0.38%     99.47% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::768-895           247      0.25%     99.72% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::896-1023          145      0.15%     99.87% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-1151           66      0.07%     99.94% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1152-1279           31      0.03%     99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1280-1407           13      0.01%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1408-1535            9      0.01%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1536-1663            1      0.00%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1792-1919            1      0.00%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1920-2047            2      0.00%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2688-2815            1      0.00%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2944-3071            2      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::3072-3199            2      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::3200-3327            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::3328-3455            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           98767                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         98767                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        16.582674                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       16.549780                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        1.086524                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16              73305     74.22%     74.22% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17               1806      1.83%     76.05% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18              18343     18.57%     94.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19               3630      3.68%     98.30% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20                937      0.95%     99.24% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21                387      0.39%     99.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22                162      0.16%     99.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23                107      0.11%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24                 60      0.06%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::25                 22      0.02%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26                  6      0.01%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::27                  1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::30                  1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           98767                       # Writes before turning the bus around for reads
system.physmem.totQLat                   132285118194                       # Total ticks spent queuing
system.physmem.totMemAccLat              220621018194                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                  23556240000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       28078.57                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  46828.57                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                         390.71                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                         135.83                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                      391.28                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                      135.83                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           4.11                       # Data bus utilization in percentage
system.physmem.busUtilRead                       3.05                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      1.06                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.44                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        24.97                       # Average write queue length when enqueuing
system.physmem.readRowHits                    1709073                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    352585                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   36.28                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  21.53                       # Row buffer hit rate for writes
system.physmem.avgGap                       121416.62                       # Average gap between requests
system.physmem.pageHitRate                      32.47                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                16073195040                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                 8770096500                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy               18077007000                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy               5251294800                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy            50404907280                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy           410674128390                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           102790850250                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             612041479260                       # Total energy per rank (pJ)
system.physmem_0.averagePower              793.088667                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   168453702129                       # Time in different power states
system.physmem_0.memoryStateTime::REF     25769380000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT    577496605871                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                16339027320                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                 8915143875                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy               18669222000                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy               5361163200                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy            50404907280                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy           412008151545                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           101620654500                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             613318269720                       # Total energy per rank (pJ)
system.physmem_1.averagePower              794.743144                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   166509885283                       # Time in different power states
system.physmem_1.memoryStateTime::REF     25769380000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT    579440435717                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu.branchPred.lookups               286277860                       # Number of BP lookups
system.cpu.branchPred.condPredicted         223409255                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect          14633591                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups            157407621                       # Number of BTB lookups
system.cpu.branchPred.BTBHits               150346120                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             95.513876                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                16641206                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect                 65                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.walks                         0                       # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                   46                       # Number of system calls
system.cpu.numCycles                       1543450339                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles           13927699                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                     2067517377                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                   286277860                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches          166987326                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                    1514795150                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                29291799                       # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles                  180                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.IcacheWaitRetryStallCycles          907                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                 656942032                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                   957                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples         1543369835                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              1.435149                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             1.229340                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                460957271     29.87%     29.87% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                465455811     30.16%     60.03% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                101360614      6.57%     66.59% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                515596139     33.41%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total           1543369835                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.185479                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        1.339543                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 74619350                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles             545977788                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 850086533                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles              58040967                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles               14645197                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved             42200501                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                   754                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts             2037190940                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts              52475133                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles               14645197                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                139685845                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles               464851768                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles          13523                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 837895691                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              86277811                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts             1976364426                       # Number of instructions processed by rename
system.cpu.rename.SquashedInsts              26735694                       # Number of squashed instructions processed by rename
system.cpu.rename.ROBFullEvents              45105241                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                 125505                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents                1481556                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents               25500508                       # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands          1985835865                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            9128071192                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       2432849079                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups               136                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps            1674898945                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                310936920                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts                149                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts            140                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                 111342876                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads            542549398                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores           199301403                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads          26926926                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores         29153523                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                 1947926711                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded                 208                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                1857446823                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued          13498178                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined       283894503                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined    646939215                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved             38                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples    1543369835                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         1.203501                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.151095                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           590630846     38.27%     38.27% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1           325771475     21.11%     59.38% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2           378267234     24.51%     83.89% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3           219666416     14.23%     98.12% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            29027688      1.88%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5                6176      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total      1543369835                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu               166059149     40.99%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                   1996      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead              191393147     47.24%     88.23% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite              47682914     11.77%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu            1138268714     61.28%     61.28% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult               801071      0.04%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt              28      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc             22      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead            532058987     28.64%     89.97% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite           186318001     10.03%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total             1857446823                       # Type of FU issued
system.cpu.iq.rate                           1.203438                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                   405137206                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.218115                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         5676898637                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes        2231834122                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses   1805736851                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                 228                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes                232                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses           68                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses             2262583902                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                     127                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads         17817639                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads     84243064                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses        66651                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        13168                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores     24454358                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads      4525889                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked       4805394                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles               14645197                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                25323327                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles               1332663                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts          1947926995                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts             542549398                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts            199301403                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts                146                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                 158839                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents               1172731                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          13168                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect        7701738                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect      8706499                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts             16408237                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts            1827783249                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts             516881888                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts          29663574                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                            76                       # number of nop insts executed
system.cpu.iew.exec_refs                    698636146                       # number of memory reference insts executed
system.cpu.iew.exec_branches                229555717                       # Number of branches executed
system.cpu.iew.exec_stores                  181754258                       # Number of stores executed
system.cpu.iew.exec_rate                     1.184219                       # Inst execution rate
system.cpu.iew.wb_sent                     1808767141                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                    1805736919                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                1169322951                       # num instructions producing a value
system.cpu.iew.wb_consumers                1689713401                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.169935                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.692024                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts       258002520                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls             170                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts          14632889                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples   1503882923                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.106491                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.024391                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    923604765     61.41%     61.41% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1    250635322     16.67%     78.08% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2    110056363      7.32%     85.40% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     55280526      3.68%     89.07% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4     29292132      1.95%     91.02% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5     34092515      2.27%     93.29% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6     24716046      1.64%     94.93% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7     18126603      1.21%     96.14% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8     58078651      3.86%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total   1503882923                       # Number of insts commited each cycle
system.cpu.commit.committedInsts           1544563042                       # Number of instructions committed
system.cpu.commit.committedOps             1664032434                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                      633153379                       # Number of memory references committed
system.cpu.commit.loads                     458306334                       # Number of loads committed
system.cpu.commit.membars                          62                       # Number of memory barriers committed
system.cpu.commit.branches                  213462427                       # Number of branches committed
system.cpu.commit.fp_insts                         36                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                1477900421                       # Number of committed integer instructions.
system.cpu.commit.function_calls             13665177                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu       1030178730     61.91%     61.91% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult          700322      0.04%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv                0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd              0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp              0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt              0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv              0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc            3      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead       458306334     27.54%     89.49% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite      174847045     10.51%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total        1664032434                       # Class of committed instruction
system.cpu.commit.bw_lim_events              58078651                       # number cycles where commit BW limit reached
system.cpu.rob.rob_reads                   3367838627                       # The number of ROB reads
system.cpu.rob.rob_writes                  3883562090                       # The number of ROB writes
system.cpu.timesIdled                             851                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                           80504                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                  1544563024                       # Number of Instructions Simulated
system.cpu.committedOps                    1664032416                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               0.999280                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.999280                       # CPI: Total CPI of All Threads
system.cpu.ipc                               1.000721                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         1.000721                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads               2175739809                       # number of integer regfile reads
system.cpu.int_regfile_writes              1261583749                       # number of integer regfile writes
system.cpu.fp_regfile_reads                        38                       # number of floating regfile reads
system.cpu.fp_regfile_writes                       50                       # number of floating regfile writes
system.cpu.cc_regfile_reads                6965641029                       # number of cc regfile reads
system.cpu.cc_regfile_writes                551880821                       # number of cc regfile writes
system.cpu.misc_regfile_reads               675853491                       # number of misc regfile reads
system.cpu.misc_regfile_writes                    124                       # number of misc regfile writes
system.cpu.dcache.tags.replacements          17005885                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.964949                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           638186886                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs          17006397                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             37.526284                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle          78340000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.964949                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999932                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999932                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0          423                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1           89                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses        1335687679                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses       1335687679                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data    469400845                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       469400845                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data    168785923                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total      168785923                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data           57                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total           57                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data           61                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total           61                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data     638186768                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        638186768                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    638186768                       # number of overall hits
system.cpu.dcache.overall_hits::total       638186768                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data     17353625                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total      17353625                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      3800124                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      3800124                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data            2                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total            2                       # number of SoftPFReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data            4                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total            4                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data     21153749                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total       21153749                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data     21153751                       # number of overall misses
system.cpu.dcache.overall_misses::total      21153751                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 417050356298                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 417050356298                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 149886013526                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 149886013526                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       204500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total       204500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 566936369824                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 566936369824                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 566936369824                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 566936369824                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    486754470                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    486754470                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data    172586047                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total    172586047                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data            2                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total            2                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data           61                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total           61                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data           61                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total           61                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    659340517                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    659340517                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    659340519                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    659340519                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.035652                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.035652                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.022019                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.022019                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data            1                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total            1                       # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.065574                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.065574                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.032083                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.032083                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.032083                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.032083                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24032.463321                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 24032.463321                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39442.400702                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 39442.400702                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        51125                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        51125                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 26800.751480                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 26800.751480                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 26800.748946                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 26800.748946                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs     20736521                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets      3309459                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs            945396                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets           67047                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    21.934217                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets    49.360285                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      4830628                       # number of writebacks
system.cpu.dcache.writebacks::total           4830628                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data      3084713                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total      3084713                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1062640                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total      1062640                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            4                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total            4                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      4147353                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      4147353                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      4147353                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      4147353                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data     14268912                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total     14268912                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data      2737484                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total      2737484                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data            1                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total            1                       # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data     17006396                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total     17006396                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data     17006397                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total     17006397                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 328919129806                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 328919129806                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 115124697729                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 115124697729                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data        67750                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total        67750                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 444043827535                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 444043827535                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 444043895285                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 444043895285                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.029314                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.029314                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015862                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015862                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.500000                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.500000                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.025793                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.025793                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.025793                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.025793                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23051.451281                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23051.451281                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42054.929902                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42054.929902                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        67750                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        67750                       # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26110.401495                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 26110.401495                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26110.403943                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 26110.403943                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements               589                       # number of replacements
system.cpu.icache.tags.tagsinuse           446.078018                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           656940406                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs              1077                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs          609972.521820                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   446.078018                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.871246                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.871246                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          488                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           31                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1           15                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4          442                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.953125                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses        1313885139                       # Number of tag accesses
system.cpu.icache.tags.data_accesses       1313885139                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst    656940406                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       656940406                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     656940406                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        656940406                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    656940406                       # number of overall hits
system.cpu.icache.overall_hits::total       656940406                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst         1625                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total          1625                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst         1625                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total           1625                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst         1625                       # number of overall misses
system.cpu.icache.overall_misses::total          1625                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    105016775                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    105016775                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    105016775                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    105016775                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    105016775                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    105016775                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    656942031                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    656942031                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    656942031                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    656942031                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    656942031                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    656942031                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000002                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000002                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000002                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000002                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000002                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000002                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64625.707692                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 64625.707692                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 64625.707692                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 64625.707692                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 64625.707692                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 64625.707692                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs        17596                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets          547                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs               191                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               9                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    92.125654                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets    60.777778                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst          548                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total          548                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst          548                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total          548                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst          548                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total          548                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst         1077                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total         1077                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst         1077                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total         1077                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst         1077                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total         1077                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     76192959                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total     76192959                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst     76192959                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total     76192959                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst     76192959                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total     76192959                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000002                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000002                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000002                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70745.551532                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70745.551532                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70745.551532                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 70745.551532                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70745.551532                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 70745.551532                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.prefetcher.num_hwpf_issued     10938258                       # number of hwpf issued
system.cpu.l2cache.prefetcher.pfIdentified     11626730                       # number of prefetch candidates identified
system.cpu.l2cache.prefetcher.pfBufferHit       430783                       # number of redundant prefetches already in prefetch queue
system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu.l2cache.prefetcher.pfRemovedFull            3                       # number of prefetches dropped due to prefetch queue size
system.cpu.l2cache.prefetcher.pfSpanPage      4654278                       # number of prefetches not generated due to page crossing
system.cpu.l2cache.tags.replacements          4710195                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        16130.419578                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs           15323813                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs          4726123                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             3.242364                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle      29466216500                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks  5234.041152                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst    18.862974                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data  7585.301260                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher  3292.214193                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.319461                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.001151                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.462970                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.200941                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.984523                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1022          739                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024        15189                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::0            5                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::1          553                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::3          181                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0          505                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1         2391                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1230                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         9214                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4         1849                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1022     0.045105                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.927063                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses        356873283                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses       356873283                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst           41                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data     11486555                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total       11486596                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks      4830628                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      4830628                       # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data      1752756                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total      1752756                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst           41                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data     13239311                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total        13239352                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst           41                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data     13239311                       # number of overall hits
system.cpu.l2cache.overall_hits::total       13239352                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst         1036                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data      2782314                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total      2783350                       # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       984772                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       984772                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst         1036                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data      3767086                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total       3768122                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         1036                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data      3767086                       # number of overall misses
system.cpu.l2cache.overall_misses::total      3768122                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     75378470                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 238879414609                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 238954793079                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 100155661373                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 100155661373                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst     75378470                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 339035075982                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 339110454452                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst     75378470                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 339035075982                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 339110454452                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst         1077                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data     14268869                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total     14269946                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks      4830628                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      4830628                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data      2737528                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total      2737528                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst         1077                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data     17006397                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total     17007474                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst         1077                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data     17006397                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total     17007474                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.961931                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.194992                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.195050                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.359730                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.359730                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.961931                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.221510                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.221557                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.961931                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.221510                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.221557                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72759.140927                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 85856.382353                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 85851.507385                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 101704.416223                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 101704.416223                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72759.140927                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89999.292817                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 89994.552844                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72759.140927                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89999.292817                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 89994.552844                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs           53                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                2                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs    26.500000                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks      1637857                       # number of writebacks
system.cpu.l2cache.writebacks::total          1637857                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data        35708                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total        35708                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data         3730                       # number of ReadExReq MSHR hits
system.cpu.l2cache.ReadExReq_mshr_hits::total         3730                       # number of ReadExReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data        39438                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total        39438                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data        39438                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total        39438                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         1036                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data      2746606                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total      2747642                       # number of ReadReq MSHR misses
system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher       992835                       # number of HardPFReq MSHR misses
system.cpu.l2cache.HardPFReq_mshr_misses::total       992835                       # number of HardPFReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       981042                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       981042                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         1036                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data      3727648                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total      3728684                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         1036                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data      3727648                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher       992835                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total      4721519                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     66562530                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 212706720467                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 212773282997                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher  70893901794                       # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_latency::total  70893901794                       # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  91380975745                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  91380975745                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     66562530                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 304087696212                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 304154258742                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     66562530                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 304087696212                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher  70893901794                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 375048160536                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.961931                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.192489                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.192547                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.358368                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.358368                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.961931                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.219191                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.219238                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.961931                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.219191                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.277614                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64249.546332                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 77443.477684                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 77438.502904                       # average ReadReq mshr miss latency
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 71405.522362                       # average HardPFReq mshr miss latency
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 71405.522362                       # average HardPFReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 93146.853799                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 93146.853799                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64249.546332                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 81576.290522                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 81571.476355                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64249.546332                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 81576.290522                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 71405.522362                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79433.792501                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq       14269946                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp      14269946                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback      4830628                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::HardPFReq      1298291                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq      2737528                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp      2737528                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         2154                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     38843422                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total          38845576                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        68928                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1397569600                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total         1397638528                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                     1298291                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples     23136394                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        1.056115                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.230143                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1           21838103     94.39%     94.39% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2            1298291      5.61%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total       23136394                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy    15749679999                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          2.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy       1817030                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy   26101043977                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          3.4                       # Layer utilization (%)
system.membus.trans_dist::ReadReq             3736842                       # Transaction distribution
system.membus.trans_dist::ReadResp            3736842                       # Transaction distribution
system.membus.trans_dist::Writeback           1637857                       # Transaction distribution
system.membus.trans_dist::ReadExReq            981309                       # Transaction distribution
system.membus.trans_dist::ReadExResp           981309                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port     11074159                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total               11074159                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    406784512                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               406784512                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoop_fanout::samples           6356008                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                 6356008    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total             6356008                       # Request fanout histogram
system.membus.reqLayer0.occupancy         14483850639                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               1.9                       # Layer utilization (%)
system.membus.respLayer1.occupancy        25655332661                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              3.3                       # Layer utilization (%)

---------- End Simulation Statistics   ----------