1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
|
---------- Begin Simulation Statistics ----------
sim_seconds 0.771783 # Number of seconds simulated
sim_ticks 771782683000 # Number of ticks simulated
final_tick 771782683000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 141348 # Simulator instruction rate (inst/s)
host_op_rate 152281 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 70628369 # Simulator tick rate (ticks/s)
host_mem_usage 310548 # Number of bytes of host memory used
host_seconds 10927.38 # Real time elapsed on the host
sim_insts 1544563023 # Number of instructions simulated
sim_ops 1664032415 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 66112 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 238756480 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.l2cache.prefetcher 63336128 # Number of bytes read from this memory
system.physmem.bytes_read::total 302158720 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 66112 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 66112 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 104900608 # Number of bytes written to this memory
system.physmem.bytes_written::total 104900608 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 1033 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 3730570 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.l2cache.prefetcher 989627 # Number of read requests responded to by this memory
system.physmem.num_reads::total 4721230 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1639072 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1639072 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 85661 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 309357135 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.l2cache.prefetcher 82064718 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 391507515 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 85661 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 85661 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 135919878 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 135919878 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 135919878 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 85661 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 309357135 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.l2cache.prefetcher 82064718 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 527427392 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 4721230 # Number of read requests accepted
system.physmem.writeReqs 1639072 # Number of write requests accepted
system.physmem.readBursts 4721230 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 1639072 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 301708544 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 450176 # Total number of bytes read from write queue
system.physmem.bytesWritten 104898432 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 302158720 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 104900608 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 7034 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 11 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 296496 # Per bank write bursts
system.physmem.perBankRdBursts::1 294922 # Per bank write bursts
system.physmem.perBankRdBursts::2 288553 # Per bank write bursts
system.physmem.perBankRdBursts::3 293200 # Per bank write bursts
system.physmem.perBankRdBursts::4 290519 # Per bank write bursts
system.physmem.perBankRdBursts::5 289057 # Per bank write bursts
system.physmem.perBankRdBursts::6 284695 # Per bank write bursts
system.physmem.perBankRdBursts::7 280747 # Per bank write bursts
system.physmem.perBankRdBursts::8 297891 # Per bank write bursts
system.physmem.perBankRdBursts::9 303659 # Per bank write bursts
system.physmem.perBankRdBursts::10 295750 # Per bank write bursts
system.physmem.perBankRdBursts::11 302488 # Per bank write bursts
system.physmem.perBankRdBursts::12 303486 # Per bank write bursts
system.physmem.perBankRdBursts::13 302338 # Per bank write bursts
system.physmem.perBankRdBursts::14 297681 # Per bank write bursts
system.physmem.perBankRdBursts::15 292714 # Per bank write bursts
system.physmem.perBankWrBursts::0 104090 # Per bank write bursts
system.physmem.perBankWrBursts::1 102136 # Per bank write bursts
system.physmem.perBankWrBursts::2 99204 # Per bank write bursts
system.physmem.perBankWrBursts::3 100079 # Per bank write bursts
system.physmem.perBankWrBursts::4 99319 # Per bank write bursts
system.physmem.perBankWrBursts::5 99058 # Per bank write bursts
system.physmem.perBankWrBursts::6 102867 # Per bank write bursts
system.physmem.perBankWrBursts::7 104266 # Per bank write bursts
system.physmem.perBankWrBursts::8 105488 # Per bank write bursts
system.physmem.perBankWrBursts::9 104503 # Per bank write bursts
system.physmem.perBankWrBursts::10 102301 # Per bank write bursts
system.physmem.perBankWrBursts::11 102956 # Per bank write bursts
system.physmem.perBankWrBursts::12 103260 # Per bank write bursts
system.physmem.perBankWrBursts::13 102520 # Per bank write bursts
system.physmem.perBankWrBursts::14 104484 # Per bank write bursts
system.physmem.perBankWrBursts::15 102507 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 771782536000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 4721230 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 1639072 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 2775597 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 1044443 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 331745 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 234202 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 153941 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 85295 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 39428 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 23872 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 18360 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 4183 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 1645 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 788 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 434 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 248 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 11 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 4 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 22873 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 24573 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 60114 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 75847 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 85447 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 93235 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 99435 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 103341 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 105611 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 106420 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 106485 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 107133 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 108359 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 110847 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 113228 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 106323 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 103422 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 101669 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 2755 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 1061 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 485 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 198 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 99 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 50 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 22 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 10 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 4289012 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 94.801701 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 78.923105 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 101.558340 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 3414847 79.62% 79.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 675748 15.76% 95.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 96615 2.25% 97.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 35482 0.83% 98.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 22807 0.53% 98.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 12154 0.28% 99.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 7173 0.17% 99.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 5164 0.12% 99.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 19022 0.44% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 4289012 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 98837 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 47.696531 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::gmean 32.309771 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 98.301255 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-127 95044 96.16% 96.16% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::128-255 1344 1.36% 97.52% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::256-383 770 0.78% 98.30% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::384-511 419 0.42% 98.73% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::512-639 374 0.38% 99.10% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::640-767 356 0.36% 99.46% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::768-895 254 0.26% 99.72% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::896-1023 146 0.15% 99.87% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-1151 62 0.06% 99.93% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1152-1279 41 0.04% 99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1280-1407 8 0.01% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1408-1535 7 0.01% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1536-1663 2 0.00% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1792-1919 1 0.00% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1920-2047 1 0.00% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2304-2431 1 0.00% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2560-2687 3 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2944-3071 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::3200-3327 2 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::3584-3711 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 98837 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 98837 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 16.583243 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 16.550199 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 1.089458 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16 73410 74.27% 74.27% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17 1674 1.69% 75.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18 18461 18.68% 94.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19 3603 3.65% 98.29% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20 928 0.94% 99.23% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21 388 0.39% 99.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22 174 0.18% 99.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23 100 0.10% 99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24 61 0.06% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::25 27 0.03% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26 7 0.01% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::27 4 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 98837 # Writes before turning the bus around for reads
system.physmem.totQLat 132409571838 # Total ticks spent queuing
system.physmem.totMemAccLat 220800746838 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 23570980000 # Total ticks spent in databus transfers
system.physmem.avgQLat 28087.41 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 46837.41 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 390.92 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 135.92 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 391.51 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 135.92 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 4.12 # Data bus utilization in percentage
system.physmem.busUtilRead 3.05 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 1.06 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.44 # Average read queue length when enqueuing
system.physmem.avgWrQLen 24.98 # Average write queue length when enqueuing
system.physmem.readRowHits 1710867 # Number of row buffer hits during reads
system.physmem.writeRowHits 353347 # Number of row buffer hits during writes
system.physmem.readRowHitRate 36.29 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 21.56 # Row buffer hit rate for writes
system.physmem.avgGap 121343.69 # Average gap between requests
system.physmem.pageHitRate 32.49 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 16078381200 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 8772926250 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 18081671400 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 5255351280 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 50408975760 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 410988240855 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 102552687000 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 612138233745 # Total energy per rank (pJ)
system.physmem_0.averagePower 793.150023 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 168058001250 # Time in different power states
system.physmem_0.memoryStateTime::REF 25771460000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 577951698750 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 16346489040 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 8919215250 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 18688846800 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 5365504800 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 50408975760 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 412404849315 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 101310048000 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 613443928965 # Total energy per rank (pJ)
system.physmem_1.averagePower 794.841817 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 165993972457 # Time in different power states
system.physmem_1.memoryStateTime::REF 25771460000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 580015821043 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.branchPred.lookups 286268512 # Number of BP lookups
system.cpu.branchPred.condPredicted 223399208 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 14631885 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 157652290 # Number of BTB lookups
system.cpu.branchPred.BTBHits 150341382 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 95.362638 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 16641174 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 65 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 46 # Number of system calls
system.cpu.numCycles 1543565367 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles 13925779 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 2067423618 # Number of instructions fetch has processed
system.cpu.fetch.Branches 286268512 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 166982556 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 1514915602 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 29288421 # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles 253 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.IcacheWaitRetryStallCycles 919 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 656914213 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 942 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 1543486763 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.434983 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 1.229356 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 461116597 29.87% 29.87% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 465422138 30.15% 60.03% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 101389056 6.57% 66.60% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 515558972 33.40% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 1543486763 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.185459 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.339382 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 74615169 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 546131714 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 850052649 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 58043724 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 14643507 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 42202613 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 760 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 2037139109 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 52472329 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 14643507 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 139680975 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 464946049 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 14177 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 837873228 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 86328827 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 1976320354 # Number of instructions processed by rename
system.cpu.rename.SquashedInsts 26732336 # Number of squashed instructions processed by rename
system.cpu.rename.ROBFullEvents 45128593 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 125639 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 1500891 # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents 25518898 # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands 1985788047 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 9127865226 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 2432787425 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 124 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1674898945 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 310889102 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 151 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 141 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 111344488 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 542536301 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 199301557 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 26908887 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 29198248 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 1947883742 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 210 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 1857409514 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 13500100 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 279518916 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 646881302 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 40 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 1543486763 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.203385 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.151093 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 590762659 38.27% 38.27% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 325764931 21.11% 59.38% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 378272466 24.51% 83.89% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 219653351 14.23% 98.12% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 29027182 1.88% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 6174 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 1543486763 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 166053840 40.99% 40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 1992 0.00% 40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 40.99% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 191416352 47.25% 88.24% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 47630536 11.76% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 1138248479 61.28% 61.28% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 801009 0.04% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 26 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 22 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 532044411 28.64% 89.97% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 186315567 10.03% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 1857409514 # Type of FU issued
system.cpu.iq.rate 1.203324 # Inst issue rate
system.cpu.iq.fu_busy_cnt 405102720 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.218101 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 5676908390 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 2227415601 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 1805707256 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 221 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 208 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 66 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 2262512110 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 124 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 17814082 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 84229967 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 66402 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 13168 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 24454512 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 4520775 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 4802645 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 14643507 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 25316113 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 1330365 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 1947884031 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 542536301 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 199301557 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 148 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 158933 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 1170467 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 13168 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 7700956 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 8705023 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 16405979 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 1827745758 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 516865735 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 29663756 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 79 # number of nop insts executed
system.cpu.iew.exec_refs 698617938 # number of memory reference insts executed
system.cpu.iew.exec_branches 229554698 # Number of branches executed
system.cpu.iew.exec_stores 181752203 # Number of stores executed
system.cpu.iew.exec_rate 1.184106 # Inst execution rate
system.cpu.iew.wb_sent 1808737138 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 1805707322 # cumulative count of insts written-back
system.cpu.iew.wb_producers 1169287953 # num instructions producing a value
system.cpu.iew.wb_consumers 1689671414 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.169829 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.692021 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts 257958644 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 14631182 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 1504006174 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.106400 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.024308 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 923727407 61.42% 61.42% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 250637926 16.66% 78.08% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 110048306 7.32% 85.40% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 55269063 3.67% 89.07% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 29308073 1.95% 91.02% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 34102690 2.27% 93.29% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 24713726 1.64% 94.93% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 18129256 1.21% 96.14% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 58069727 3.86% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 1504006174 # Number of insts commited each cycle
system.cpu.commit.committedInsts 1544563041 # Number of instructions committed
system.cpu.commit.committedOps 1664032433 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 633153379 # Number of memory references committed
system.cpu.commit.loads 458306334 # Number of loads committed
system.cpu.commit.membars 62 # Number of memory barriers committed
system.cpu.commit.branches 213462426 # Number of branches committed
system.cpu.commit.fp_insts 36 # Number of committed floating point instructions.
system.cpu.commit.int_insts 1477900421 # Number of committed integer instructions.
system.cpu.commit.function_calls 13665177 # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu 1030178729 61.91% 61.91% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult 700322 0.04% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc 3 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead 458306334 27.54% 89.49% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 174847045 10.51% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 1664032433 # Class of committed instruction
system.cpu.commit.bw_lim_events 58069727 # number cycles where commit BW limit reached
system.cpu.rob.rob_reads 3367926925 # The number of ROB reads
system.cpu.rob.rob_writes 3883468057 # The number of ROB writes
system.cpu.timesIdled 846 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 78604 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1544563023 # Number of Instructions Simulated
system.cpu.committedOps 1664032415 # Number of Ops (including micro ops) Simulated
system.cpu.cpi 0.999354 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.999354 # CPI: Total CPI of All Threads
system.cpu.ipc 1.000646 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.000646 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 2175695472 # number of integer regfile reads
system.cpu.int_regfile_writes 1261559121 # number of integer regfile writes
system.cpu.fp_regfile_reads 38 # number of floating regfile reads
system.cpu.fp_regfile_writes 48 # number of floating regfile writes
system.cpu.cc_regfile_reads 6965502930 # number of cc regfile reads
system.cpu.cc_regfile_writes 551873305 # number of cc regfile writes
system.cpu.misc_regfile_reads 675842878 # number of misc regfile reads
system.cpu.misc_regfile_writes 124 # number of misc regfile writes
system.cpu.dcache.tags.replacements 17005493 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.964646 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 638183172 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 17006005 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 37.526931 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 79063000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 511.964646 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999931 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999931 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 392 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 120 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 1335677307 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 1335677307 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 469397613 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 469397613 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 168785441 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 168785441 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 57 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 57 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 638183054 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 638183054 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 638183054 # number of overall hits
system.cpu.dcache.overall_hits::total 638183054 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 17351867 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 17351867 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 3800606 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 3800606 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 21152473 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 21152473 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 21152475 # number of overall misses
system.cpu.dcache.overall_misses::total 21152475 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 417182903209 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 417182903209 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 149917932873 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 149917932873 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 358750 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 358750 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 567100836082 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 567100836082 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 567100836082 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 567100836082 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 486749480 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 486749480 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 2 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 2 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 659335527 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 659335527 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 659335529 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 659335529 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035648 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.035648 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022022 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.022022 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.065574 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.065574 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.032082 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.032082 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.032082 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.032082 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24042.536933 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 24042.536933 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39445.797032 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 39445.797032 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 89687.500000 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 89687.500000 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 26810.143480 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 26810.143480 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 26810.140945 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 26810.140945 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 20723795 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 3315809 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 944207 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 67033 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.948360 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 49.465323 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 4835251 # number of writebacks
system.cpu.dcache.writebacks::total 4835251 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3083373 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 3083373 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1063096 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 1063096 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 4146469 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 4146469 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 4146469 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 4146469 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14268494 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 14268494 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737510 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 2737510 # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 17006004 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 17006004 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 17006005 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 17006005 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 329072767985 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 329072767985 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 115107857313 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 115107857313 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 67750 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 67750 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 444180625298 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 444180625298 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 444180693048 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 444180693048 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029314 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029314 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015862 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015862 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025793 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.025793 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025793 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.025793 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23062.894233 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23062.894233 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42048.378750 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42048.378750 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 67750 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 67750 # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26119.047443 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 26119.047443 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26119.049891 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 26119.049891 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 588 # number of replacements
system.cpu.icache.tags.tagsinuse 446.068543 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 656912599 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 1076 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 610513.567844 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 446.068543 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.871228 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.871228 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 488 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 442 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.953125 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 1313829498 # Number of tag accesses
system.cpu.icache.tags.data_accesses 1313829498 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 656912599 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 656912599 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 656912599 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 656912599 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 656912599 # number of overall hits
system.cpu.icache.overall_hits::total 656912599 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1612 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1612 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1612 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1612 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1612 # number of overall misses
system.cpu.icache.overall_misses::total 1612 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 102924516 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 102924516 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 102924516 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 102924516 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 102924516 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 102924516 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 656914211 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 656914211 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 656914211 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 656914211 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 656914211 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 656914211 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63848.955335 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 63848.955335 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 63848.955335 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 63848.955335 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 63848.955335 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 63848.955335 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 17306 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 307 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 186 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 8 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs 93.043011 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 38.375000 # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 536 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 536 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 536 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 536 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 536 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 536 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1076 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 1076 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 1076 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 1076 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 1076 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 1076 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 76203217 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 76203217 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 76203217 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 76203217 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 76203217 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 76203217 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70820.833643 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70820.833643 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70820.833643 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 70820.833643 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70820.833643 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 70820.833643 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.prefetcher.num_hwpf_issued 10941726 # number of hwpf issued
system.cpu.l2cache.prefetcher.pfIdentified 11630409 # number of prefetch candidates identified
system.cpu.l2cache.prefetcher.pfBufferHit 431114 # number of redundant prefetches already in prefetch queue
system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu.l2cache.prefetcher.pfSpanPage 4654951 # number of prefetches not generated due to page crossing
system.cpu.l2cache.tags.replacements 4713207 # number of replacements
system.cpu.l2cache.tags.tagsinuse 16130.406064 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 15325447 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 4729134 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 3.240646 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 29468558500 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 5233.732135 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 18.908605 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 7574.796716 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 3302.968608 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.319442 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001154 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.462329 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.201597 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.984522 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1022 731 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024 15196 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::0 5 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::1 525 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::3 201 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 466 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2455 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1253 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 9206 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1816 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1022 0.044617 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.927490 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 356943997 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 356943997 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst 43 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 11484174 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 11484217 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 4835251 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 4835251 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 1752141 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 1752141 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 43 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 13236315 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 13236358 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 43 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 13236315 # number of overall hits
system.cpu.l2cache.overall_hits::total 13236358 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 1033 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 2784280 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 2785313 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 985410 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 985410 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 1033 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 3769690 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 3770723 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 1033 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 3769690 # number of overall misses
system.cpu.l2cache.overall_misses::total 3770723 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 75372729 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 239047213138 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 239122585867 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 100142345987 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 100142345987 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 75372729 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 339189559125 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 339264931854 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 75372729 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 339189559125 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 339264931854 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 1076 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 14268454 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 14269530 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 4835251 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 4835251 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 2737551 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 2737551 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 1076 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 17006005 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 17007081 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 1076 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 17006005 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 17007081 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.960037 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.195135 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.195193 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.359960 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.359960 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.960037 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.221668 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.221715 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.960037 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.221668 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.221715 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72964.887706 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 85856.024946 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 85851.243960 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 101625.055547 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 101625.055547 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72964.887706 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89978.104068 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 89973.443251 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72964.887706 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89978.104068 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 89973.443251 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 846 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 211.500000 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 1639072 # number of writebacks
system.cpu.l2cache.writebacks::total 1639072 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 36084 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total 36084 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3647 # number of ReadExReq MSHR hits
system.cpu.l2cache.ReadExReq_mshr_hits::total 3647 # number of ReadExReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 39731 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 39731 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 39731 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 39731 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1033 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 2748196 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 2749229 # number of ReadReq MSHR misses
system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 993723 # number of HardPFReq MSHR misses
system.cpu.l2cache.HardPFReq_mshr_misses::total 993723 # number of HardPFReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 981763 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 981763 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 1033 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 3729959 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 3730992 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 1033 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 3729959 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 993723 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 4724715 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 66585771 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 212846915589 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 212913501360 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 71046693133 # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 71046693133 # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 91372170669 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 91372170669 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 66585771 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 304219086258 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 304285672029 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 66585771 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 304219086258 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 71046693133 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 375332365162 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.960037 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.192606 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.192664 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.358628 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.358628 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.960037 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.219332 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.219379 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.960037 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.219332 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.277809 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64458.636012 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 77449.685390 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 77444.804111 # average ReadReq mshr miss latency
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 71495.470199 # average HardPFReq mshr miss latency
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 71495.470199 # average HardPFReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 93069.478753 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 93069.478753 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64458.636012 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 81560.973259 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 81556.238134 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64458.636012 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 81560.973259 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 71495.470199 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79440.212830 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq 14269530 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 14269530 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 4835251 # Transaction distribution
system.cpu.toL2Bus.trans_dist::HardPFReq 1300143 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 2737551 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 2737551 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2152 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 38847261 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 38849413 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 68864 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1397840384 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 1397909248 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 1300143 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 23142477 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 3.056180 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.230269 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::3 21842334 94.38% 94.38% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4 1300143 5.62% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 23142477 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 15756418748 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 2.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 1812271 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 26100835834 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 3.4 # Layer utilization (%)
system.membus.trans_dist::ReadReq 3739202 # Transaction distribution
system.membus.trans_dist::ReadResp 3739202 # Transaction distribution
system.membus.trans_dist::Writeback 1639072 # Transaction distribution
system.membus.trans_dist::ReadExReq 982028 # Transaction distribution
system.membus.trans_dist::ReadExResp 982028 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11081532 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 11081532 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 407059328 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 407059328 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 6360302 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 6360302 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 6360302 # Request fanout histogram
system.membus.reqLayer0.occupancy 14493239223 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 1.9 # Layer utilization (%)
system.membus.respLayer1.occupancy 25671846860 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 3.3 # Layer utilization (%)
---------- End Simulation Statistics ----------
|