path: root/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.770336                       # Number of seconds simulated
sim_ticks                                770336310500                       # Number of ticks simulated
final_tick                               770336310500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 130811                       # Simulator instruction rate (inst/s)
host_op_rate                                   140929                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               65240720                       # Simulator tick rate (ticks/s)
host_mem_usage                                 314688                       # Number of bytes of host memory used
host_seconds                                 11807.60                       # Real time elapsed on the host
sim_insts                                  1544563024                       # Number of instructions simulated
sim_ops                                    1664032416                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst             66496                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data         238054976                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.l2cache.prefetcher     63977600                       # Number of bytes read from this memory
system.physmem.bytes_read::total            302099072                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst        66496                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           66496                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks    104804160                       # Number of bytes written to this memory
system.physmem.bytes_written::total         104804160                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst               1039                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data            3719609                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.l2cache.prefetcher       999650                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               4720298                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1637565                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1637565                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst                86321                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data            309027334                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.l2cache.prefetcher     83051518                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total               392165172                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst           86321                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total              86321                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks         136049877                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total              136049877                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks         136049877                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst               86321                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data           309027334                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.l2cache.prefetcher     83051518                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              528215049                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                       4720298                       # Number of read requests accepted
system.physmem.writeReqs                      1637565                       # Number of write requests accepted
system.physmem.readBursts                     4720298                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                    1637565                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                301639360                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                    459712                       # Total number of bytes read from write queue
system.physmem.bytesWritten                 104801536                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                 302099072                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys              104804160                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                     7183                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                      11                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0              296850                       # Per bank write bursts
system.physmem.perBankRdBursts::1              294498                       # Per bank write bursts
system.physmem.perBankRdBursts::2              288916                       # Per bank write bursts
system.physmem.perBankRdBursts::3              292682                       # Per bank write bursts
system.physmem.perBankRdBursts::4              290729                       # Per bank write bursts
system.physmem.perBankRdBursts::5              289596                       # Per bank write bursts
system.physmem.perBankRdBursts::6              284483                       # Per bank write bursts
system.physmem.perBankRdBursts::7              281209                       # Per bank write bursts
system.physmem.perBankRdBursts::8              297427                       # Per bank write bursts
system.physmem.perBankRdBursts::9              303552                       # Per bank write bursts
system.physmem.perBankRdBursts::10             295336                       # Per bank write bursts
system.physmem.perBankRdBursts::11             302232                       # Per bank write bursts
system.physmem.perBankRdBursts::12             303231                       # Per bank write bursts
system.physmem.perBankRdBursts::13             302345                       # Per bank write bursts
system.physmem.perBankRdBursts::14             297342                       # Per bank write bursts
system.physmem.perBankRdBursts::15             292687                       # Per bank write bursts
system.physmem.perBankWrBursts::0              104014                       # Per bank write bursts
system.physmem.perBankWrBursts::1              101992                       # Per bank write bursts
system.physmem.perBankWrBursts::2               99263                       # Per bank write bursts
system.physmem.perBankWrBursts::3               99947                       # Per bank write bursts
system.physmem.perBankWrBursts::4               99433                       # Per bank write bursts
system.physmem.perBankWrBursts::5               98879                       # Per bank write bursts
system.physmem.perBankWrBursts::6              102579                       # Per bank write bursts
system.physmem.perBankWrBursts::7              104318                       # Per bank write bursts
system.physmem.perBankWrBursts::8              105363                       # Per bank write bursts
system.physmem.perBankWrBursts::9              104471                       # Per bank write bursts
system.physmem.perBankWrBursts::10             102169                       # Per bank write bursts
system.physmem.perBankWrBursts::11             102930                       # Per bank write bursts
system.physmem.perBankWrBursts::12             102920                       # Per bank write bursts
system.physmem.perBankWrBursts::13             102581                       # Per bank write bursts
system.physmem.perBankWrBursts::14             104115                       # Per bank write bursts
system.physmem.perBankWrBursts::15             102550                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    770336158500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                 4720298                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                1637565                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                   2783946                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                   1045590                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                    328353                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                    232144                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                    151285                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                     83614                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                     38578                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                     23869                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                     18243                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      4278                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                     1738                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      814                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      426                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      232                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        5                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    23160                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    24842                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    60100                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    75642                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    85493                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    93558                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    99663                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                   103776                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                   105596                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                   106367                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                   106074                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                   106708                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                   108208                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                   111119                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                   114322                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                   105421                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                   102034                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                   101193                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     2551                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      964                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      428                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      159                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                       76                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                       38                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                       21                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        9                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        8                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        4                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        3                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples      4289513                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean       94.751761                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean      78.903148                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     101.431882                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127        3416049     79.64%     79.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255       675171     15.74%     95.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        96645      2.25%     97.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511        35451      0.83%     98.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639        23003      0.54%     98.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767        12074      0.28%     99.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         6995      0.16%     99.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         5025      0.12%     99.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        19100      0.45%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total        4289513                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         98662                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        47.769871                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::gmean       32.372187                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev       98.540692                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-255           96215     97.52%     97.52% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::256-511          1195      1.21%     98.73% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::512-767           729      0.74%     99.47% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::768-1023          403      0.41%     99.88% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-1279           87      0.09%     99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1280-1535           19      0.02%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1536-1791            4      0.00%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1792-2047            4      0.00%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-2303            1      0.00%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2304-2559            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2560-2815            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::3072-3327            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::3584-3839            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::5120-5375            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           98662                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         98662                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        16.597312                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       16.563431                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        1.103098                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16              72815     73.80%     73.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17               1780      1.80%     75.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18              18354     18.60%     94.21% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19               3927      3.98%     98.19% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20                986      1.00%     99.19% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21                404      0.41%     99.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22                201      0.20%     99.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23                116      0.12%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24                 44      0.04%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::25                 22      0.02%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26                 12      0.01%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::27                  1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           98662                       # Writes before turning the bus around for reads
system.physmem.totQLat                   131160021238                       # Total ticks spent queuing
system.physmem.totMemAccLat              219530927488                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                  23565575000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       27828.73                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  46578.73                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                         391.57                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                         136.05                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                      392.17                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                      136.05                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           4.12                       # Data bus utilization in percentage
system.physmem.busUtilRead                       3.06                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      1.06                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.44                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        25.01                       # Average write queue length when enqueuing
system.physmem.readRowHits                    1707273                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    353841                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   36.22                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  21.61                       # Row buffer hit rate for writes
system.physmem.avgGap                       121162.75                       # Average gap between requests
system.physmem.pageHitRate                      32.46                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                16082924760                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                 8775405375                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy               18087474600                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy               5251508640                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy            50314383600                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy           409609386630                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           102893262750                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             611014346355                       # Total energy per rank (pJ)
system.physmem_0.averagePower              793.182199                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   168633417027                       # Time in different power states
system.physmem_0.memoryStateTime::REF     25723100000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT    575976400473                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                16345687680                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                 8918778000                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy               18674323200                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy               5359543200                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy            50314383600                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy           410844304170                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           101810001750                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             612267021600                       # Total energy per rank (pJ)
system.physmem_1.averagePower              794.808347                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   166829398639                       # Time in different power states
system.physmem_1.memoryStateTime::REF     25723100000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT    577780670361                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu.branchPred.lookups               286278310                       # Number of BP lookups
system.cpu.branchPred.condPredicted         223407435                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect          14630059                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups            158227088                       # Number of BTB lookups
system.cpu.branchPred.BTBHits               150348964                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             95.021002                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                16641238                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect                 64                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.walks                         0                       # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                   46                       # Number of system calls
system.cpu.numCycles                       1540672622                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles           13926355                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                     2067514794                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                   286278310                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches          166990202                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                    1512022873                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                29284737                       # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles                  188                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.IcacheWaitRetryStallCycles         1021                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                 656940964                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                   966                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples         1540592805                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              1.437738                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             1.228920                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                458181319     29.74%     29.74% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                465421558     30.21%     59.95% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                101422593      6.58%     66.53% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                515567335     33.47%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total           1540592805                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.185814                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        1.341956                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 74646858                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles             543216907                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 849967493                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles              58119883                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles               14641664                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved             42201795                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                   757                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts             2037179352                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts              52470113                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles               14641664                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                139717275                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles               462450514                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles          13916                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 837848883                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              85920553                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts             1976355004                       # Number of instructions processed by rename
system.cpu.rename.SquashedInsts              26745374                       # Number of squashed instructions processed by rename
system.cpu.rename.ROBFullEvents              45156757                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                 125486                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents                1486003                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents               25049006                       # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands          1985823032                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            9128033727                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       2432836892                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups               151                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps            1674898945                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                310924087                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts                156                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts            148                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                 111428528                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads            542554069                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores           199305704                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads          26941972                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores         29270810                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                 1947933260                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded                 215                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                1857474146                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued          13497185                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined       283901059                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined    647116126                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved             45                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples    1540592805                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         1.205688                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.150881                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           587702275     38.15%     38.15% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1           325996808     21.16%     59.31% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2           378232244     24.55%     83.86% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3           219639231     14.26%     98.12% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            29016078      1.88%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5                6169      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total      1540592805                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu               166081126     41.00%     41.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                   1996      0.00%     41.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     41.00% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     41.00% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     41.00% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     41.00% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     41.00% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     41.00% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     41.00% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     41.00% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     41.00% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     41.00% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     41.00% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     41.00% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     41.00% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     41.00% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     41.00% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     41.00% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     41.00% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     41.00% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     41.00% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     41.00% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     41.00% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     41.00% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     41.00% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     41.00% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     41.00% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     41.00% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     41.00% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead              191505284     47.27%     88.27% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite              47530605     11.73%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu            1138242397     61.28%     61.28% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult               801060      0.04%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt              32      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc             22      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     61.32% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead            532116023     28.65%     89.97% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite           186314612     10.03%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total             1857474146                       # Type of FU issued
system.cpu.iq.rate                           1.205625                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                   405119011                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.218102                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         5674157044                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes        2231847189                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses   1805703414                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                 249                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes                266                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses           72                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses             2262593018                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                     139                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads         17811740                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads     84247735                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses        66708                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        13149                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores     24458659                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads      4504401                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked       4884981                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles               14641664                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                25329983                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles               1325123                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts          1947933556                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts             542554069                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts            199305704                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts                153                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                 159005                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents               1165002                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          13149                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect        7699177                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect      8705456                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts             16404633                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts            1827812064                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts             516937908                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts          29662082                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                            81                       # number of nop insts executed
system.cpu.iew.exec_refs                    698690935                       # number of memory reference insts executed
system.cpu.iew.exec_branches                229542500                       # Number of branches executed
system.cpu.iew.exec_stores                  181753027                       # Number of stores executed
system.cpu.iew.exec_rate                     1.186373                       # Inst execution rate
system.cpu.iew.wb_sent                     1808734068                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                    1805703486                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                1169239698                       # num instructions producing a value
system.cpu.iew.wb_consumers                1689624086                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.172023                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.692012                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts       258007667                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls             170                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts          14629355                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples   1501111622                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.108533                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.025633                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    920819202     61.34%     61.34% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1    250634053     16.70%     78.04% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2    110061016      7.33%     85.37% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     55281373      3.68%     89.05% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4     29321487      1.95%     91.01% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5     34081425      2.27%     93.28% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6     24716781      1.65%     94.92% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7     18131809      1.21%     96.13% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8     58064476      3.87%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total   1501111622                       # Number of insts commited each cycle
system.cpu.commit.committedInsts           1544563042                       # Number of instructions committed
system.cpu.commit.committedOps             1664032434                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                      633153379                       # Number of memory references committed
system.cpu.commit.loads                     458306334                       # Number of loads committed
system.cpu.commit.membars                          62                       # Number of memory barriers committed
system.cpu.commit.branches                  213462427                       # Number of branches committed
system.cpu.commit.fp_insts                         36                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                1477900421                       # Number of committed integer instructions.
system.cpu.commit.function_calls             13665177                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu       1030178730     61.91%     61.91% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult          700322      0.04%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv                0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd              0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp              0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt              0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv              0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc            3      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead       458306334     27.54%     89.49% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite      174847045     10.51%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total        1664032434                       # Class of committed instruction
system.cpu.commit.bw_lim_events              58064476                       # number cycles where commit BW limit reached
system.cpu.rob.rob_reads                   3365086648                       # The number of ROB reads
system.cpu.rob.rob_writes                  3883566462                       # The number of ROB writes
system.cpu.timesIdled                             859                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                           79817                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                  1544563024                       # Number of Instructions Simulated
system.cpu.committedOps                    1664032416                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               0.997481                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.997481                       # CPI: Total CPI of All Threads
system.cpu.ipc                               1.002525                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         1.002525                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads               2175803949                       # number of integer regfile reads
system.cpu.int_regfile_writes              1261568723                       # number of integer regfile writes
system.cpu.fp_regfile_reads                        40                       # number of floating regfile reads
system.cpu.fp_regfile_writes                       54                       # number of floating regfile writes
system.cpu.cc_regfile_reads                6965710140                       # number of cc regfile reads
system.cpu.cc_regfile_writes                551865181                       # number of cc regfile writes
system.cpu.misc_regfile_reads               675846539                       # number of misc regfile reads
system.cpu.misc_regfile_writes                    124                       # number of misc regfile writes
system.cpu.dcache.tags.replacements          17004606                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.964973                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           638063275                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs          17005118                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             37.521838                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle          77839500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.964973                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999932                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999932                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0          420                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1           92                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses        1335698850                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses       1335698850                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data    469343498                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       469343498                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data    168719659                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total      168719659                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data           57                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total           57                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data           61                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total           61                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data     638063157                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        638063157                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    638063157                       # number of overall hits
system.cpu.dcache.overall_hits::total       638063157                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data     17417197                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total      17417197                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      3866388                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      3866388                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data            2                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total            2                       # number of SoftPFReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data            4                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total            4                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data     21283585                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total       21283585                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data     21283587                       # number of overall misses
system.cpu.dcache.overall_misses::total      21283587                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 415522893500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 415522893500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 149855935942                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 149855935942                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       216000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total       216000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 565378829442                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 565378829442                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 565378829442                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 565378829442                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    486760695                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    486760695                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data    172586047                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total    172586047                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data            2                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total            2                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data           61                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total           61                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data           61                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total           61                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    659346742                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    659346742                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    659346744                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    659346744                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.035782                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.035782                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.022403                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.022403                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data            1                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total            1                       # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.065574                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.065574                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.032280                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.032280                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.032280                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.032280                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23857.047348                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 23857.047348                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38758.638797                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 38758.638797                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        54000                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        54000                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 26564.078817                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 26564.078817                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 26564.076320                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 26564.076320                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs     20755892                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets      3446894                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs            946527                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets           67143                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    21.928473                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets    51.336610                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      4835415                       # number of writebacks
system.cpu.dcache.writebacks::total           4835415                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data      3149636                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total      3149636                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1128832                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total      1128832                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            4                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total            4                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      4278468                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      4278468                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      4278468                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      4278468                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data     14267561                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total     14267561                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data      2737556                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total      2737556                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data            1                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total            1                       # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data     17005117                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total     17005117                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data     17005118                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total     17005118                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 335383172000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 335383172000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 116381847286                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 116381847286                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data        68000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total        68000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 451765019286                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 451765019286                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 451765087286                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 451765087286                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.029311                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.029311                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015862                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015862                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.500000                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.500000                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.025791                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.025791                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.025791                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.025791                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23506.692700                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23506.692700                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42513.047144                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42513.047144                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        68000                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        68000                       # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26566.416408                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 26566.416408                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26566.418844                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 26566.418844                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements               592                       # number of replacements
system.cpu.icache.tags.tagsinuse           446.127099                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           656939322                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs              1080                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs          608277.150000                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   446.127099                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.871342                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.871342                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          488                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           31                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1           15                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4          442                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.953125                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses        1313883006                       # Number of tag accesses
system.cpu.icache.tags.data_accesses       1313883006                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst    656939322                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       656939322                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     656939322                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        656939322                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    656939322                       # number of overall hits
system.cpu.icache.overall_hits::total       656939322                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst         1641                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total          1641                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst         1641                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total           1641                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst         1641                       # number of overall misses
system.cpu.icache.overall_misses::total          1641                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    107375484                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    107375484                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    107375484                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    107375484                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    107375484                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    107375484                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    656940963                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    656940963                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    656940963                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    656940963                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    656940963                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    656940963                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000002                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000002                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000002                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000002                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000002                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000002                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 65432.957952                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 65432.957952                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 65432.957952                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 65432.957952                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 65432.957952                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 65432.957952                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs        18112                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets         1654                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs               192                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets              10                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    94.333333                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets   165.400000                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst          561                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total          561                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst          561                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total          561                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst          561                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total          561                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst         1080                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total         1080                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst         1080                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total         1080                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst         1080                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total         1080                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     76771987                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total     76771987                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst     76771987                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total     76771987                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst     76771987                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total     76771987                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000002                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000002                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000002                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71085.173148                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71085.173148                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71085.173148                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 71085.173148                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71085.173148                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 71085.173148                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.prefetcher.num_hwpf_issued     11620529                       # number of hwpf issued
system.cpu.l2cache.prefetcher.pfIdentified     11640215                       # number of prefetch candidates identified
system.cpu.l2cache.prefetcher.pfBufferHit        14721                       # number of redundant prefetches already in prefetch queue
system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu.l2cache.prefetcher.pfSpanPage      4656609                       # number of prefetches not generated due to page crossing
system.cpu.l2cache.tags.replacements          4712362                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        16129.977996                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs           27367770                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs          4728288                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             5.788093                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle      29479829000                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks  5227.936161                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst    18.488571                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data  7534.908085                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher  3348.645178                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.319088                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.001128                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.459894                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.204385                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.984496                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1022          817                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024        15109                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::0            3                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::1          599                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::3          215                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0          502                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1         2347                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1263                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         9167                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4         1830                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1022     0.049866                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.922180                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses        551302751                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses       551302751                       # Number of data accesses
system.cpu.l2cache.Writeback_hits::writebacks      4835415                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      4835415                       # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data      1752988                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total      1752988                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst           41                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total           41                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data     11483491                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total     11483491                       # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst           41                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data     13236479                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total        13236520                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst           41                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data     13236479                       # number of overall hits
system.cpu.l2cache.overall_hits::total       13236520                       # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data       984611                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       984611                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         1039                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total         1039                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data      2784028                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total      2784028                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst         1039                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data      3768639                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total       3769678                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         1039                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data      3768639                       # number of overall misses
system.cpu.l2cache.overall_misses::total      3769678                       # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  99828708999                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  99828708999                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     75380000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total     75380000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 238235637000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 238235637000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst     75380000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 338064345999                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 338139725999                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst     75380000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 338064345999                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 338139725999                       # number of overall miss cycles
system.cpu.l2cache.Writeback_accesses::writebacks      4835415                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      4835415                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data      2737599                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total      2737599                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         1080                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total         1080                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data     14267519                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total     14267519                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst         1080                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data     17005118                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total     17006198                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst         1080                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data     17005118                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total     17006198                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.359662                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.359662                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.962037                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.962037                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.195130                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.195130                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.962037                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.221618                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.221665                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.962037                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.221618                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.221665                       # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 101388.984075                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 101388.984075                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 72550.529355                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 72550.529355                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85572.284833                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85572.284833                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72550.529355                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89704.624401                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 89699.896383                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72550.529355                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89704.624401                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 89699.896383                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs           30                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                2                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs           15                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks      1637565                       # number of writebacks
system.cpu.l2cache.writebacks::total          1637565                       # number of writebacks
system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data         4105                       # number of ReadExReq MSHR hits
system.cpu.l2cache.ReadExReq_mshr_hits::total         4105                       # number of ReadExReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data        45593                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total        45593                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data        49698                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total        49698                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data        49698                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total        49698                       # number of overall MSHR hits
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks       100082                       # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total       100082                       # number of CleanEvict MSHR misses
system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher      1001959                       # number of HardPFReq MSHR misses
system.cpu.l2cache.HardPFReq_mshr_misses::total      1001959                       # number of HardPFReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       980506                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       980506                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         1039                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total         1039                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data      2738435                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total      2738435                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         1039                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data      3718941                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total      3719980                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         1039                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data      3718941                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher      1001959                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total      4721939                       # number of overall MSHR misses
system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher  72923665986                       # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_latency::total  72923665986                       # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  93548158999                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  93548158999                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     69146000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     69146000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 218917649000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 218917649000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     69146000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 312465807999                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 312534953999                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     69146000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 312465807999                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher  72923665986                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 385458619985                       # number of overall MSHR miss cycles
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.358163                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.358163                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.962037                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.962037                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.191935                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.191935                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.962037                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.218695                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.218743                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.962037                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.218695                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.277660                       # mshr miss rate for overall accesses
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 72781.087835                       # average HardPFReq mshr miss latency
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 72781.087835                       # average HardPFReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95408.043397                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95408.043397                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66550.529355                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66550.529355                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79942.612843                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79942.612843                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66550.529355                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84020.103572                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84015.224275                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66550.529355                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84020.103572                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 72781.087835                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 81631.427256                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.snoop_filter.tot_requests     34011398                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests     17005208                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests        21592                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops       111772                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops       111653                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops          119                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp      14268599                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback      6472980                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict     15222988                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::HardPFReq      1281199                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq      2737599                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp      2737599                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq         1080                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq     14267519                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         2748                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     50993254                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total          50996002                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        69120                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1397794112                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total         1397863232                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                     5993561                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples     40004959                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        0.003877                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.062190                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0           39849994     99.61%     99.61% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1             154846      0.39%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                119      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total       40004959                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy    21841114998                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          2.8                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy       1620000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy   25507681990                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          3.3                       # Layer utilization (%)
system.membus.trans_dist::ReadResp            3739654                       # Transaction distribution
system.membus.trans_dist::Writeback           1637565                       # Transaction distribution
system.membus.trans_dist::CleanEvict          3065415                       # Transaction distribution
system.membus.trans_dist::ReadExReq            980644                       # Transaction distribution
system.membus.trans_dist::ReadExResp           980644                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq       3739654                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port     14143576                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total               14143576                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    406903232                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               406903232                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoop_fanout::samples           9423278                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                 9423278    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total             9423278                       # Request fanout histogram
system.membus.reqLayer0.occupancy         17318873513                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               2.2                       # Layer utilization (%)
system.membus.respLayer1.occupancy        25673835894                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              3.3                       # Layer utilization (%)

---------- End Simulation Statistics   ----------