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|
---------- Begin Simulation Statistics ----------
sim_seconds 0.458036 # Number of seconds simulated
sim_ticks 458035985000 # Number of ticks simulated
final_tick 458035985000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 197390 # Simulator instruction rate (inst/s)
host_op_rate 220203 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 58535443 # Simulator tick rate (ticks/s)
host_mem_usage 234800 # Number of bytes of host memory used
host_seconds 7824.93 # Real time elapsed on the host
sim_insts 1544563073 # Number of instructions simulated
sim_ops 1723073885 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 48320 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 156358784 # Number of bytes read from this memory
system.physmem.bytes_read::total 156407104 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 48320 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 48320 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 71946432 # Number of bytes written to this memory
system.physmem.bytes_written::total 71946432 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 755 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 2443106 # Number of read requests responded to by this memory
system.physmem.num_reads::total 2443861 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1124163 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1124163 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 105494 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 341367904 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 341473398 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 105494 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 105494 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 157075938 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 157075938 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 157075938 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 105494 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 341367904 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 498549336 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 46 # Number of system calls
system.cpu.numCycles 916071971 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 300386365 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 246254548 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 16072669 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 170403157 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 156239351 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 18292614 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 219 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 292465712 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 2157283635 # Number of instructions fetch has processed
system.cpu.fetch.Branches 300386365 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 174531965 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 428963032 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 83531263 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 119911343 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 109 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 283465873 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 5375761 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 908345220 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.641582 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.245010 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 479382246 52.78% 52.78% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 23075019 2.54% 55.32% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 38696357 4.26% 59.58% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 47758356 5.26% 64.83% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 40740735 4.49% 69.32% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 46836926 5.16% 74.47% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 39064245 4.30% 78.78% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 18137906 2.00% 80.77% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 174653430 19.23% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 908345220 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.327907 # Number of branch fetches per cycle
system.cpu.fetch.rate 2.354928 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 321276302 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 100437637 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 403614016 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 16012907 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 67004358 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 46143588 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 709 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 2345766913 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 2404 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 67004358 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 342772787 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 44470406 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 13938 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 396994343 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 57089388 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 2288809868 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 21597 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 4587251 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 43867874 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 3 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 2263371035 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 10565210641 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 10565207285 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 3356 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1706320010 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 557051025 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 5363 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 5361 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 133306732 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 624412648 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 218802984 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 85974356 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 66146404 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 2189209490 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 1708 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 2014638202 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 4851094 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 461527844 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 1075835396 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 1528 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 908345220 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 2.217921 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.925838 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 244431658 26.91% 26.91% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 136114338 14.98% 41.89% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 157116427 17.30% 59.19% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 116129005 12.78% 71.98% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 125782921 13.85% 85.82% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 75959694 8.36% 94.19% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 39392857 4.34% 98.52% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 10729861 1.18% 99.70% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 2688459 0.30% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 908345220 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 792596 3.16% 3.16% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 4903 0.02% 3.18% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 3.18% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.18% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.18% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.18% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 3.18% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.18% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 3.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 3.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.18% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 19003801 75.87% 79.06% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 5245876 20.94% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 1233307061 61.22% 61.22% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 930228 0.05% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 49 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 3 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 28 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 10 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 586604414 29.12% 90.38% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 193796407 9.62% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 2014638202 # Type of FU issued
system.cpu.iq.rate 2.199214 # Inst issue rate
system.cpu.iq.fu_busy_cnt 25047176 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.012433 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 4967519524 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 2650923657 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 1956580647 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 370 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 618 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 132 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 2039685190 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 188 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 63569960 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 138485869 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 280074 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 188083 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 43955929 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 515490 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 67004358 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 19766452 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 1127497 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 2189219165 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 5544678 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 624412648 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 218802984 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 1639 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 172089 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 43011 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 188083 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 8607625 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 10203792 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 18811417 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 1985083877 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 571977023 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 29554325 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 7967 # number of nop insts executed
system.cpu.iew.exec_refs 762799722 # number of memory reference insts executed
system.cpu.iew.exec_branches 238022734 # Number of branches executed
system.cpu.iew.exec_stores 190822699 # Number of stores executed
system.cpu.iew.exec_rate 2.166952 # Inst execution rate
system.cpu.iew.wb_sent 1965575614 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 1956580779 # cumulative count of insts written-back
system.cpu.iew.wb_producers 1296425776 # num instructions producing a value
system.cpu.iew.wb_consumers 2069436870 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 2.135837 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.626463 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 1544563091 # The number of committed instructions
system.cpu.commit.commitCommittedOps 1723073903 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 466205393 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 180 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 16072230 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 841340863 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 2.048009 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.762269 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 352627350 41.91% 41.91% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 193034897 22.94% 64.86% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 73667996 8.76% 73.61% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 35236864 4.19% 77.80% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 18719576 2.22% 80.03% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 30675778 3.65% 83.67% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 19663987 2.34% 86.01% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 10964014 1.30% 87.31% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 106750401 12.69% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 841340863 # Number of insts commited each cycle
system.cpu.commit.committedInsts 1544563091 # Number of instructions committed
system.cpu.commit.committedOps 1723073903 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 660773834 # Number of memory references committed
system.cpu.commit.loads 485926779 # Number of loads committed
system.cpu.commit.membars 62 # Number of memory barriers committed
system.cpu.commit.branches 213462373 # Number of branches committed
system.cpu.commit.fp_insts 36 # Number of committed floating point instructions.
system.cpu.commit.int_insts 1536941881 # Number of committed integer instructions.
system.cpu.commit.function_calls 13665177 # Number of function calls committed.
system.cpu.commit.bw_lim_events 106750401 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 2923869159 # The number of ROB reads
system.cpu.rob.rob_writes 4445740607 # The number of ROB writes
system.cpu.timesIdled 753914 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 7726751 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1544563073 # Number of Instructions Simulated
system.cpu.committedOps 1723073885 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 1544563073 # Number of Instructions Simulated
system.cpu.cpi 0.593095 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.593095 # CPI: Total CPI of All Threads
system.cpu.ipc 1.686072 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.686072 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 9944305109 # number of integer regfile reads
system.cpu.int_regfile_writes 1936656463 # number of integer regfile writes
system.cpu.fp_regfile_reads 139 # number of floating regfile reads
system.cpu.fp_regfile_writes 147 # number of floating regfile writes
system.cpu.misc_regfile_reads 2896410924 # number of misc regfile reads
system.cpu.misc_regfile_writes 144 # number of misc regfile writes
system.cpu.icache.replacements 25 # number of replacements
system.cpu.icache.tagsinuse 627.053723 # Cycle average of tags in use
system.cpu.icache.total_refs 283464725 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 785 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 361101.560510 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 627.053723 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.306179 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.306179 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 283464725 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 283464725 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 283464725 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 283464725 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 283464725 # number of overall hits
system.cpu.icache.overall_hits::total 283464725 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1148 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1148 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1148 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1148 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1148 # number of overall misses
system.cpu.icache.overall_misses::total 1148 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 38598000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 38598000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 38598000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 38598000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 38598000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 38598000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 283465873 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 283465873 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 283465873 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 283465873 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 283465873 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 283465873 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 33621.951220 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 33621.951220 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 33621.951220 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 33621.951220 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 33621.951220 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 33621.951220 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 363 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 363 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 363 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 363 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 363 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 363 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 785 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 785 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 785 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 785 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 785 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 785 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27001000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 27001000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27001000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 27001000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27001000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 27001000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34396.178344 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34396.178344 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34396.178344 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 34396.178344 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34396.178344 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 34396.178344 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 9618836 # number of replacements
system.cpu.dcache.tagsinuse 4087.631943 # Cycle average of tags in use
system.cpu.dcache.total_refs 660703184 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 9622932 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 68.659239 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 3346369000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4087.631943 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.997957 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.997957 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 493290864 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 493290864 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 167412157 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 167412157 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 92 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 92 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 71 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 71 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 660703021 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 660703021 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 660703021 # number of overall hits
system.cpu.dcache.overall_hits::total 660703021 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 10330521 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 10330521 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 5173890 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 5173890 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 15504411 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 15504411 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 15504411 # number of overall misses
system.cpu.dcache.overall_misses::total 15504411 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 163224239500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 163224239500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 124852568337 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 124852568337 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 113500 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 113500 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 288076807837 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 288076807837 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 288076807837 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 288076807837 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 503621385 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 503621385 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 95 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 95 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 71 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 71 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 676207432 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 676207432 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 676207432 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 676207432 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020512 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.020512 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029979 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.029979 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.031579 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.031579 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.022928 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.022928 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.022928 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.022928 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15800.194346 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 15800.194346 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24131.276146 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 24131.276146 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37833.333333 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 37833.333333 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 18580.312908 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 18580.312908 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 18580.312908 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 18580.312908 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 200292336 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 119500 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 73738 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 8 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 2716.270254 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 14937.500000 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 3473805 # number of writebacks
system.cpu.dcache.writebacks::total 3473805 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2601467 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 2601467 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3280012 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 3280012 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 5881479 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 5881479 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 5881479 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 5881479 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7729054 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 7729054 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893878 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 1893878 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 9622932 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 9622932 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 9622932 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 9622932 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 78985396500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 78985396500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 42766465749 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 42766465749 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 121751862249 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 121751862249 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 121751862249 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 121751862249 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015347 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015347 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010974 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010974 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014231 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.014231 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014231 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.014231 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 10219.283822 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 10219.283822 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22581.425915 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22581.425915 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12652.262559 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 12652.262559 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12652.262559 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 12652.262559 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 2428308 # number of replacements
system.cpu.l2cache.tagsinuse 31141.553043 # Cycle average of tags in use
system.cpu.l2cache.total_refs 8745111 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 2458022 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 3.557784 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 77921850000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 14050.890908 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 15.916061 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 17074.746074 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.428799 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.000486 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.521080 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.950365 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 29 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 6116875 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 6116904 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 3473805 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 3473805 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 1062945 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 1062945 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 29 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 7179820 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 7179849 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 29 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 7179820 # number of overall hits
system.cpu.l2cache.overall_hits::total 7179849 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 756 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 1612178 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 1612934 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 830934 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 830934 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 756 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 2443112 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 2443868 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 756 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 2443112 # number of overall misses
system.cpu.l2cache.overall_misses::total 2443868 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 25970500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 55332029500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 55358000000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 28726375500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 28726375500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 25970500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 84058405000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 84084375500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 25970500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 84058405000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 84084375500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 785 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 7729053 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 7729838 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 3473805 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 3473805 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1893879 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 1893879 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 785 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 9622932 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 9623717 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 785 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 9622932 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 9623717 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.963057 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.208587 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.208663 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.438747 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.438747 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.963057 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.253884 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.253942 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.963057 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.253884 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.253942 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34352.513228 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34321.290515 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 34321.305149 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34571.187964 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34571.187964 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34352.513228 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34406.283871 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 34406.267237 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34352.513228 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34406.283871 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 34406.267237 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 36965500 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 4354 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8490.009187 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 1124163 # number of writebacks
system.cpu.l2cache.writebacks::total 1124163 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total 7 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 6 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 7 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 6 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 7 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 755 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1612172 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 1612927 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 830934 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 830934 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 755 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 2443106 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 2443861 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 755 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 2443106 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 2443861 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 23546000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 50285384000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 50308930000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 26141067500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 26141067500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23546000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 76426451500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 76449997500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23546000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 76426451500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 76449997500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.961783 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.208586 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.208662 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.438747 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.438747 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.961783 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.253884 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.253941 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.961783 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.253884 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.253941 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31186.754967 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31191.078868 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31191.076844 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31459.860230 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31459.860230 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31186.754967 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31282.495111 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31282.465533 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31186.754967 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31282.495111 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31282.465533 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
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